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Lowe output mode working

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Removed_REF_marker
erikkaashoek 5 years ago
parent acf2b1f180
commit 0da4d0a0e6
5 changed files with 63 additions and 32 deletions
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27
main.c
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@ -2395,19 +2395,20 @@ static const VNAShellCommand commands[] =
#endif
{ "y", cmd_y, CMD_WAIT_MUTEX },
{ "z", cmd_z, CMD_WAIT_MUTEX },
{ "i", cmd_i, 0 },
{ "v", cmd_v, 0 },
{ "a", cmd_a, 0 },
{ "b", cmd_b, 0 },
{ "t", cmd_t, 0 },
{ "e", cmd_e, 0 },
{ "s", cmd_s, 0 },
{ "m", cmd_m, 0 },
{ "p", cmd_p, 0 },
{ "w", cmd_w, 0 },
{ "o", cmd_o, 0 },
{ "d", cmd_d, 0 },
{ "f", cmd_f, 0 },
{ "i", cmd_i, CMD_WAIT_MUTEX },
{ "v", cmd_v, CMD_WAIT_MUTEX },
{ "a", cmd_a, CMD_WAIT_MUTEX },
{ "b", cmd_b, CMD_WAIT_MUTEX },
{ "t", cmd_t, CMD_WAIT_MUTEX },
{ "e", cmd_e, CMD_WAIT_MUTEX },
{ "s", cmd_s, CMD_WAIT_MUTEX },
{ "m", cmd_m, CMD_WAIT_MUTEX },
{ "p", cmd_p, CMD_WAIT_MUTEX },
{ "w", cmd_w, CMD_WAIT_MUTEX },
{ "o", cmd_o, CMD_WAIT_MUTEX },
{ "d", cmd_d, CMD_WAIT_MUTEX },
{ "f", cmd_f, CMD_WAIT_MUTEX },
{ "g", cmd_g, CMD_WAIT_MUTEX },
// { "g", cmd_g, 0 },
#ifdef __ULTRA_SA__
{ "x", cmd_x, 0 },

2
nanovna.h
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@ -1069,6 +1069,8 @@ extern int SI4463_R;
void Si4463_set_refer(int ref);
void SI446x_set_AGC_LNA(uint8_t v);
void SI4463_set_gpio(int i, int s);
#define GPIO_HIGH 3
#define GPIO_LOW 2
void SI4463_start_tx(uint8_t CHANNEL);
void SI4463_init_rx(void);
void SI4463_init_tx(void);

11
sa_cmd.c
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@ -569,8 +569,9 @@ VNA_SHELL_FUNCTION(cmd_m)
VNA_SHELL_FUNCTION(cmd_p)
{
(void)argc;
return;
int p = my_atoi(argv[0]);
SI4463_set_output_level(p);
return;
int a = my_atoi(argv[1]);
if (p==5)
set_attenuation(-a);
@ -581,6 +582,14 @@ return;
set_refer_output(a);
}
VNA_SHELL_FUNCTION(cmd_g)
{
(void)argc;
int p = my_atoi(argv[0]);
int a = my_atoi(argv[1]);
SI4463_set_gpio(p,a);
}
VNA_SHELL_FUNCTION(cmd_w)
{
(void)argc;

2
sa_core.c
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@ -1994,7 +1994,7 @@ modulation_again:
#endif
#ifdef __ADF4351__
// START_PROFILE;
if (setting.mode == M_LOW) {
if (MODE_LOW(setting.mode)) {
if (config.frequency_IF2 != 0) {
set_freq (ADF4351_LO2, config.frequency_IF2 - local_IF); // Down from IF2 to fixed second IF in Ultra SA mode
local_IF = config.frequency_IF2;

53
si4432.c
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@ -1004,12 +1004,12 @@ void ADF4351_force_refresh(void) {
uint32_t ADF4351_set_frequency(int channel, uint32_t freq, int drive) // freq / 10Hz
{
// freq -= 71000;
// SI4463_set_gpio(3,1);
// SI4463_set_gpio(3,GPIO_HIGH);
// uint32_t offs = ((freq / 1000)* ( 0) )/ 1000;
uint32_t offs = 0;
uint32_t actual_freq = ADF4351_prep_frequency(channel,freq + offs, drive);
// SI4463_set_gpio(3,0);
// SI4463_set_gpio(3,GPIO_LOW);
if (actual_freq != prev_actual_freq) {
//START_PROFILE;
ADF4351_frequency_changed = true;
@ -1179,7 +1179,7 @@ static float SI4463_step_size = 100; // Will be recalculated once used
static uint8_t SI4463_channel = 0;
static uint8_t SI4463_in_tx_mode = false;
int SI4463_R = 5;
static int SI4463_output_level = 0x20;
static si446x_state_t SI4463_get_state(void);
static void SI4463_set_state(si446x_state_t);
@ -1370,21 +1370,26 @@ static uint8_t gpio_state[4] = { 7,8,0,0 };
void SI4463_refresh_gpio(void)
{
uint8_t data[] = {
0x13, 0x07, 0x08, gpio_state[2], gpio_state[3]
uint8_t data[] =
{
0x11, 0x00, 0x01, 0x01, 0x40 // GLOBAL_CLK_CFG Enable divided clock
};
SI4463_do_api(data, sizeof(data), NULL, 0);
uint8_t data2[] =
{
0x13, gpio_state[0], gpio_state[1], gpio_state[2], gpio_state[3], 0, 0, 0
};
SI4463_do_api(data2, sizeof(data2), NULL, 0);
}
void SI4463_set_gpio(int i, int s)
{
if (s)
gpio_state[i] = 3;
else
gpio_state[i] = 2;
gpio_state[i] = s;
SI4463_refresh_gpio();
}
#if 0
static void SI4463_clear_FIFO(void)
{
// 'static const' saves 20 bytes of flash here, but uses 2 bytes of RAM
@ -1394,7 +1399,14 @@ static void SI4463_clear_FIFO(void)
};
SI4463_do_api((uint8_t*)clearFifo, sizeof(clearFifo), NULL, 0);
}
#endif
void SI4463_set_output_level(int t)
{
SI4463_output_level = t;
if (SI4463_in_tx_mode)
SI4463_start_tx(0); // Refresh output level
}
void SI4463_start_tx(uint8_t CHANNEL)
{
volatile si446x_state_t s;
@ -1409,7 +1421,7 @@ void SI4463_start_tx(uint8_t CHANNEL)
}
}
#endif
#if 0
#if 1
{
uint8_t data[] =
{
@ -1419,13 +1431,13 @@ void SI4463_start_tx(uint8_t CHANNEL)
SI4463_do_api(data, sizeof(data), NULL, 0);
}
#endif
#if 0
#if 1
{
uint8_t data[] =
{
0x11, 0x22, 0x04, 0x00,
0x05, // Fine PA mode and switched current PA
0x20, // Level
SI4463_output_level, // Level
0x00, // Duty
0x00 // Ramp
};
@ -1464,8 +1476,9 @@ void SI4463_start_rx(uint8_t CHANNEL)
volatile si446x_state_t s = SI4463_get_state();
if (s == SI446X_STATE_TX){
SI4463_set_state(SI446X_STATE_READY);
my_microsecond_delay(200);
}
SI4463_refresh_gpio();
#if 0
{
uint8_t data[] =
{
@ -1474,6 +1487,7 @@ void SI4463_start_rx(uint8_t CHANNEL)
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
#endif
uint8_t data[] = {
SI446X_CMD_ID_START_RX,
CHANNEL,
@ -2053,7 +2067,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
{
(void) step_size;
// SI4463_set_gpio(3,1);
// SI4463_set_gpio(3,GPIO_HIGH);
int S = 4 ; // Aprox 100 Hz channels
SI4463_channel = 0;
@ -2105,7 +2119,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
};
SI4463_do_api(data, sizeof(data), NULL, 0);
SI4463_frequency_changed = true;
// SI4463_set_gpio(3,0);
// SI4463_set_gpio(3,GPIO_LOW);
return;
}
refresh_count=0;
@ -2187,7 +2201,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
}
#endif
SI4463_wait_for_cts();
// SI4463_set_gpio(3,0);
// SI4463_set_gpio(3,GPIO_LOW);
SI4463_frequency_changed = true;
}
@ -2227,16 +2241,20 @@ again:
prev_band = -1; // 433MHz
}
#if 0
#undef RADIO_CONFIG_H_
#include "radio_config_Si4468_tx.h"
static const uint8_t SI4463_config_tx[] =
RADIO_CONFIGURATION_DATA_ARRAY;
#endif
void SI4463_init_tx(void)
{
#if 0
reset:
SI_SDN_LOW;
my_microsecond_delay(100);
@ -2250,6 +2268,7 @@ reset:
SI4463_do_api((void *)&SI4463_config_tx[i+1], SI4463_config_tx[i], NULL, 0);
i += SI4463_config_tx[i];
}
#endif
#endif
SI4463_start_tx(0);
#if 0

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