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Basic High Output mode working

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Removed_REF_marker
erikkaashoek 5 years ago
parent 22fe92f79b
commit acf2b1f180
5 changed files with 736 additions and 145 deletions
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3
main.c
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@ -2842,9 +2842,6 @@ int main(void)
i2sObjectInit(&I2SD2);
i2sStart(&I2SD2, &i2sconfig);
i2sStartExchange(&I2SD2);
#endif
#ifdef __SI4463__
SI4463_init();
#endif
area_height = AREA_HEIGHT_NORMAL;
ui_init();

4
nanovna.h
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@ -1068,6 +1068,10 @@ enum {
extern int SI4463_R;
void Si4463_set_refer(int ref);
void SI446x_set_AGC_LNA(uint8_t v);
void SI4463_set_gpio(int i, int s);
void SI4463_start_tx(uint8_t CHANNEL);
void SI4463_init_rx(void);
void SI4463_init_tx(void);
#endif
void set_R(int f);

524
radio_config_Si4468_tx.h
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@ -0,0 +1,524 @@
/*! @file radio_config.h
* @brief This file contains the automatically generated
* configurations.
*
* @n WDS GUI Version: 3.2.11.0
* @n Device: Si4468 Rev.: A2
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2017 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef RADIO_CONFIG_H_
#define RADIO_CONFIG_H_
// USER DEFINED PARAMETERS
// Define your own parameters here
// INPUT DATA
/*
// Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15
// MOD_type: 1 Rsymb(sps): 2000 Fdev(Hz): 20000 RXBW(Hz): 200000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
// RF Freq.(MHz): 940 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 9 Hi_pfm_div: 1
// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0
//
// # RX IF frequency is -406250 Hz
// # WB filter 1 (BW = 198.40 kHz); NB-filter 1 (BW = 198.40 kHz)
//
// Modulation index: 20
*/
// CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
// CONFIGURATION COMMANDS
/*
// Command: RF_POWER_UP
// Description: Command to power-up the device and select the operational mode and functionality.
*/
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80
/*
// Command: RF_GPIO_PIN_CFG
// Description: Configures the GPIO pins.
*/
#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x44, 0x20, 0x00, 0x00, 0x00
/*
// Set properties: RF_GLOBAL_XO_TUNE_2
// Number of properties: 2
// Group ID: 0x00
// Start ID: 0x00
// Default values: 0x40, 0x00,
// Descriptions:
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
// GLOBAL_CLK_CFG - Clock configuration options.
*/
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x40
/*
// Set properties: RF_GLOBAL_CONFIG_1
// Number of properties: 1
// Group ID: 0x00
// Start ID: 0x03
// Default values: 0x20,
// Descriptions:
// GLOBAL_CONFIG - Global configuration settings.
*/
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20
/*
// Set properties: RF_INT_CTL_ENABLE_1
// Number of properties: 1
// Group ID: 0x01
// Start ID: 0x00
// Default values: 0x04,
// Descriptions:
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
*/
#define RF_INT_CTL_ENABLE_1 0x11, 0x01, 0x01, 0x00, 0x00
/*
// Set properties: RF_FRR_CTL_A_MODE_4
// Number of properties: 4
// Group ID: 0x02
// Start ID: 0x00
// Default values: 0x01, 0x02, 0x09, 0x00,
// Descriptions:
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
*/
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00
/*
// Set properties: RF_PREAMBLE_CONFIG_1
// Number of properties: 1
// Group ID: 0x10
// Start ID: 0x04
// Default values: 0x21,
// Descriptions:
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
*/
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21
/*
// Set properties: RF_MODEM_MOD_TYPE_12
// Number of properties: 12
// Group ID: 0x20
// Start ID: 0x00
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
// Descriptions:
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x49, 0x00, 0x07, 0x00, 0x4E, 0x20, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00
/*
// Set properties: RF_MODEM_FREQ_DEV_0_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x0C
// Default values: 0xD3,
// Descriptions:
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x00
/*
// Set properties: RF_MODEM_TX_RAMP_DELAY_12
// Number of properties: 12
// Group ID: 0x20
// Start ID: 0x18
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B,
// Descriptions:
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
// MODEM_MDM_CTRL - MDM control.
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections.
// MODEM_IFPKD_THRESHOLDS -
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
*/
#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x00, 0x80, 0x08, 0x03, 0xC0, 0x00, 0x1A, 0x20, 0x0C, 0xE8, 0x00, 0x66
/*
// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12
// Number of properties: 12
// Group ID: 0x20
// Start ID: 0x24
// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69,
// Descriptions:
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
// MODEM_BCR_GEAR - RX BCR loop gear control.
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls.
// MODEM_AFC_GEAR - RX AFC loop gear control.
// MODEM_AFC_WAIT - RX AFC loop wait time control.
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
*/
#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x05, 0x0A, 0x8E, 0x02, 0x83, 0x00, 0xC2, 0x00, 0x54, 0x23, 0x00, 0x0A
/*
// Set properties: RF_MODEM_AFC_LIMITER_1_3
// Number of properties: 3
// Group ID: 0x20
// Start ID: 0x30
// Default values: 0x00, 0x40, 0xA0,
// Descriptions:
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
*/
#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x3F, 0xB3, 0x80
/*
// Set properties: RF_MODEM_AGC_CONTROL_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x35
// Default values: 0xE0,
// Descriptions:
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
*/
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x60
/*
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12
// Number of properties: 12
// Group ID: 0x20
// Start ID: 0x38
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03,
// Descriptions:
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector.
// MODEM_OOK_CNT1 - OOK control.
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
*/
#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x16, 0x16, 0x80, 0x02, 0xFF, 0xFF, 0x00, 0x28, 0x0C, 0x84, 0x21
/*
// Set properties: RF_MODEM_RAW_CONTROL_5
// Number of properties: 5
// Group ID: 0x20
// Start ID: 0x45
// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80,
// Descriptions:
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
*/
#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x8C, 0x01, 0x89, 0x01, 0x00
/*
// Set properties: RF_MODEM_RSSI_JUMP_THRESH_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x4B
// Default values: 0x0C,
// Descriptions:
// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold.
*/
#define RF_MODEM_RSSI_JUMP_THRESH_1 0x11, 0x20, 0x01, 0x4B, 0x06
/*
// Set properties: RF_MODEM_RSSI_CONTROL2_2
// Number of properties: 2
// Group ID: 0x20
// Start ID: 0x4D
// Default values: 0x00, 0x40,
// Descriptions:
// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
// MODEM_RSSI_COMP - RSSI compensation value.
*/
#define RF_MODEM_RSSI_CONTROL2_2 0x11, 0x20, 0x02, 0x4D, 0x18, 0x40
/*
// Set properties: RF_MODEM_RAW_SEARCH2_2
// Number of properties: 2
// Group ID: 0x20
// Start ID: 0x50
// Default values: 0x00, 0x08,
// Descriptions:
// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors.
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
*/
#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08
/*
// Set properties: RF_MODEM_SPIKE_DET_2
// Number of properties: 2
// Group ID: 0x20
// Start ID: 0x54
// Default values: 0x00, 0x00,
// Descriptions:
// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
*/
#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
/*
// Set properties: RF_MODEM_RSSI_MUTE_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x57
// Default values: 0x00,
// Descriptions:
// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts.
*/
#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00
/*
// Set properties: RF_MODEM_DSA_CTRL1_5
// Number of properties: 5
// Group ID: 0x20
// Start ID: 0x5B
// Default values: 0x00, 0x00, 0x00, 0x00, 0x00,
// Descriptions:
// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm.
// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm.
// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
*/
#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x10, 0x78, 0x20
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
// Number of properties: 12
// Group ID: 0x21
// Start ID: 0x00
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
// Descriptions:
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
// Number of properties: 12
// Group ID: 0x21
// Start ID: 0x0C
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
// Descriptions:
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
/*
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
// Number of properties: 12
// Group ID: 0x21
// Start ID: 0x18
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
// Descriptions:
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
/*
// Set properties: RF_PA_MODE_4
// Number of properties: 4
// Group ID: 0x22
// Start ID: 0x00
// Default values: 0x08, 0x7F, 0x00, 0x5D,
// Descriptions:
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
// PA_PWR_LVL - Configuration of PA output power level.
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
// PA_TC - Configuration of PA ramping parameters.
*/
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x10, 0x00, 0x5F
/*
// Set properties: RF_SYNTH_PFDCP_CPFF_7
// Number of properties: 7
// Group ID: 0x23
// Start ID: 0x00
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
// Descriptions:
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
*/
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
/*
// Set properties: RF_FREQ_CONTROL_INTE_8
// Number of properties: 8
// Group ID: 0x40
// Start ID: 0x00
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
// Descriptions:
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x47, 0x0A, 0x76, 0x27, 0x27, 0x62, 0x20, 0xFF
// AUTOMATICALLY GENERATED CODE!
// DO NOT EDIT/MODIFY BELOW THIS LINE!
// --------------------------------------------
#ifndef FIRMWARE_LOAD_COMPILE
#define RADIO_CONFIGURATION_DATA_ARRAY { \
0x07, RF_POWER_UP, \
0x08, RF_GPIO_PIN_CFG, \
0x06, RF_GLOBAL_XO_TUNE_2, \
0x05, RF_GLOBAL_CONFIG_1, \
0x05, RF_INT_CTL_ENABLE_1, \
0x08, RF_FRR_CTL_A_MODE_4, \
0x05, RF_PREAMBLE_CONFIG_1, \
0x10, RF_MODEM_MOD_TYPE_12, \
0x05, RF_MODEM_FREQ_DEV_0_1, \
0x10, RF_MODEM_TX_RAMP_DELAY_12, \
0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \
0x07, RF_MODEM_AFC_LIMITER_1_3, \
0x05, RF_MODEM_AGC_CONTROL_1, \
0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \
0x09, RF_MODEM_RAW_CONTROL_5, \
0x05, RF_MODEM_RSSI_JUMP_THRESH_1, \
0x06, RF_MODEM_RSSI_CONTROL2_2, \
0x06, RF_MODEM_RAW_SEARCH2_2, \
0x06, RF_MODEM_SPIKE_DET_2, \
0x05, RF_MODEM_RSSI_MUTE_1, \
0x09, RF_MODEM_DSA_CTRL1_5, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
0x08, RF_PA_MODE_4, \
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
0x0C, RF_FREQ_CONTROL_INTE_8, \
0x00 \
}
#else
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
#endif
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
#error "This property must be defined!"
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
#endif
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
#endif
#define RADIO_CONFIGURATION_DATA { \
Radio_Configuration_Data_Array, \
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
}
#endif /* RADIO_CONFIG_H_ */

30
sa_core.c
Unescape View File

@ -663,7 +663,7 @@ void set_harmonic(int h)
void set_step_delay(int d) // override RSSI measurement delay or set to one of three auto modes
{
if ((3 <= d && d < 250) || d > 30000) // values 0 (normal scan), 1 (precise scan) and 2(fast scan) have special meaning and are auto calculated
if ((3 <= d && d < 100) || d > 30000) // values 0 (normal scan), 1 (precise scan) and 2(fast scan) have special meaning and are auto calculated
return;
if (d <3) {
setting.step_delay_mode = d;
@ -997,9 +997,9 @@ void calculate_step_delay(void)
#endif
#endif
#ifdef __SI4463__
if (actual_rbw_x10 >= 8500) { SI4432_step_delay = 500; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 3000) { SI4432_step_delay = 500; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 1000) { SI4432_step_delay = 800; SI4432_offset_delay = 100; }
if (actual_rbw_x10 >= 8500) { SI4432_step_delay = 300; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 3000) { SI4432_step_delay = 300; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 1000) { SI4432_step_delay = 300; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 300) { SI4432_step_delay = 1000; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 100) { SI4432_step_delay = 1400; SI4432_offset_delay = 100; }
else if (actual_rbw_x10 >= 30) { SI4432_step_delay = 2500; SI4432_offset_delay = 100; }
@ -1128,6 +1128,10 @@ void setupSA(void)
PE4302_init();
PE4302_Write_Byte(0);
#endif
#ifdef __SI4463__
SI4463_init_rx(); // Must be before ADF4351_setup!!!!
#endif
ADF4351_Setup();
#if 0 // Measure fast scan time
setting.sweep_time_us = 0;
@ -1153,8 +1157,8 @@ static uint32_t old_frequency_step;
void set_freq(int V, unsigned long freq) // translate the requested frequency into a setting of the SI4432
{
// if (old_freq[V] == freq && setting.frequency_step == old_frequency_step) // Do not change HW if not needed
// return;
if (old_freq[V] == freq && setting.frequency_step == old_frequency_step) // Do not change HW if not needed
return;
#ifdef __SI4432__
if (V <= 1) {
SI4432_Sel = V;
@ -1294,6 +1298,9 @@ case M_ULTRA:
} else {
set_switch_receive();
}
#endif
#ifdef __SI4463__
SI4463_init_rx(); // Must be before ADF4351_setup!!!!
#endif
set_AGC_LNA();
@ -1323,6 +1330,9 @@ mute:
} else {
set_switch_receive();
}
#endif
#ifdef __SI4463__
SI4463_init_rx();
#endif
set_AGC_LNA();
@ -1347,6 +1357,9 @@ case M_GENLOW: // Mixed output from 0
set_switch_off();
SI4432_Transmit(12); // Fix LO drive a 10dBm
}
#endif
#ifdef __SI4468__
SI4463_init_tx();
#endif
break;
case M_GENHIGH: // Direct output from 1
@ -1364,6 +1377,9 @@ case M_GENHIGH: // Direct output from 1
set_switch_transmit();
}
SI4432_Transmit(setting.drive);
#endif
#ifdef __SI4468__
SI4463_init_tx();
#endif
break;
}
@ -2018,7 +2034,7 @@ modulation_again:
#endif
if (!tracking)
set_freq (SI4463_RX, local_IF); // compensate ADF error with SI446x when not in tracking mode
} else if (setting.mode == M_HIGH) {
} else if (setting.mode == M_HIGH || setting.mode == M_GENHIGH) {
set_freq (SI4463_RX, lf); // sweep RX, local_IF = 0 in high mode
}
// STOP_PROFILE;

320
si4432.c
Unescape View File

@ -43,7 +43,7 @@
// Hardware or software SPI use
#ifdef USE_HARDWARE_SPI_MODE
#define SI4432_SPI SPI1
#define SI4432_SPI_SPEED SPI_BR_DIV16
#define SI4432_SPI_SPEED SPI_BR_DIV8
//#define SI4432_SPI_SPEED SPI_BR_DIV64
static uint32_t old_spi_settings;
#else
@ -966,24 +966,20 @@ void ADF4351_Setup(void)
void ADF4351_WriteRegister32(int channel, const uint32_t value)
{
for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF);
// my_microsecond_delay(1);
palSetPad(GPIOB, ADF4351_LE[channel]);
my_microsecond_delay(1); // Must
palClearPad(GPIOB, ADF4351_LE[channel]);
// my_microsecond_delay(1); // Not needed
}
void ADF4351_Set(int channel)
{
set_SPI_mode(SPI_MODE_SI);
my_microsecond_delay(1);
// my_microsecond_delay(1);
palClearPad(GPIOB, ADF4351_LE[channel]);
my_microsecond_delay(1);
// my_microsecond_delay(1);
for (int i = 5; i >= 0; i--) {
ADF4351_WriteRegister32(channel, registers[i]);
// if (debug) Serial.println(registers[i],HEX);
}
}
@ -1008,10 +1004,12 @@ void ADF4351_force_refresh(void) {
uint32_t ADF4351_set_frequency(int channel, uint32_t freq, int drive) // freq / 10Hz
{
// freq -= 71000;
// SI4463_set_gpio(3,1);
// uint32_t offs = ((freq / 1000)* ( 0) )/ 1000;
uint32_t offs = 0;
uint32_t actual_freq = ADF4351_prep_frequency(channel,freq + offs, drive);
// SI4463_set_gpio(3,0);
if (actual_freq != prev_actual_freq) {
//START_PROFILE;
ADF4351_frequency_changed = true;
@ -1179,9 +1177,14 @@ static int64_t SI4463_outdiv = -1;
static uint32_t SI4463_prev_freq = 0;
static float SI4463_step_size = 100; // Will be recalculated once used
static uint8_t SI4463_channel = 0;
static uint8_t SI4463_in_tx_mode = false;
int SI4463_R = 5;
static si446x_state_t SI4463_get_state(void);
static void SI4463_set_state(si446x_state_t);
#define MIN_DELAY 2
#define my_deleted_delay(T)
@ -1363,6 +1366,25 @@ static void SI4463_set_state(si446x_state_t newState)
SI4463_do_api(data, sizeof(data), NULL, 0);
}
static uint8_t gpio_state[4] = { 7,8,0,0 };
void SI4463_refresh_gpio(void)
{
uint8_t data[] = {
0x13, 0x07, 0x08, gpio_state[2], gpio_state[3]
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
void SI4463_set_gpio(int i, int s)
{
if (s)
gpio_state[i] = 3;
else
gpio_state[i] = 2;
SI4463_refresh_gpio();
}
static void SI4463_clear_FIFO(void)
{
// 'static const' saves 20 bytes of flash here, but uses 2 bytes of RAM
@ -1373,8 +1395,85 @@ static void SI4463_clear_FIFO(void)
SI4463_do_api((uint8_t*)clearFifo, sizeof(clearFifo), NULL, 0);
}
void SI4463_start_tx(uint8_t CHANNEL)
{
volatile si446x_state_t s;
#if 0
s = SI4463_get_state();
if (s == SI446X_STATE_RX){
SI4463_set_state(SI446X_STATE_READY);
my_microsecond_delay(200);
s = SI4463_get_state();
if (s != SI446X_STATE_READY){
my_microsecond_delay(1000);
}
}
#endif
#if 0
{
uint8_t data[] =
{
0x11, 0x20, 0x01, 0x00,
0x00, // CW mode
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
#endif
#if 0
{
uint8_t data[] =
{
0x11, 0x22, 0x04, 0x00,
0x05, // Fine PA mode and switched current PA
0x20, // Level
0x00, // Duty
0x00 // Ramp
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
#endif
retry:
{
uint8_t data[] =
{
SI446X_CMD_ID_START_TX,
CHANNEL,
0, // Stay in TX state
0, // TX len
0, // TX len
0,// TX delay
0// Num repeat
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
SI4463_in_tx_mode = true;
my_microsecond_delay(1000);
#if 0
s = SI4463_get_state();
if (s != SI446X_STATE_TX){
my_microsecond_delay(1000);
goto retry;
}
#endif
}
void SI4463_start_rx(uint8_t CHANNEL)
{
volatile si446x_state_t s = SI4463_get_state();
if (s == SI446X_STATE_TX){
SI4463_set_state(SI446X_STATE_READY);
my_microsecond_delay(200);
}
{
uint8_t data[] =
{
0x11, 0x20, 0x01, 0x00,
0x0A, // Restore 2FSK mode
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
uint8_t data[] = {
SI446X_CMD_ID_START_RX,
CHANNEL,
@ -1387,18 +1486,19 @@ void SI4463_start_rx(uint8_t CHANNEL)
};
retry:
SI4463_do_api(data, sizeof(data), NULL, 0);
// my_microsecond_delay(SI4432_offset_delay);
#if 0
// my_microsecond_delay(15000);
si446x_state_t s = getState();
si446x_state_t s = SI4463_get_state();
if (s != SI446X_STATE_RX) {
my_microsecond_delay(1000);
goto retry;
}
#endif
SI4463_in_tx_mode = false;
}
void SI4463_short_start_rx(void)
{
uint8_t data[] = {
@ -1406,6 +1506,7 @@ void SI4463_short_start_rx(void)
};
retry:
SI4463_do_api(data, sizeof(data), NULL, 0);
SI4463_in_tx_mode = false;
}
void SI4463_clear_int_status()
@ -1490,7 +1591,7 @@ uint8_t getFRR(uint8_t reg)
}
// Get current radio state
si446x_state_t getState(void)
static si446x_state_t SI4463_get_state(void)
{
#if 0
#if 0
@ -1521,15 +1622,6 @@ again:
return (si446x_state_t)state;
}
// Set new state
void setState(si446x_state_t newState)
{
uint8_t data[] = {
SI446X_CMD_CHANGE_STATE,
newState
};
SI4463_do_api(data, sizeof(data), NULL, 0);
}
void set_RSSI_comp(void)
{
@ -1925,7 +2017,9 @@ static int prev_band = -1;
uint16_t SI4463_force_RBW(int f)
{
setState(SI446X_STATE_READY);
if (SI4463_in_tx_mode)
return(0);
SI4463_set_state(SI446X_STATE_READY);
uint8_t *config = RBW_choices[f].reg;
uint16_t i=0;
while(config[i] != 0)
@ -1959,17 +2053,10 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
{
(void) step_size;
// SI4463_set_gpio(3,1);
int S = 4 ; // Aprox 100 Hz channels
// SI4463_step_size = S * (Npresc ? 2000000*freq_xco : 4000000*freq_xco) / ((2<<18) * SI4463_outdiv);
// SI4463_channel = (freq - SI4463_prev_freq) / SI4463_step_size; // Recalculate in case step size changed
// if (freq < SI4463_prev_freq || freq > SI4463_prev_freq + 255 * SI4463_step_size ) {
SI4463_channel = 0;
// SI4463_prev_freq = freq - SI4463_channel * SI4463_step_size;
#if 1
if (freq >= 822000000 && freq <= 1140000000) { // till 1140MHz
SI4463_band = 0;
SI4463_outdiv = 4;
@ -1997,40 +2084,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
int32_t R = (freq * SI4463_outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco) - 1; // R between 0x00 and 0x7f (127)
int64_t MOD = 524288;
int32_t F = ((freq * SI4463_outdiv*MOD) / (Npresc ? 2*freq_xco : 4*freq_xco)) - R*MOD;
volatile uint32_t actual_freq = (R*MOD + F) * (Npresc ? 2*freq_xco : 4*freq_xco)/ SI4463_outdiv/MOD;
#else
#define freq_xco 26.0
float RFout=freq/1000000.0; // To MHz
if (RFout >= 822 && RFout <= 1140) { // till 1140MHz
SI4463_band = 0;
SI4463_outdiv = 4;
#if 0 // band 4 does not function
} else if (RFout >= 568 && RFout <= 758 ) { // works till 758MHz
SI4463_band = 4;
SI4463_outdiv = 6;
#endif
} else if (RFout >= 420 && RFout <= 568) { // works till 568MHz
SI4463_band = 2;
SI4463_outdiv = 8;
} else if (RFout >= 329 && RFout <= 454) { // works till 454MHz
SI4463_band = 1;
SI4463_outdiv = 10;
} else if (RFout >= 274 && RFout <= 339) { // to 339
SI4463_band = 3;
SI4463_outdiv = 12;
} else if (RFout >= 136 && RFout <= 190){ // 136 { // To 190
SI4463_band = 5;
SI4463_outdiv = 24;
}
if (SI4463_band == -1)
return;
int32_t R = (RFout * SI4463_outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco) - 1; // R between 0x00 and 0x7f (127)
float MOD = 524288.0;
int32_t F = (((RFout * SI4463_outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco)) - R) * MOD;
volatile uint32_t actual_freq = (R+((float)F)/MOD) * (Npresc ? 2*freq_xco : 4*freq_xco)*1000000 / SI4463_outdiv;
#endif
uint32_t actual_freq = (R*MOD + F) * (Npresc ? 2*freq_xco : 4*freq_xco)/ SI4463_outdiv/MOD;
if (actual_freq < freq - 100 || actual_freq > freq + 100 ){
while(1)
my_microsecond_delay(10);
@ -2039,7 +2093,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
while(1)
my_microsecond_delay(10);
}
if (FALSE && /* refresh_count++ < 20 && */(SI4463_band == prev_band) /* && !ADF4351_frequency_changed */ ) {
if ((SI4463_band == prev_band)) {
uint8_t data[] = {
0x36,
(uint8_t) R, // R data[4]
@ -2050,27 +2104,12 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
0x66
};
SI4463_do_api(data, sizeof(data), NULL, 0);
#if 0
// SI4463_short_start_rx();
my_microsecond_delay(200);
si446x_state_t s = getState();
if (s != SI446X_STATE_RX) {
SI4463_short_start_rx();
osalThreadSleepMilliseconds(1000);
#if 0
si446x_state_t s = getState();
if (s != SI446X_STATE_RX) {
osalThreadSleepMilliseconds(3000);
goto retry;
}
#endif
}
#endif
SI4463_frequency_changed = true;
// SI4463_set_gpio(3,0);
return;
}
refresh_count=0;
setState(SI446X_STATE_READY);
SI4463_set_state(SI446X_STATE_READY);
my_deleted_delay(100);
/*
@ -2119,7 +2158,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
0x10 + (uint8_t)(SI4463_band + (Npresc ? 0x08 : 0)) // 0x08 for high performance mode, 0x10 to skip recal
};
SI4463_do_api(data2, sizeof(data2), NULL, 0);
my_microsecond_delay(30000);
// my_microsecond_delay(30000);
prev_band = SI4463_band;
}
@ -2128,26 +2167,31 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size)
// SI4463_clear_int_status();
retry:
SI4463_start_rx(SI4463_channel);
#if 1
si446x_state_t s = getState();
if (s != SI446X_STATE_RX) {
if (SI4463_in_tx_mode)
SI4463_start_tx(0);
else {
SI4463_start_rx(SI4463_channel);
osalThreadSleepMilliseconds(1000);
#if 1
si446x_state_t s = getState();
si446x_state_t s = SI4463_get_state();
if (s != SI446X_STATE_RX) {
osalThreadSleepMilliseconds(3000);
goto retry;
}
SI4463_start_rx(SI4463_channel);
osalThreadSleepMilliseconds(1000);
#if 1
si446x_state_t s = SI4463_get_state();
if (s != SI446X_STATE_RX) {
osalThreadSleepMilliseconds(3000);
goto retry;
}
#endif
}
}
#endif
SI4463_wait_for_cts();
// SI4463_set_gpio(3,0);
SI4463_frequency_changed = true;
}
void SI4463_init(void)
void SI4463_init_rx(void)
{
reset:
SI_SDN_LOW;
@ -2156,59 +2200,67 @@ reset:
my_microsecond_delay(1000);
SI_SDN_LOW;
my_microsecond_delay(1000);
#if 0
ili9341_set_foreground(LCD_BRIGHT_COLOR_GREEN);
while (!SI4463_READ_CTS) {
ili9341_drawstring_7x13("Waiting", 50, 200);
my_microsecond_delay(100);
#ifdef __SI4468__
for(uint16_t i=0;i<sizeof(SI4468_config);i++)
{
SI4463_do_api((void *)&SI4468_config[i+1], SI4468_config[i], NULL, 0);
i += SI4468_config[i];
}
ili9341_drawstring_7x13("Proceed", 50, 200);
#endif
SI4463_start_rx(SI4463_channel);
#if 0
for(uint16_t i=0;i<sizeof(SI4463_config);i++)
{
SI4463_do_api((void *)&SI4463_config[i+1], SI4463_config[i], NULL, 0);
i += SI4463_config[i];
my_microsecond_delay(200);
volatile si446x_state_t s ;
}
#endif
#ifdef __SI4468__
uint16_t i=0;
#if 0
SI4463_do_api((void *)&SI4468_config[i+1], SI4468_config[i], NULL, 0);
i += SI4468_config[i]+1;
my_microsecond_delay(2000000);
SI4463_do_api((void *)&SI4468_config[i+1], SI4468_config[i], NULL, 0);
i += SI4468_config[i]+1;
//my_microsecond_delay(2000000);
SI4463_do_api((void *)&SI4468_config[i+1], SI4468_config[i], NULL, 0);
i += SI4468_config[i]+1;
//my_microsecond_delay(1000000);
again:
Si446x_getInfo(&SI4463_info);
// s = SI4463_get_state();
// SI4463_clear_int_status();
my_microsecond_delay(15000);
s = SI4463_get_state();
if (s != SI446X_STATE_RX) {
ili9341_drawstring_7x13("Waiting for RX", 50, 200);
osalThreadSleepMilliseconds(3000);
goto reset;
}
ili9341_drawstring_7x13("Waiting ready ", 50, 200);
#endif
for(;i<sizeof(SI4468_config);i++)
{
SI4463_do_api((void *)&SI4468_config[i+1], SI4468_config[i], NULL, 0);
i += SI4468_config[i];
my_deleted_delay(2000);
prev_band = -1; // 433MHz
}
#endif
// SI4463_do_api((void *)&SI4463_config[1], SI4463_config[0], NULL, 0);
// SI4463_set_freq(433800000,1000);
#undef RADIO_CONFIG_H_
#include "radio_config_Si4468_tx.h"
//#define SI446X_ADC_SPEED 10
// RSSI = getADC(SI446X_ADC_CONV_BATT, (SI446X_ADC_SPEED<<4), 2);
#if 1
static const uint8_t SI4463_config_tx[] =
RADIO_CONFIGURATION_DATA_ARRAY;
void SI4463_init_tx(void)
{
reset:
SI_SDN_LOW;
my_microsecond_delay(100);
SI_SDN_HIGH;
my_microsecond_delay(1000);
SI_SDN_LOW;
my_microsecond_delay(1000);
#ifdef __SI4468__
for(uint16_t i=0;i<sizeof(SI4463_config_tx);i++)
{
SI4463_do_api((void *)&SI4463_config_tx[i+1], SI4463_config_tx[i], NULL, 0);
i += SI4463_config_tx[i];
}
#endif
SI4463_start_tx(0);
#if 0
volatile si446x_state_t s ;
again:
Si446x_getInfo(&SI4463_info);
// s = getState();
// s = SI4463_get_state();
// SI4463_clear_int_status();
SI4463_start_rx(SI4463_channel);
my_microsecond_delay(15000);
s = getState();
s = SI4463_get_state();
if (s != SI446X_STATE_RX) {
ili9341_drawstring_7x13("Waiting for RX", 50, 200);
osalThreadSleepMilliseconds(3000);
@ -2216,11 +2268,9 @@ again:
}
ili9341_drawstring_7x13("Waiting ready ", 50, 200);
#endif
// Si446x_RSSI();
// goto again;
prev_band = -1; // 433MHz
}
#pragma GCC pop_options

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