Jonathan Brandenburg
8 years ago
parent
d3d2449ac7
commit
fa9cb7621f
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// Copyright (c) 2018 Brandenburg Tech, LLC
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// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1.Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2.Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3.Neither the name of AXSEM AG, Duebendorf nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// 4.All advertising materials mentioning features or use of this software
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// must display the following acknowledgement:
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// This product includes software developed by AXSEM AG and its contributors.
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// 5.The usage of this source code is only granted for operation with AX5043
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// and AX8052F143. Porting to other radio or communication devices is
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// strictly prohibited.
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//
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// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef AX5043INIT_H_
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#define AX5043INIT_H_
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#include <stdint.h>
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#define AXRADIO_ERR_NOERROR 0x00
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#define AXRADIO_ERR_NOTSUPPORTED 0x01
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#define AXRADIO_ERR_BUSY 0x02
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#define AXRADIO_ERR_TIMEOUT 0x03
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#define AXRADIO_ERR_INVALID 0x04
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#define AXRADIO_ERR_NOCHIP 0x05
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#define AXRADIO_ERR_RANGING 0x06
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#define AXRADIO_ERR_LOCKLOST 0x07
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#define AXRADIO_ERR_RETRANSMISSION 0x08
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#define AXRADIO_ERR_RESYNC 0x09
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#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a
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#define AXRADIO_ERR_RECEIVESTART 0x0b
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#define AXRADIO_MODE_UNINIT 0x00
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#define AXRADIO_MODE_OFF 0x01
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#define AXRADIO_MODE_DEEPSLEEP 0x02
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#define AXRADIO_MODE_CW_TRANSMIT 0x03
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#define AXRADIO_MODE_ASYNC_TRANSMIT 0x10
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#define AXRADIO_MODE_WOR_TRANSMIT 0x11
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#define AXRADIO_MODE_ACK_TRANSMIT 0x12
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#define AXRADIO_MODE_WOR_ACK_TRANSMIT 0x13
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#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC 0x18
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#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM 0x19
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#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC_LSB 0x1A
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#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM_LSB 0x1B
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#define AXRADIO_MODE_STREAM_TRANSMIT 0x1C
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#define AXRADIO_MODE_ASYNC_RECEIVE 0x20
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#define AXRADIO_MODE_WOR_RECEIVE 0x21
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#define AXRADIO_MODE_ACK_RECEIVE 0x22
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#define AXRADIO_MODE_WOR_ACK_RECEIVE 0x23
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#define AXRADIO_MODE_STREAM_RECEIVE_UNENC 0x28
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#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM 0x29
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#define AXRADIO_MODE_STREAM_RECEIVE_UNENC_LSB 0x2A
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#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM_LSB 0x2B
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#define AXRADIO_MODE_STREAM_RECEIVE 0x2C
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#define AXRADIO_MODE_STREAM_RECEIVE_DATAPIN 0x2D
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#define AXRADIO_MODE_SYNC_MASTER 0x30
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#define AXRADIO_MODE_SYNC_ACK_MASTER 0x31
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#define AXRADIO_MODE_SYNC_SLAVE 0x32
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#define AXRADIO_MODE_SYNC_ACK_SLAVE 0x33
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#define AX5043_AFSKCTRL 0x114 /* AFSK Control */
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#define AX5043_AFSKMARK0 0x113 /* AFSK Mark (1) Frequency 0 */
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#define AX5043_AFSKMARK1 0x112 /* AFSK Mark (1) Frequency 1 */
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#define AX5043_AFSKSPACE0 0x111 /* AFSK Space (0) Frequency 0 */
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#define AX5043_AFSKSPACE1 0x110 /* AFSK Space (0) Frequency 1 */
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#define AX5043_AGCCOUNTER 0x043 /* AGC Counter */
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#define AX5043_AMPLFILTER 0x115 /* Amplitude Filter */
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#define AX5043_BBOFFSCAP 0x189 /* Baseband Offset Compensation Capacitors */
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#define AX5043_BBTUNE 0x188 /* Baseband Tuning */
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#define AX5043_BGNDRSSI 0x041 /* Background RSSI */
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#define AX5043_BGNDRSSIGAIN 0x22E /* Background RSSI Averaging Time Constant */
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#define AX5043_BGNDRSSITHR 0x22F /* Background RSSI Relative Threshold */
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#define AX5043_CRCINIT0 0x017 /* CRC Initial Value 0 */
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#define AX5043_CRCINIT1 0x016 /* CRC Initial Value 1 */
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#define AX5043_CRCINIT2 0x015 /* CRC Initial Value 2 */
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#define AX5043_CRCINIT3 0x014 /* CRC Initial Value 3 */
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#define AX5043_DACCONFIG 0x332 /* DAC Configuration */
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#define AX5043_DACVALUE0 0x331 /* DAC Value 0 */
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#define AX5043_DACVALUE1 0x330 /* DAC Value 1 */
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#define AX5043_DECIMATION 0x102 /* Decimation Factor */
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#define AX5043_DIVERSITY 0x042 /* Antenna Diversity Configuration */
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#define AX5043_ENCODING 0x011 /* Encoding */
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#define AX5043_FEC 0x018 /* Forward Error Correction */
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#define AX5043_FECSTATUS 0x01A /* Forward Error Correction Status */
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#define AX5043_FECSYNC 0x019 /* Forward Error Correction Sync Threshold */
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#define AX5043_FIFOCOUNT0 0x02B /* Number of Words currently in FIFO 0 */
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#define AX5043_FIFOCOUNT1 0x02A /* Number of Words currently in FIFO 1 */
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#define AX5043_FIFODATA 0x029 /* FIFO Data */
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#define AX5043_FIFOFREE0 0x02D /* Number of Words that can be written to FIFO 0 */
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#define AX5043_FIFOFREE1 0x02C /* Number of Words that can be written to FIFO 1 */
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#define AX5043_FIFOSTAT 0x028 /* FIFO Control */
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#define AX5043_FIFOTHRESH0 0x02F /* FIFO Threshold 0 */
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#define AX5043_FIFOTHRESH1 0x02E /* FIFO Threshold 1 */
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#define AX5043_FRAMING 0x012 /* Framing Mode */
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#define AX5043_FREQA0 0x037 /* Frequency A 0 */
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#define AX5043_FREQA1 0x036 /* Frequency A 1 */
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#define AX5043_FREQA2 0x035 /* Frequency A 2 */
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#define AX5043_FREQA3 0x034 /* Frequency A 3 */
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#define AX5043_FREQB0 0x03F /* Frequency B 0 */
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#define AX5043_FREQB1 0x03E /* Frequency B 1 */
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#define AX5043_FREQB2 0x03D /* Frequency B 2 */
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#define AX5043_FREQB3 0x03C /* Frequency B 3 */
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#define AX5043_FSKDEV0 0x163 /* FSK Deviation 0 */
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#define AX5043_FSKDEV1 0x162 /* FSK Deviation 1 */
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#define AX5043_FSKDEV2 0x161 /* FSK Deviation 2 */
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#define AX5043_FSKDMAX0 0x10D /* Four FSK Rx Maximum Deviation 0 */
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#define AX5043_FSKDMAX1 0x10C /* Four FSK Rx Maximum Deviation 1 */
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#define AX5043_FSKDMIN0 0x10F /* Four FSK Rx Minimum Deviation 0 */
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#define AX5043_FSKDMIN1 0x10E /* Four FSK Rx Minimum Deviation 1 */
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#define AX5043_GPADC13VALUE0 0x309 /* GPADC13 Value 0 */
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#define AX5043_GPADC13VALUE1 0x308 /* GPADC13 Value 1 */
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#define AX5043_GPADCCTRL 0x300 /* General Purpose ADC Control */
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#define AX5043_GPADCPERIOD 0x301 /* GPADC Sampling Period */
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#define AX5043_IFFREQ0 0x101 /* 2nd LO / IF Frequency 0 */
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#define AX5043_IFFREQ1 0x100 /* 2nd LO / IF Frequency 1 */
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#define AX5043_IRQINVERSION0 0x00B /* IRQ Inversion 0 */
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#define AX5043_IRQINVERSION1 0x00A /* IRQ Inversion 1 */
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#define AX5043_IRQMASK0 0x007 /* IRQ Mask 0 */
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#define AX5043_IRQMASK1 0x006 /* IRQ Mask 1 */
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#define AX5043_IRQREQUEST0 0x00D /* IRQ Request 0 */
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#define AX5043_IRQREQUEST1 0x00C /* IRQ Request 1 */
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#define AX5043_LPOSCCONFIG 0x310 /* Low Power Oscillator Calibration Configuration */
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#define AX5043_LPOSCFREQ0 0x317 /* Low Power Oscillator Frequency Tuning Low Byte */
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#define AX5043_LPOSCFREQ1 0x316 /* Low Power Oscillator Frequency Tuning High Byte */
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#define AX5043_LPOSCKFILT0 0x313 /* Low Power Oscillator Calibration Filter Constant Low Byte */
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#define AX5043_LPOSCKFILT1 0x312 /* Low Power Oscillator Calibration Filter Constant High Byte */
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#define AX5043_LPOSCPER0 0x319 /* Low Power Oscillator Period Low Byte */
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#define AX5043_LPOSCPER1 0x318 /* Low Power Oscillator Period High Byte */
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#define AX5043_LPOSCREF0 0x315 /* Low Power Oscillator Reference Frequency Low Byte */
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#define AX5043_LPOSCREF1 0x314 /* Low Power Oscillator Reference Frequency High Byte */
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#define AX5043_LPOSCSTATUS 0x311 /* Low Power Oscillator Calibration Status */
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#define AX5043_MATCH0LEN 0x214 /* Pattern Match Unit 0, Pattern Length */
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#define AX5043_MATCH0MAX 0x216 /* Pattern Match Unit 0, Maximum Match */
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#define AX5043_MATCH0MIN 0x215 /* Pattern Match Unit 0, Minimum Match */
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#define AX5043_MATCH0PAT0 0x213 /* Pattern Match Unit 0, Pattern 0 */
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#define AX5043_MATCH0PAT1 0x212 /* Pattern Match Unit 0, Pattern 1 */
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#define AX5043_MATCH0PAT2 0x211 /* Pattern Match Unit 0, Pattern 2 */
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#define AX5043_MATCH0PAT3 0x210 /* Pattern Match Unit 0, Pattern 3 */
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#define AX5043_MATCH1LEN 0x21C /* Pattern Match Unit 1, Pattern Length */
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#define AX5043_MATCH1MAX 0x21E /* Pattern Match Unit 1, Maximum Match */
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#define AX5043_MATCH1MIN 0x21D /* Pattern Match Unit 1, Minimum Match */
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#define AX5043_MATCH1PAT0 0x219 /* Pattern Match Unit 1, Pattern 0 */
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#define AX5043_MATCH1PAT1 0x218 /* Pattern Match Unit 1, Pattern 1 */
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#define AX5043_MAXDROFFSET0 0x108 /* Maximum Receiver Datarate Offset 0 */
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#define AX5043_MAXDROFFSET1 0x107 /* Maximum Receiver Datarate Offset 1 */
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#define AX5043_MAXDROFFSET2 0x106 /* Maximum Receiver Datarate Offset 2 */
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#define AX5043_MAXRFOFFSET0 0x10B /* Maximum Receiver RF Offset 0 */
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#define AX5043_MAXRFOFFSET1 0x10A /* Maximum Receiver RF Offset 1 */
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#define AX5043_MAXRFOFFSET2 0x109 /* Maximum Receiver RF Offset 2 */
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#define AX5043_MODCFGA 0x164 /* Modulator Configuration A */
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#define AX5043_MODCFGF 0x160 /* Modulator Configuration F */
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#define AX5043_MODCFGP 0xF5F /* Modulator Configuration P */
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#define AX5043_MODULATION 0x010 /* Modulation */
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#define AX5043_PINFUNCANTSEL 0x025 /* Pin Function ANTSEL */
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#define AX5043_PINFUNCDATA 0x023 /* Pin Function DATA */
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#define AX5043_PINFUNCDCLK 0x022 /* Pin Function DCLK */
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#define AX5043_PINFUNCIRQ 0x024 /* Pin Function IRQ */
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#define AX5043_PINFUNCPWRAMP 0x026 /* Pin Function PWRAMP */
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#define AX5043_PINFUNCSYSCLK 0x021 /* Pin Function SYSCLK */
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#define AX5043_PINSTATE 0x020 /* Pin State */
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#define AX5043_PKTACCEPTFLAGS 0x233 /* Packet Controller Accept Flags */
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#define AX5043_PKTCHUNKSIZE 0x230 /* Packet Chunk Size */
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#define AX5043_PKTMISCFLAGS 0x231 /* Packet Controller Miscellaneous Flags */
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#define AX5043_PKTSTOREFLAGS 0x232 /* Packet Controller Store Flags */
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#define AX5043_PLLCPI 0x031 /* PLL Charge Pump Current */
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#define AX5043_PLLCPIBOOST 0x039 /* PLL Charge Pump Current (Boosted) */
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#define AX5043_PLLLOCKDET 0x182 /* PLL Lock Detect Delay */
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#define AX5043_PLLLOOP 0x030 /* PLL Loop Filter Settings */
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#define AX5043_PLLLOOPBOOST 0x038 /* PLL Loop Filter Settings (Boosted) */
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#define AX5043_PLLRANGINGA 0x033 /* PLL Autoranging A */
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#define AX5043_PLLRANGINGB 0x03B /* PLL Autoranging B */
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#define AX5043_PLLRNGCLK 0x183 /* PLL Autoranging Clock */
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#define AX5043_PLLVCODIV 0x032 /* PLL Divider Settings */
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#define AX5043_PLLVCOI 0x180 /* PLL VCO Current */
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#define AX5043_PLLVCOIR 0x181 /* PLL VCO Current Readback */
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#define AX5043_POWCTRL1 0xF08 /* Power Control 1 */
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#define AX5043_POWIRQMASK 0x005 /* Power Management Interrupt Mask */
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#define AX5043_POWSTAT 0x003 /* Power Management Status */
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#define AX5043_POWSTICKYSTAT 0x004 /* Power Management Sticky Status */
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#define AX5043_PWRAMP 0x027 /* PWRAMP Control */
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#define AX5043_PWRMODE 0x002 /* Power Mode */
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#define AX5043_RADIOEVENTMASK0 0x009 /* Radio Event Mask 0 */
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#define AX5043_RADIOEVENTMASK1 0x008 /* Radio Event Mask 1 */
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#define AX5043_RADIOEVENTREQ0 0x00F /* Radio Event Request 0 */
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#define AX5043_RADIOEVENTREQ1 0x00E /* Radio Event Request 1 */
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#define AX5043_RADIOSTATE 0x01C /* Radio Controller State */
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#define AX5043_REF 0xF0D /* Reference */
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#define AX5043_RSSI 0x040 /* Received Signal Strength Indicator */
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#define AX5043_RSSIABSTHR 0x22D /* RSSI Absolute Threshold */
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#define AX5043_RSSIREFERENCE 0x22C /* RSSI Offset */
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#define AX5043_RXDATARATE0 0x105 /* Receiver Datarate 0 */
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#define AX5043_RXDATARATE1 0x104 /* Receiver Datarate 1 */
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#define AX5043_RXDATARATE2 0x103 /* Receiver Datarate 2 */
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#define AX5043_SCRATCH 0x001 /* Scratch */
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#define AX5043_SILICONREVISION 0x000 /* Silicon Revision */
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#define AX5043_TIMER0 0x05B /* 1MHz Timer 0 */
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#define AX5043_TIMER1 0x05A /* 1MHz Timer 1 */
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#define AX5043_TIMER2 0x059 /* 1MHz Timer 2 */
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#define AX5043_TMGRXAGC 0x227 /* Receiver AGC Settling Time */
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#define AX5043_TMGRXBOOST 0x223 /* Receive PLL Boost Time */
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#define AX5043_TMGRXCOARSEAGC 0x226 /* Receive Coarse AGC Time */
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#define AX5043_TMGRXOFFSACQ 0x225 /* Receive Baseband DC Offset Acquisition Time */
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#define AX5043_TMGRXPREAMBLE1 0x229 /* Receiver Preamble 1 Timeout */
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#define AX5043_TMGRXPREAMBLE2 0x22A /* Receiver Preamble 2 Timeout */
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#define AX5043_TMGRXPREAMBLE3 0x22B /* Receiver Preamble 3 Timeout */
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#define AX5043_TMGRXRSSI 0x228 /* Receiver RSSI Settling Time */
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#define AX5043_TMGRXSETTLE 0x224 /* Receive PLL (post Boost) Settling Time */
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#define AX5043_TMGTXBOOST 0x220 /* Transmit PLL Boost Time */
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#define AX5043_TMGTXSETTLE 0x221 /* Transmit PLL (post Boost) Settling Time */
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#define AX5043_TRKAFSKDEMOD0 0x055 /* AFSK Demodulator Tracking 0 */
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#define AX5043_TRKAFSKDEMOD1 0x054 /* AFSK Demodulator Tracking 1 */
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#define AX5043_TRKAMPLITUDE0 0x049 /* Amplitude Tracking 0 */
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#define AX5043_TRKAMPLITUDE1 0x048 /* Amplitude Tracking 1 */
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#define AX5043_TRKDATARATE0 0x047 /* Datarate Tracking 0 */
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#define AX5043_TRKDATARATE1 0x046 /* Datarate Tracking 1 */
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#define AX5043_TRKDATARATE2 0x045 /* Datarate Tracking 2 */
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#define AX5043_TRKFREQ0 0x051 /* Frequency Tracking 0 */
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#define AX5043_TRKFREQ1 0x050 /* Frequency Tracking 1 */
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#define AX5043_TRKFSKDEMOD0 0x053 /* FSK Demodulator Tracking 0 */
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#define AX5043_TRKFSKDEMOD1 0x052 /* FSK Demodulator Tracking 1 */
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#define AX5043_TRKPHASE0 0x04B /* Phase Tracking 0 */
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#define AX5043_TRKPHASE1 0x04A /* Phase Tracking 1 */
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#define AX5043_TRKRFFREQ0 0x04F /* RF Frequency Tracking 0 */
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#define AX5043_TRKRFFREQ1 0x04E /* RF Frequency Tracking 1 */
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#define AX5043_TRKRFFREQ2 0x04D /* RF Frequency Tracking 2 */
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#define AX5043_TXPWRCOEFFA0 0x169 /* Transmitter Predistortion Coefficient A 0 */
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#define AX5043_TXPWRCOEFFA1 0x168 /* Transmitter Predistortion Coefficient A 1 */
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#define AX5043_TXPWRCOEFFB0 0x16B /* Transmitter Predistortion Coefficient B 0 */
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#define AX5043_TXPWRCOEFFB1 0x16A /* Transmitter Predistortion Coefficient B 1 */
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#define AX5043_TXPWRCOEFFC0 0x16D /* Transmitter Predistortion Coefficient C 0 */
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#define AX5043_TXPWRCOEFFC1 0x16C /* Transmitter Predistortion Coefficient C 1 */
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#define AX5043_TXPWRCOEFFD0 0x16F /* Transmitter Predistortion Coefficient D 0 */
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#define AX5043_TXPWRCOEFFD1 0x16E /* Transmitter Predistortion Coefficient D 1 */
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#define AX5043_TXPWRCOEFFE0 0x171 /* Transmitter Predistortion Coefficient E 0 */
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#define AX5043_TXPWRCOEFFE1 0x170 /* Transmitter Predistortion Coefficient E 1 */
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#define AX5043_TXRATE0 0x167 /* Transmitter Bitrate 0 */
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#define AX5043_TXRATE1 0x166 /* Transmitter Bitrate 1 */
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#define AX5043_TXRATE2 0x165 /* Transmitter Bitrate 2 */
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#define AX5043_WAKEUP0 0x06B /* Wakeup Time 0 */
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#define AX5043_WAKEUP1 0x06A /* Wakeup Time 1 */
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#define AX5043_WAKEUPFREQ0 0x06D /* Wakeup Frequency 0 */
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#define AX5043_WAKEUPFREQ1 0x06C /* Wakeup Frequency 1 */
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#define AX5043_WAKEUPTIMER0 0x069 /* Wakeup Timer 0 */
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#define AX5043_WAKEUPTIMER1 0x068 /* Wakeup Timer 1 */
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#define AX5043_WAKEUPXOEARLY 0x06E /* Wakeup Crystal Oscillator Early */
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#define AX5043_XTALAMPL 0xF11 /* Crystal Oscillator Amplitude Control */
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#define AX5043_XTALCAP 0x184 /* Crystal Oscillator Load Capacitance */
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#define AX5043_XTALOSC 0xF10 /* Crystal Oscillator Control */
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#define AX5043_XTALSTATUS 0x01D /* Crystal Oscillator Status */
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#define AX5043_0xF00 0xF00
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#define AX5043_0xF0C 0xF0C
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#define AX5043_0xF18 0xF18
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#define AX5043_0xF1C 0xF1C
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#define AX5043_0xF21 0xF21
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#define AX5043_0xF22 0xF22
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#define AX5043_0xF23 0xF23
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#define AX5043_0xF26 0xF26
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#define AX5043_0xF30 0xF30
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#define AX5043_0xF31 0xF31
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#define AX5043_0xF32 0xF32
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#define AX5043_0xF33 0xF33
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#define AX5043_0xF34 0xF34
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#define AX5043_0xF35 0xF35
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#define AX5043_0xF44 0xF44
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#define AX5043_AGCAHYST0 0x122 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST1 0x132 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST2 0x142 /* AGC Analog Hysteresis */
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#define AX5043_AGCAHYST3 0x152 /* AGC Analog Hysteresis */
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#define AX5043_AGCGAIN0 0x120 /* AGC Speed */
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#define AX5043_AGCGAIN1 0x130 /* AGC Speed */
|
||||
#define AX5043_AGCGAIN2 0x140 /* AGC Speed */
|
||||
#define AX5043_AGCGAIN3 0x150 /* AGC Speed */
|
||||
#define AX5043_AGCMINMAX0 0x123 /* AGC Analog Update Behaviour */
|
||||
#define AX5043_AGCMINMAX1 0x133 /* AGC Analog Update Behaviour */
|
||||
#define AX5043_AGCMINMAX2 0x143 /* AGC Analog Update Behaviour */
|
||||
#define AX5043_AGCMINMAX3 0x153 /* AGC Analog Update Behaviour */
|
||||
#define AX5043_AGCTARGET0 0x121 /* AGC Target */
|
||||
#define AX5043_AGCTARGET1 0x131 /* AGC Target */
|
||||
#define AX5043_AGCTARGET2 0x141 /* AGC Target */
|
||||
#define AX5043_AGCTARGET3 0x151 /* AGC Target */
|
||||
#define AX5043_AMPLITUDEGAIN0 0x12B /* Amplitude Estimator Bandwidth */
|
||||
#define AX5043_AMPLITUDEGAIN1 0x13B /* Amplitude Estimator Bandwidth */
|
||||
#define AX5043_AMPLITUDEGAIN2 0x14B /* Amplitude Estimator Bandwidth */
|
||||
#define AX5043_AMPLITUDEGAIN3 0x15B /* Amplitude Estimator Bandwidth */
|
||||
#define AX5043_BBOFFSRES0 0x12F /* Baseband Offset Compensation Resistors */
|
||||
#define AX5043_BBOFFSRES1 0x13F /* Baseband Offset Compensation Resistors */
|
||||
#define AX5043_BBOFFSRES2 0x14F /* Baseband Offset Compensation Resistors */
|
||||
#define AX5043_BBOFFSRES3 0x15F /* Baseband Offset Compensation Resistors */
|
||||
#define AX5043_DRGAIN0 0x125 /* Data Rate Estimator Bandwidth */
|
||||
#define AX5043_DRGAIN1 0x135 /* Data Rate Estimator Bandwidth */
|
||||
#define AX5043_DRGAIN2 0x145 /* Data Rate Estimator Bandwidth */
|
||||
#define AX5043_DRGAIN3 0x155 /* Data Rate Estimator Bandwidth */
|
||||
#define AX5043_FOURFSK0 0x12E /* Four FSK Control */
|
||||
#define AX5043_FOURFSK1 0x13E /* Four FSK Control */
|
||||
#define AX5043_FOURFSK2 0x14E /* Four FSK Control */
|
||||
#define AX5043_FOURFSK3 0x15E /* Four FSK Control */
|
||||
#define AX5043_FREQDEV00 0x12D /* Receiver Frequency Deviation 0 */
|
||||
#define AX5043_FREQDEV01 0x13D /* Receiver Frequency Deviation 0 */
|
||||
#define AX5043_FREQDEV02 0x14D /* Receiver Frequency Deviation 0 */
|
||||
#define AX5043_FREQDEV03 0x15D /* Receiver Frequency Deviation 0 */
|
||||
#define AX5043_FREQDEV10 0x12C /* Receiver Frequency Deviation 1 */
|
||||
#define AX5043_FREQDEV11 0x13C /* Receiver Frequency Deviation 1 */
|
||||
#define AX5043_FREQDEV12 0x14C /* Receiver Frequency Deviation 1 */
|
||||
#define AX5043_FREQDEV13 0x15C /* Receiver Frequency Deviation 1 */
|
||||
#define AX5043_FREQUENCYGAINA0 0x127 /* Frequency Estimator Bandwidth A */
|
||||
#define AX5043_FREQUENCYGAINA1 0x137 /* Frequency Estimator Bandwidth A */
|
||||
#define AX5043_FREQUENCYGAINA2 0x147 /* Frequency Estimator Bandwidth A */
|
||||
#define AX5043_FREQUENCYGAINA3 0x157 /* Frequency Estimator Bandwidth A */
|
||||
#define AX5043_FREQUENCYGAINB0 0x128 /* Frequency Estimator Bandwidth B */
|
||||
#define AX5043_FREQUENCYGAINB1 0x138 /* Frequency Estimator Bandwidth B */
|
||||
#define AX5043_FREQUENCYGAINB2 0x148 /* Frequency Estimator Bandwidth B */
|
||||
#define AX5043_FREQUENCYGAINB3 0x158 /* Frequency Estimator Bandwidth B */
|
||||
#define AX5043_FREQUENCYGAINC0 0x129 /* Frequency Estimator Bandwidth C */
|
||||
#define AX5043_FREQUENCYGAINC1 0x139 /* Frequency Estimator Bandwidth C */
|
||||
#define AX5043_FREQUENCYGAINC2 0x149 /* Frequency Estimator Bandwidth C */
|
||||
#define AX5043_FREQUENCYGAINC3 0x159 /* Frequency Estimator Bandwidth C */
|
||||
#define AX5043_FREQUENCYGAIND0 0x12A /* Frequency Estimator Bandwidth D */
|
||||
#define AX5043_FREQUENCYGAIND1 0x13A /* Frequency Estimator Bandwidth D */
|
||||
#define AX5043_FREQUENCYGAIND2 0x14A /* Frequency Estimator Bandwidth D */
|
||||
#define AX5043_FREQUENCYGAIND3 0x15A /* Frequency Estimator Bandwidth D */
|
||||
#define AX5043_FREQUENCYLEAK 0x116 /* Baseband Frequency Recovery Loop Leakiness */
|
||||
#define AX5043_PHASEGAIN0 0x126 /* Phase Estimator Bandwidth */
|
||||
#define AX5043_PHASEGAIN1 0x136 /* Phase Estimator Bandwidth */
|
||||
#define AX5043_PHASEGAIN2 0x146 /* Phase Estimator Bandwidth */
|
||||
#define AX5043_PHASEGAIN3 0x156 /* Phase Estimator Bandwidth */
|
||||
#define AX5043_PKTADDR0 0x207 /* Packet Address 0 */
|
||||
#define AX5043_PKTADDR1 0x206 /* Packet Address 1 */
|
||||
#define AX5043_PKTADDR2 0x205 /* Packet Address 2 */
|
||||
#define AX5043_PKTADDR3 0x204 /* Packet Address 3 */
|
||||
#define AX5043_PKTADDRCFG 0x200 /* Packet Address Config */
|
||||
#define AX5043_PKTADDRMASK0 0x20B /* Packet Address Mask 0 */
|
||||
#define AX5043_PKTADDRMASK1 0x20A /* Packet Address Mask 1 */
|
||||
#define AX5043_PKTADDRMASK2 0x209 /* Packet Address Mask 2 */
|
||||
#define AX5043_PKTADDRMASK3 0x208 /* Packet Address Mask 3 */
|
||||
#define AX5043_PKTLENCFG 0x201 /* Packet Length Configuration */
|
||||
#define AX5043_PKTLENOFFSET 0x202 /* Packet Length Offset */
|
||||
#define AX5043_PKTMAXLEN 0x203 /* Packet Maximum Length */
|
||||
#define AX5043_RXPARAMCURSET 0x118 /* Receiver Parameter Current Set */
|
||||
#define AX5043_RXPARAMSETS 0x117 /* Receiver Parameter Set Indirection */
|
||||
#define AX5043_TIMEGAIN0 0x124 /* Time Estimator Bandwidth */
|
||||
#define AX5043_TIMEGAIN1 0x134 /* Time Estimator Bandwidth */
|
||||
#define AX5043_TIMEGAIN2 0x144 /* Time Estimator Bandwidth */
|
||||
#define AX5043_TIMEGAIN3 0x154 /* Time Estimator Bandwidth */
|
||||
|
||||
// power states
|
||||
#define AX5043_PWRSTATE_POWERDOWN 0x0
|
||||
#define AX5043_PWRSTATE_DEEPSLEEP 0x1
|
||||
#define AX5043_PWRSTATE_REGS_ON 0x4
|
||||
#define AX5043_PWRSTATE_XTAL_ON 0x5
|
||||
#define AX5043_PWRSTATE_FIFO_ON 0x7
|
||||
#define AX5043_PWRSTATE_SYNTH_RX 0x8
|
||||
#define AX5043_PWRSTATE_FULL_RX 0x9
|
||||
#define AX5043_PWRSTATE_WOR_RX 0xb
|
||||
#define AX5043_PWRSTATE_SYNTH_TX 0xc
|
||||
#define AX5043_PWRSTATE_FULL_TX 0xd
|
||||
|
||||
//fifo commands
|
||||
#define AX5043_FIFOCMD_NOP 0x00
|
||||
#define AX5043_FIFOCMD_DATA 0x01
|
||||
#define AX5043_FIFOCMD_REPEATDATA 0x02
|
||||
#define AX5043_FIFOCMD_TIMER 0x10
|
||||
#define AX5043_FIFOCMD_RSSI 0x11
|
||||
#define AX5043_FIFOCMD_FREQOFFS 0x12
|
||||
#define AX5043_FIFOCMD_RFFREQOFFS 0x13
|
||||
#define AX5043_FIFOCMD_DATARATE 0x14
|
||||
#define AX5043_FIFOCMD_ANTRSSI 0x15
|
||||
#define AX5043_FIFOCMD_TXCTRL 0x1C
|
||||
#define AX5043_FIFOCMD_TXPWR 0x1D
|
||||
|
||||
#define SILICONREV1 0x51
|
||||
\
|
||||
#define RADIO_OK 0
|
||||
#define RADIO_ERR_REVISION 1
|
||||
#define RADIO_ERR_COMM 2
|
||||
#define RADIO_ERR_IRQ 3
|
||||
#define RADIO_ERR_WAKEUPTIMEOUT 4
|
||||
|
||||
#define PKTDATA_BUFLEN 260
|
||||
|
||||
typedef enum {
|
||||
trxstate_off,
|
||||
trxstate_rx,
|
||||
trxstate_rxwor,
|
||||
trxstate_wait_xtal,
|
||||
trxstate_xtal_ready,
|
||||
trxstate_pll_ranging,
|
||||
trxstate_pll_ranging_done,
|
||||
trxstate_pll_settling,
|
||||
trxstate_pll_settled,
|
||||
trxstate_tx_xtalwait,
|
||||
trxstate_tx_longpreamble,
|
||||
trxstate_tx_shortpreamble,
|
||||
trxstate_tx_packet,
|
||||
trxstate_tx_waitdone,
|
||||
trxstate_txcw_xtalwait,
|
||||
trxstate_txstream_xtalwait,
|
||||
trxstate_txstream
|
||||
} axradio_trxstate_t;
|
||||
|
||||
struct axradio_address {
|
||||
uint8_t addr[4];
|
||||
};
|
||||
|
||||
struct axradio_address_mask {
|
||||
uint8_t addr[4];
|
||||
uint8_t mask[4];
|
||||
};
|
||||
|
||||
uint8_t axradio_init(void);
|
||||
void axradio_wait_for_xtal(void);
|
||||
|
||||
#endif /* AX5043INIT_H_ */
|
||||
@ -0,0 +1,35 @@
|
||||
/*! \file ax5043init_p.h
|
||||
\brief Provides an interface to initialze the AX5043 transceiver.
|
||||
*/
|
||||
|
||||
#ifndef AX5043INIT_P_H_
|
||||
#define AX5043INIT_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define AXRADIO_ERR_NOERROR 0x00 //!< Operation successful
|
||||
#define AXRADIO_ERR_NOTSUPPORTED 0x01 //!< Operation not supported
|
||||
#define AXRADIO_ERR_BUSY 0x02 //!< Transceiver busy
|
||||
#define AXRADIO_ERR_TIMEOUT 0x03 //!< Operation timed out
|
||||
#define AXRADIO_ERR_INVALID 0x04 //!< Invalid parameter
|
||||
#define AXRADIO_ERR_NOCHIP 0x05 //!< Transceiver not found
|
||||
#define AXRADIO_ERR_RANGING 0x06 //!< Frequency could not be ranged
|
||||
#define AXRADIO_ERR_LOCKLOST 0x07 //!< Lost PLL lock
|
||||
#define AXRADIO_ERR_RETRANSMISSION 0x08 //!< Retrasnmitted packet
|
||||
#define AXRADIO_ERR_RESYNC 0x09 //!< Restarts synchronization
|
||||
#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a //!< Synchronization timed out
|
||||
#define AXRADIO_ERR_RECEIVESTART 0x0b //!< Receiver restarted
|
||||
|
||||
//! Structure containing a four byte X.25 address
|
||||
struct axradio_address {
|
||||
uint8_t addr[4]; //!< Four byte X.25 address
|
||||
};
|
||||
|
||||
/*! \fn uint8_t axradio_init(void)
|
||||
\brief Initialize the AX5043 radio transceiver.
|
||||
\return AXRADIO_ERR_NOERROR on success, otherwise a value indicating an error.
|
||||
\sa AXRADIO_ERR_NOERROR
|
||||
*/
|
||||
uint8_t axradio_init(void);
|
||||
|
||||
#endif /* AX5043INIT_P_H_ */
|
||||
@ -1,50 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1.Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// 2.Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// 3.Neither the name of AXSEM AG, Duebendorf nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
// 4.All advertising materials mentioning features or use of this software
|
||||
// must display the following acknowledgement:
|
||||
// This product includes software developed by AXSEM AG and its contributors.
|
||||
// 5.The usage of this source code is only granted for operation with AX5043
|
||||
// and AX8052F143. Porting to other radio or communication devices is
|
||||
// strictly prohibited.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
|
||||
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
#ifndef AX5043MODE_H_
|
||||
#define AX5043MODE_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
uint8_t mode_tx();
|
||||
uint8_t mode_rx();
|
||||
uint8_t ax5043_off(void);
|
||||
uint8_t ax5043_off_xtal(void);
|
||||
uint8_t ax5043_init_registers_tx(void);
|
||||
uint8_t axradio_get_pllvcoi(void);
|
||||
uint8_t ax5043_init_registers_rx(void);
|
||||
uint8_t ax5043_receiver_on_continuous(void);
|
||||
|
||||
|
||||
#endif /* AX5043MODE_H_ */
|
||||
@ -0,0 +1,27 @@
|
||||
/*! \file ax5043mode_p.h
|
||||
\brief Provides an interface to change the transceiver mode.
|
||||
*/
|
||||
|
||||
#ifndef AX5043MODE_P_H_
|
||||
#define AX5043MODE_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! \fn uint8_t mode_tx()
|
||||
\brief Switch the tranceiver into transmit mode.
|
||||
\return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
|
||||
\sa AXRADIO_ERR_NOERROR
|
||||
*/
|
||||
uint8_t mode_tx(void);
|
||||
|
||||
/*! \fn uint8_t mode_rx()
|
||||
\brief Switch the tranceiver into receive mode.
|
||||
|
||||
The receive buffer may contain garbage and reading from the buffer
|
||||
will obtain and discard that garbage.
|
||||
\return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
|
||||
\sa AXRADIO_ERR_NOERROR
|
||||
*/
|
||||
uint8_t mode_rx(void);
|
||||
|
||||
#endif /* AX5043MODE_P_H_ */
|
||||
@ -1,15 +0,0 @@
|
||||
/*
|
||||
* ax5043rx.h
|
||||
*
|
||||
* Created on: Feb 23, 2018
|
||||
* Author: Jonathan Brandenburg
|
||||
*/
|
||||
|
||||
#ifndef AX5043RX_H_
|
||||
#define AX5043RX_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
uint8_t receive_packet(void);
|
||||
|
||||
#endif /* AX5043RX_H_ */
|
||||
@ -0,0 +1,16 @@
|
||||
/*! \file ax5043rx_p.h
|
||||
\brief Provides an interface to receive packets using the digital transceiver.
|
||||
*/
|
||||
#ifndef AX5043RX_P_H_
|
||||
#define AX5043RX_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! \fn uint8_t receive_packet(void)
|
||||
\brief Receive a packet from the digital transceiver receive buffer.
|
||||
\return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
|
||||
\sa AXRADIO_ERR_NOERROR
|
||||
*/
|
||||
uint8_t receive_packet(void);
|
||||
|
||||
#endif /* AX5043RX_P_H_ */
|
||||
@ -1,46 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1.Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// 2.Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// 3.Neither the name of AXSEM AG, Duebendorf nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
// 4.All advertising materials mentioning features or use of this software
|
||||
// must display the following acknowledgement:
|
||||
// This product includes software developed by AXSEM AG and its contributors.
|
||||
// 5.The usage of this source code is only granted for operation with AX5043
|
||||
// and AX8052F143. Porting to other radio or communication devices is
|
||||
// strictly prohibited.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
|
||||
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
#ifndef AX5043TX_H_
|
||||
#define AX5043TX_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "ax5043init.h"
|
||||
|
||||
uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen);
|
||||
void ax5043_writefifo(const uint8_t *ptr, uint8_t len);
|
||||
void ax5043_prepare_tx(void);
|
||||
|
||||
#endif /* AX5043TX_H_ */
|
||||
@ -0,0 +1,21 @@
|
||||
/*! \file ax5043tx_p.h
|
||||
\brief Provides an interface to transmit packets using the digital transceiver.
|
||||
*/
|
||||
#ifndef AX5043TX_P_H_
|
||||
#define AX5043TX_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "ax5043init_p.h"
|
||||
|
||||
/*! \fn uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen)
|
||||
\brief Transmit a packet using the digital transceiver
|
||||
\param addr The address of the desired destiantion radio, if used.
|
||||
\param pkt The byte data to be transmitted.
|
||||
\param pktlen The number of bytes in pkt to be transmitted.
|
||||
\return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
|
||||
\sa AXRADIO_ERR_NOERROR
|
||||
*/
|
||||
uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen);
|
||||
|
||||
#endif /* AX5043TX_P_H_ */
|
||||
@ -1,85 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#include "crc.h"
|
||||
|
||||
/* Polynomial: x^16 + x^15 + x^2 + 1 = 0x18005 LSB first */
|
||||
|
||||
const uint16_t crc_crc16_table[256] = {
|
||||
0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241,
|
||||
0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440,
|
||||
0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40,
|
||||
0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841,
|
||||
0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40,
|
||||
0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41,
|
||||
0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641,
|
||||
0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040,
|
||||
0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240,
|
||||
0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441,
|
||||
0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41,
|
||||
0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840,
|
||||
0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41,
|
||||
0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40,
|
||||
0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640,
|
||||
0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041,
|
||||
0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240,
|
||||
0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441,
|
||||
0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41,
|
||||
0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840,
|
||||
0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41,
|
||||
0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40,
|
||||
0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640,
|
||||
0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041,
|
||||
0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241,
|
||||
0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440,
|
||||
0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40,
|
||||
0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841,
|
||||
0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40,
|
||||
0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41,
|
||||
0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641,
|
||||
0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040
|
||||
};
|
||||
|
||||
uint16_t crc_crc16(const uint8_t *buf, uint16_t buflen, uint16_t crc)
|
||||
{
|
||||
if (!buflen)
|
||||
return crc;
|
||||
do {
|
||||
crc = crc_crc16_byte(crc, *buf++);
|
||||
} while (--buflen);
|
||||
return crc;
|
||||
}
|
||||
|
||||
uint16_t crc_crc16_byte(uint16_t crc, uint8_t c)
|
||||
{
|
||||
return (crc >> 8) ^ crc_crc16_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
|
||||
}
|
||||
|
||||
uint16_t pn9_buffer(uint8_t *buf, uint16_t buflen, uint16_t pn9, uint8_t xor)
|
||||
{
|
||||
if (!buflen)
|
||||
return pn9;
|
||||
do {
|
||||
*buf++ ^= pn9 ^ xor;
|
||||
pn9 = pn9_advance_byte(pn9);
|
||||
} while (--buflen);
|
||||
return pn9;
|
||||
}
|
||||
|
||||
uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits)
|
||||
{
|
||||
if (!bits)
|
||||
return pn9;
|
||||
do {
|
||||
pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
|
||||
} while (--bits);
|
||||
return pn9;
|
||||
}
|
||||
|
||||
uint16_t pn9_advance_byte(uint16_t pn9)
|
||||
{
|
||||
uint8_t bits = 8;
|
||||
do {
|
||||
pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
|
||||
} while (--bits);
|
||||
return pn9;
|
||||
}
|
||||
@ -1,16 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#ifndef CRC_H_
|
||||
#define CRC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
uint16_t crc_crc16(const uint8_t *buf, uint16_t buflen, uint16_t crc);
|
||||
uint16_t crc_crc16_byte(uint16_t crc, uint8_t c);
|
||||
uint16_t pn9_buffer(uint8_t *buf, uint16_t buflen, uint16_t pn9, uint8_t xor);
|
||||
uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits);
|
||||
uint16_t pn9_advance_byte(uint16_t pn9);
|
||||
|
||||
|
||||
|
||||
#endif /* CRC_H_ */
|
||||
@ -1,25 +0,0 @@
|
||||
/* Warning: This file is automatically generated by AX-RadioLAB.
|
||||
Manual changes are overwritten! */
|
||||
|
||||
#include "../ax5043/ax5043init.h"
|
||||
|
||||
|
||||
#define USE_LCD
|
||||
#define USE_DBGLINK
|
||||
//#define USE_COM0
|
||||
//#define DEBUGMSG
|
||||
#define MCU_SLEEP
|
||||
#define WTIMER0_CLKSRC CLKSRC_LPOSC
|
||||
#define WTIMER0_PRESCALER 0x01
|
||||
#define RADIO_MODE_RX AXRADIO_MODE_ASYNC_RECEIVE
|
||||
#define FXTAL 48000000
|
||||
|
||||
extern const struct axradio_address remoteaddr_rx;
|
||||
extern const struct axradio_address_mask localaddr_rx;
|
||||
|
||||
extern const uint8_t framing_insert_counter;
|
||||
extern const uint8_t framing_counter_pos;
|
||||
|
||||
extern const uint16_t lposckfiltmax;
|
||||
|
||||
extern const uint16_t lpxosc_settlingtime;
|
||||
Binary file not shown.
@ -1,96 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#include "ax5043spi.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
//#include "dummyspi.h"
|
||||
//#warning "For production builds, must not include dummyspi.h"
|
||||
#include <wiringPiSPI.h>
|
||||
#include <wiringPi.h>
|
||||
|
||||
int spiChannel = -1;
|
||||
int spiSpeed = -1;
|
||||
|
||||
void setSpiChannel(int newSpiChannel) {
|
||||
spiChannel = newSpiChannel;
|
||||
}
|
||||
|
||||
void setSpiSpeed(int newSpiSpeed) {
|
||||
spiSpeed = newSpiSpeed;
|
||||
}
|
||||
|
||||
void initializeSpi() {
|
||||
//printf("INFO: Initializing SPI\n");
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
if (spiSpeed < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI speed %d\n", spiSpeed);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
|
||||
int fd;
|
||||
|
||||
wiringPiSetup();
|
||||
|
||||
fd = wiringPiSPISetup(spiChannel, spiSpeed);
|
||||
if (fd < 0) {
|
||||
fprintf(stderr, "ERROR: Cannot open SPI bus with error %d, %s\n",
|
||||
errno, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
//printf("INFO: Finished initializing SPI\n");
|
||||
}
|
||||
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val) {
|
||||
uint8_t buf[3];
|
||||
int result;
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
buf[0] = (unsigned char)(0x00f0 | ((reg & 0xf00) >> 8));
|
||||
buf[1] = (reg & 0xff);
|
||||
buf[2] = val & 0xff;
|
||||
|
||||
result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
|
||||
if (result < 0) {
|
||||
fprintf(stderr, "Failed to write the register with result %d and error %s\n",
|
||||
result, strerror(result));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t ax5043ReadReg(uint16_t reg) {
|
||||
uint8_t buf[3];
|
||||
int result;
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
buf[0] = (unsigned char)(0x0070 | ((reg & 0xf00) >> 8));
|
||||
buf[1] = (reg & 0xff);
|
||||
buf[2] = 0x0000;
|
||||
|
||||
result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
|
||||
if (result < 0) {
|
||||
fprintf(stderr, "Failed to read register with result = %d and error %s\n",
|
||||
result, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
//printf("DEBUG: read value: %d\n", (int)buf[2]);
|
||||
return (buf[2] & 0xff);
|
||||
}
|
||||
@ -1,17 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#ifndef AX5043SPI_H_
|
||||
#define AX5043SPI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SPI_CHANNEL (0)
|
||||
#define SPI_SPEED (32000000)
|
||||
|
||||
void setSpiChannel(int newSpiChannel);
|
||||
void setSpiSpeed(int newSpiSpeed);
|
||||
void initializeSpi();
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val);
|
||||
uint8_t ax5043ReadReg(uint16_t reg);
|
||||
|
||||
#endif /* AX5043SPI_H_ */
|
||||
@ -0,0 +1,57 @@
|
||||
/*! \file ax5043spi_p.h
|
||||
\brief Provides an abstraction layer for the SPI interface communicating to the digital transceiver
|
||||
*/
|
||||
|
||||
#ifndef AX5043SPI_P_H_
|
||||
#define AX5043SPI_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SPI_CHANNEL (0) //!< The default SPI channel for the digital transceiver
|
||||
#define SPI_SPEED (32000000) //!< The default SPI bus speed for the digital transceiver
|
||||
|
||||
/*! \fn void setSpiChannel(int newSpiChannel)
|
||||
\brief Set the SPI channel for the digital transceiver.
|
||||
|
||||
setSpiChannel must be called before initializeSpi(). The default is SPI_CHANNEL.
|
||||
\param newSpiChannel The SPI channel for the digital transceiver.
|
||||
\sa SPI_CHANNEL
|
||||
\sa initializeSpi
|
||||
*/
|
||||
void setSpiChannel(int newSpiChannel);
|
||||
|
||||
/*! \fn void setSpiSpeed(int newSpiSpeed)
|
||||
\brief Set the SPI bus speed for the digital transceiver.
|
||||
|
||||
|
||||
setSpiSpeed must be called before initializeSpi(). The default is SPI_SPEED.
|
||||
\param newSpiSpeed The SPI bus speed for the digital transceiver.
|
||||
\sa SPI_SPEED
|
||||
\sa initializeSpi
|
||||
*/
|
||||
void setSpiSpeed(int newSpiSpeed);
|
||||
|
||||
/*! \fn void initializeSpi()
|
||||
\brief Initilize the SPI bus to communicate with the digital transceiver.
|
||||
|
||||
setSpiChannel() and setSpiSpeed() must both be called before initializeSPI().
|
||||
\sa setSpiChannel
|
||||
\sa setSpiSpeed
|
||||
*/
|
||||
void initializeSpi(void);
|
||||
|
||||
/*! \fn void ax5043WriteReg(uint16_t reg, uint8_t val)
|
||||
\brief Write a value to an AX5043 register.
|
||||
\param reg The register to write.
|
||||
\param val The value to right to the register.
|
||||
*/
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val);
|
||||
|
||||
/*! \fn uint8_t ax5043ReadReg(uint16_t reg)
|
||||
\brief Read a value from an AX5043 register.
|
||||
\param reg The register to read.
|
||||
\return The value read from the register.
|
||||
*/
|
||||
uint8_t ax5043ReadReg(uint16_t reg);
|
||||
|
||||
#endif /* AX5043SPI_P_H_ */
|
||||
Binary file not shown.
@ -1,97 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#include "ax5043spi.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
//#include "dummyspi.h"
|
||||
//#warning "For production builds, must not include dummyspi.h"
|
||||
#include <wiringPiSPI.h>
|
||||
#include <wiringPi.h>
|
||||
|
||||
int spiChannel = -1;
|
||||
int spiSpeed = -1;
|
||||
|
||||
void setSpiChannel(int newSpiChannel) {
|
||||
spiChannel = newSpiChannel;
|
||||
}
|
||||
|
||||
void setSpiSpeed(int newSpiSpeed) {
|
||||
spiSpeed = newSpiSpeed;
|
||||
}
|
||||
|
||||
void initializeSpi() {
|
||||
printf("INFO: Initializing SPI\n");
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
if (spiSpeed < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI speed %d\n", spiSpeed);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
|
||||
int fd;
|
||||
|
||||
wiringPiSetup();
|
||||
|
||||
fd = wiringPiSPISetup(spiChannel, spiSpeed);
|
||||
|
||||
if (fd < 0) {
|
||||
fprintf(stderr, "ERROR: Cannot open SPI bus with error %d, %s\n",
|
||||
errno, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
printf("INFO: Finished initializing SPI\n");
|
||||
}
|
||||
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val) {
|
||||
uint8_t buf[3];
|
||||
int result;
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
buf[0] = (unsigned char)(0x00f0 | ((reg & 0xf00) >> 8));
|
||||
buf[1] = (reg & 0xff);
|
||||
buf[2] = val & 0xff;
|
||||
|
||||
result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
|
||||
if (result < 0) {
|
||||
fprintf(stderr, "Failed to write the register with result %d and error %s\n",
|
||||
result, strerror(result));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t ax5043ReadReg(uint16_t reg) {
|
||||
uint8_t buf[3];
|
||||
int result;
|
||||
|
||||
if (spiChannel < 0) {
|
||||
fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
buf[0] = (unsigned char)(0x0070 | ((reg & 0xf00) >> 8));
|
||||
buf[1] = (reg & 0xff);
|
||||
buf[2] = 0x0000;
|
||||
|
||||
result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
|
||||
if (result < 0) {
|
||||
fprintf(stderr, "Failed to read register with result = %d and error %s\n",
|
||||
result, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
//printf("DEBUG: read value: %d\n", (int)buf[2]);
|
||||
return (buf[2] & 0xff);
|
||||
}
|
||||
@ -1,17 +0,0 @@
|
||||
// Copyright (c) 2018 Brandenburg Tech, LLC
|
||||
|
||||
#ifndef AX5043SPI_H_
|
||||
#define AX5043SPI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SPI_CHANNEL (0)
|
||||
#define SPI_SPEED (32000000)
|
||||
|
||||
void setSpiChannel(int newSpiChannel);
|
||||
void setSpiSpeed(int newSpiSpeed);
|
||||
void initializeSpi();
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val);
|
||||
uint8_t ax5043ReadReg(uint16_t reg);
|
||||
|
||||
#endif /* AX5043SPI_H_ */
|
||||
@ -0,0 +1,57 @@
|
||||
/*! \file ax5043spi_p.h
|
||||
\brief Provides an abstraction layer for the SPI interface communicating to the digital transceiver
|
||||
*/
|
||||
|
||||
#ifndef AX5043SPI_P_H_
|
||||
#define AX5043SPI_P_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SPI_CHANNEL (0) //!< The default SPI channel for the digital transceiver
|
||||
#define SPI_SPEED (32000000) //!< The default SPI bus speed for the digital transceiver
|
||||
|
||||
/*! \fn void setSpiChannel(int newSpiChannel)
|
||||
\brief Set the SPI channel for the digital transceiver.
|
||||
|
||||
setSpiChannel must be called before initializeSpi(). The default is SPI_CHANNEL.
|
||||
\param newSpiChannel The SPI channel for the digital transceiver.
|
||||
\sa SPI_CHANNEL
|
||||
\sa initializeSpi
|
||||
*/
|
||||
void setSpiChannel(int newSpiChannel);
|
||||
|
||||
/*! \fn void setSpiSpeed(int newSpiSpeed)
|
||||
\brief Set the SPI bus speed for the digital transceiver.
|
||||
|
||||
|
||||
setSpiSpeed must be called before initializeSpi(). The default is SPI_SPEED.
|
||||
\param newSpiSpeed The SPI bus speed for the digital transceiver.
|
||||
\sa SPI_SPEED
|
||||
\sa initializeSpi
|
||||
*/
|
||||
void setSpiSpeed(int newSpiSpeed);
|
||||
|
||||
/*! \fn void initializeSpi()
|
||||
\brief Initilize the SPI bus to communicate with the digital transceiver.
|
||||
|
||||
setSpiChannel() and setSpiSpeed() must both be called before initializeSPI().
|
||||
\sa setSpiChannel
|
||||
\sa setSpiSpeed
|
||||
*/
|
||||
void initializeSpi(void);
|
||||
|
||||
/*! \fn void ax5043WriteReg(uint16_t reg, uint8_t val)
|
||||
\brief Write a value to an AX5043 register.
|
||||
\param reg The register to write.
|
||||
\param val The value to right to the register.
|
||||
*/
|
||||
void ax5043WriteReg(uint16_t reg, uint8_t val);
|
||||
|
||||
/*! \fn uint8_t ax5043ReadReg(uint16_t reg)
|
||||
\brief Read a value from an AX5043 register.
|
||||
\param reg The register to read.
|
||||
\return The value read from the register.
|
||||
*/
|
||||
uint8_t ax5043ReadReg(uint16_t reg);
|
||||
|
||||
#endif /* AX5043SPI_P_H_ */
|
||||
Loading…
Reference in new issue