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/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hal.h"
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#include "si5351.h"
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#define SI5351_I2C_ADDR (0x60<<1)
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static void
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rcc_gpio_init(void)
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{
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// Reset AHB,APB1,APB2
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RCC->AHBRSTR |= 0xffffffff;
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RCC->AHBRSTR = 0;
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RCC->APB1RSTR |= 0xffffffff;
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RCC->APB1RSTR = 0;
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RCC->APB2RSTR |= 0xffffffff;
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RCC->APB2RSTR = 0;
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RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_I2C1EN;
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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RCC->CFGR3 |= RCC_CFGR3_I2C1SW_HSI;
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// STM32F072
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GPIOB->AFRH = 0x55550011; // PB8,PB9 Alternate Function 1
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// STM32F303
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//GPIOB->AFRH = 0x55550044; // PB8,PB9 Alternate Function 4
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GPIOB->OTYPER |= 0x0300; // PB8,PB9 Open drain
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GPIOB->MODER |= 0x000A0000;//
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GPIOB->OSPEEDR |= 0x00050000;//
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}
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static void
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i2c_init(I2C_TypeDef* i2c)
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{
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// Disable the I2Cx peripheral
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i2c->CR1 &= ~I2C_CR1_PE;
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while (i2c->CR1 & I2C_CR1_PE);
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// 100kHz @ 8MHz
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i2c->TIMINGR = 0x10420F13;
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// Use 7-bit addresses
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i2c->CR2 &=~ I2C_CR2_ADD10;
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// Enable the analog filter
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i2c->CR1 &= ~I2C_CR1_ANFOFF;
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// Disable NOSTRETCH
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i2c->CR1 |= I2C_CR1_NOSTRETCH;
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// Enable I2Cx peripheral clock.
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// Select APB1 as clock source
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if (i2c == I2C1) {
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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} else if (i2c == I2C2) {
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RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
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}
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// Enable the I2Cx peripheral
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i2c->CR1 |= I2C_CR1_PE;
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}
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static void
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i2cSendByte(I2C_TypeDef* i2c, uint8_t addr, const uint8_t *buf, uint8_t len)
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{
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i2c->CR2 = (I2C_CR2_SADD & addr) // Set the slave address
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| (I2C_CR2_NBYTES & (len << 16)) // Send one byte
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| I2C_CR2_START // Generate start condition
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| I2C_CR2_AUTOEND; // Generate stop condition after sent
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// Send the data
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while (len-- > 0) {
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while (!(i2c->ISR & I2C_ISR_TXIS));
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i2c->TXDR = (I2C_TXDR_TXDATA & *buf++);
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}
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}
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// register addr, length, data, ...
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const uint8_t si5351_configs_low[] = {
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff,
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4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN,
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2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF,
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// setup PLL (26MHz * 32 = 832MHz : 32/2-2=14)
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9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0,
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// RESET PLL
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2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B,
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// setup multisynth (832MHz/8MHz=104,104/2-2=50)
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9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0,
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2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE,
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0,
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0 // sentinel
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};
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void
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si5351_init_bulk(void)
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{
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const uint8_t *p = si5351_configs_low;
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while (*p) {
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uint8_t len = *p++;
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i2cSendByte(I2C1, SI5351_I2C_ADDR, p, len);
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p += len;
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}
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}
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void
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si5351_setup(void)
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{
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rcc_gpio_init();
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i2c_init(I2C1);
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si5351_init_bulk();
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}
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