Merge pull request #4 from ttrftech/harmonic_mode

Add Harmonic mode (900MHz)

main.c

@@ -41,9 +41,12 @@ void sweep(void);
 
 static MUTEX_DECL(mutex);
 
+#define DRIVE_STRENGTH_AUTO (-1)
+#define FREQ_HARMONICS 300000000
+
 int32_t frequency_offset = 5000;
 int32_t frequency = 10000000;
-uint8_t drive_strength = SI5351_CLK_DRIVE_STRENGTH_2MA;
+int8_t drive_strength = DRIVE_STRENGTH_AUTO;
 int8_t frequency_updated = FALSE;
 int8_t sweep_enabled = TRUE;
 int8_t cal_auto_interpolate = TRUE;
@@ -126,10 +129,25 @@ static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[])
 int set_frequency(int freq)
 {
     int delay = 0;
-    if (frequency != freq) {
+    if (frequency == freq)
-      delay = si5351_set_frequency_with_offset(freq, frequency_offset, drive_strength);
+      return delay;
-      frequency = freq;
+
+    if (freq > FREQ_HARMONICS && frequency <= FREQ_HARMONICS) {
+      tlv320aic3204_set_gain(30, 30);
+      delay += 10;
+    }
+    if (freq <= FREQ_HARMONICS && frequency > FREQ_HARMONICS) {
+      tlv320aic3204_set_gain(0, 0);
+      delay += 10;
     }
+
+    int8_t ds = drive_strength;
+    if (ds == DRIVE_STRENGTH_AUTO) {
+      ds = freq > FREQ_HARMONICS ? SI5351_CLK_DRIVE_STRENGTH_8MA : SI5351_CLK_DRIVE_STRENGTH_2MA;
+    }
+    delay += si5351_set_frequency_with_offset(freq, frequency_offset, ds);
+
+    frequency = freq;
     return delay;
 }
 
@@ -160,7 +178,7 @@ static void cmd_freq(BaseSequentialStream *chp, int argc, char *argv[])
 static void cmd_power(BaseSequentialStream *chp, int argc, char *argv[])
 {
     if (argc != 1) {
-        chprintf(chp, "usage: power {0-3}\r\n");
+        chprintf(chp, "usage: power {0-3|-1}\r\n");
         return;
     }
     drive_strength = atoi(argv[0]);
@@ -458,10 +476,10 @@ void sweep(void)
 
  rewind:
   frequency_updated = FALSE;
-  delay = 3;
+  //delay = 3;
 
   for (i = 0; i < sweep_points; i++) {
-    set_frequency(frequencies[i]);
+    delay = set_frequency(frequencies[i]);
     tlv320aic3204_select_in3(); // CH0:REFLECT
     wait_dsp(delay);
 
@@ -587,7 +605,7 @@ freq_mode_centerspan(void)
 
 
 #define START_MIN 50000
-#define STOP_MAX 300000000
+#define STOP_MAX 900000000
 
 void
 set_sweep_frequency(int type, float frequency)

si5351.c

@@ -306,9 +306,13 @@ int
 si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
 {
   int band;
-  int delay = 5;
+  int delay = 3;
   uint32_t ofreq = freq + offset;
   uint32_t rdiv = SI5351_R_DIV_1;
+  if (freq > 300000000) {
+    freq /= 3;
+    ofreq /= 5;
+  }
   if (freq <= 100000000) {
     band = 0;
   } else if (freq < 150000000) {
@@ -356,13 +360,13 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
   case 1:
     // Set PLL twice on changing from band 2
     if (current_band == 2) {
-      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
+      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
                                     SI5351_CLK_DRIVE_STRENGTH_2MA);
       si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     }
 
     // div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
                                   SI5351_CLK_DRIVE_STRENGTH_2MA);
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
@@ -371,11 +375,11 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
 
   case 2:
     // div by 4 mode. both PLL A and B are dedicated for CLK0, CLK1
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4,
+                                  SI5351_CLK_DRIVE_STRENGTH_2MA);
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
                                   SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 4,
-                                  SI5351_CLK_DRIVE_STRENGTH_2MA);
     break;
   }
 
@@ -384,7 +388,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
 #if 1
     si5351_enable_output();
 #endif
-    delay += 0;
+    delay += 10;
   }
 
   current_band = band;

tlv320aic3204.c

@@ -81,6 +81,12 @@ void tlv320aic3204_init(void)
     I2CWrite(AIC3204_ADDR, 0x13, 0x82); /* Power up the MADC divider with value 2 */
     I2CWrite(AIC3204_ADDR, 0x14, 0x80); /* Program the OSR of ADC to 128 */
     I2CWrite(AIC3204_ADDR, 0x3d, 0x01); /* Select ADC PRB_R1 */
+#if 0
+  tlv320aic3204_adc_filter_enable(TRUE);
+  I2CWrite(AIC3204_ADDR, 0x00, 0x08); // Select page 8, Disable Adaptive Filtering for ADC
+  I2CWrite(AIC3204_ADDR, 0x01, 0x00);
+  tlv320aic3204_config_adc_filter();
+#endif
     I2CWrite(AIC3204_ADDR, 0x00, 0x01); /* Select Page 1 */
     I2CWrite(AIC3204_ADDR, 0x3d, 0x00); /* Select ADC PTM_R4 */
     I2CWrite(AIC3204_ADDR, 0x47, 0x32); /* Set MicPGA startup delay to 3.1ms */
@@ -97,8 +103,8 @@ void tlv320aic3204_init(void)
     I2CWrite(AIC3204_ADDR, 0x51, 0xc0); /* Power up Left and Right ADC Channels */
     I2CWrite(AIC3204_ADDR, 0x52, 0x00); /* Unmute Left and Right ADC Digital Volume Control */    
 
-    //tlv320aic3204_config_adc_filter();
+    tlv320aic3204_config_adc_filter();
-    //tlv320aic3204_adc_filter_enable(TRUE);
+    tlv320aic3204_adc_filter_enable(TRUE);
 }
 
 void tlv320aic3204_select_in3(void)