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multi_trace
erikkaashoek 5 years ago
parent 125aba6e7c
commit c1a40c5dca
5 changed files with 69 additions and 53 deletions
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50
radio_config_Si4468_10kHz.h
Unescape View File

@ -19,15 +19,15 @@
// INPUT DATA
/*
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15
// MOD_type: 2 Rsymb(sps): 19000 Fdev(Hz): 100000 RXBW(Hz): 10000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2
// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1
// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
// MOD_type: 2 Rsymb(sps): 5000 Fdev(Hz): 2500 RXBW(Hz): 10000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1
// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1
//
// # RX IF frequency is -468750 Hz
// # WB filter 13 (BW = 10.65 kHz); NB-filter 13 (BW = 10.65 kHz)
// # WB filter 4 (BW = 10.33 kHz); NB-filter 4 (BW = 10.33 kHz)
//
// Modulation index: 10.526
// Modulation index: 1
*/
@ -161,7 +161,7 @@
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
*/
#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11
#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11
/*
// Set properties: RF_MODEM_AFC_LIMITER_1_3
@ -222,7 +222,7 @@
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
*/
#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00
#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
/*
// Set properties: RF_MODEM_RSSI_JUMP_THRESH_4
@ -260,7 +260,7 @@
// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
*/
#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07
#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
/*
// Set properties: RF_MODEM_RSSI_MUTE_1
@ -286,7 +286,7 @@
// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
*/
#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20
#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
@ -398,7 +398,7 @@
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF
/*
// Command: RF_START_RX
@ -474,7 +474,7 @@
// Descriptions:
// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
*/
#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14
#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88
/*
// Set properties: RF_PKT_CONFIG1_1
@ -507,7 +507,7 @@
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x02, 0xE6, 0x30, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x0D
#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0xC3, 0x50, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x00
/*
// Set properties: RF_MODEM_FREQ_DEV_0_1_1
@ -518,7 +518,7 @@
// Descriptions:
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7
#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x57
/*
// Set properties: RF_MODEM_TX_RAMP_DELAY_12_1
@ -540,7 +540,7 @@
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
*/
#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x30, 0x50, 0x00, 0xB5, 0x00, 0x42
#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x20, 0x0C, 0xB5, 0x00, 0x5E
/*
// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1
@ -562,7 +562,7 @@
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
*/
#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xC8, 0x4B, 0x03, 0xE1, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0x0E
#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x76, 0x1A, 0x05, 0x72, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x16
/*
// Set properties: RF_MODEM_AFC_LIMITER_1_3_1
@ -575,7 +575,7 @@
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
*/
#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x53, 0x80
#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCE, 0xA0
/*
// Set properties: RF_MODEM_AGC_CONTROL_1_1
@ -608,7 +608,7 @@
// MODEM_OOK_CNT1 - OOK control.
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
*/
#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0E, 0x0E, 0x80, 0x02, 0xFF, 0xFF, 0x00, 0x28, 0x0C, 0x84, 0x23
#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x15, 0x15, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
/*
// Set properties: RF_MODEM_RAW_CONTROL_10
@ -628,7 +628,7 @@
// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
// MODEM_RSSI_COMP - RSSI compensation value.
*/
#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x07, 0xFF, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40
#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x55, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40
/*
// Set properties: RF_MODEM_RAW_SEARCH2_2_1
@ -652,7 +652,7 @@
// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
*/
#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0xC2, 0xA7
#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07
/*
// Set properties: RF_MODEM_RSSI_MUTE_1_1
@ -678,7 +678,7 @@
// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
*/
#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x44, 0x7F, 0x78, 0x20
#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
@ -700,7 +700,7 @@
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
@ -722,7 +722,7 @@
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
/*
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
@ -744,7 +744,7 @@
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
/*
// Set properties: RF_PA_TC_1_1
@ -790,7 +790,7 @@
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF
#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF
// AUTOMATICALLY GENERATED CODE!

52
radio_config_Si4468_30kHz.h
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@ -19,15 +19,15 @@
// INPUT DATA
/*
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15
// MOD_type: 2 Rsymb(sps): 58000 Fdev(Hz): 100000 RXBW(Hz): 30000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2
// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1
// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
// MOD_type: 2 Rsymb(sps): 30000 Fdev(Hz): 7500 RXBW(Hz): 30000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2
// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1
// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1
//
// # RX IF frequency is -468750 Hz
// # WB filter 13 (BW = 31.96 kHz); NB-filter 13 (BW = 31.96 kHz)
// # WB filter 9 (BW = 32.77 kHz); NB-filter 9 (BW = 32.77 kHz)
//
// Modulation index: 3.448
// Modulation index: 0.5
*/
@ -161,7 +161,7 @@
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
*/
#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11
#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11
/*
// Set properties: RF_MODEM_AFC_LIMITER_1_3
@ -222,7 +222,7 @@
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
*/
#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00
#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00
/*
// Set properties: RF_MODEM_RSSI_JUMP_THRESH_4
@ -260,7 +260,7 @@
// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
*/
#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07
#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
/*
// Set properties: RF_MODEM_RSSI_MUTE_1
@ -286,7 +286,7 @@
// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
*/
#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20
#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
@ -398,7 +398,7 @@
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF
/*
// Command: RF_START_RX
@ -474,7 +474,7 @@
// Descriptions:
// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
*/
#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14
#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88
/*
// Set properties: RF_PKT_CONFIG1_1
@ -507,7 +507,7 @@
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x08, 0xD9, 0xA0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x0D
#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x04, 0x93, 0xE0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x01
/*
// Set properties: RF_MODEM_FREQ_DEV_0_1_1
@ -518,7 +518,7 @@
// Descriptions:
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
*/
#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7
#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x06
/*
// Set properties: RF_MODEM_TX_RAMP_DELAY_12_1
@ -540,7 +540,7 @@
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
*/
#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xB5, 0x00, 0x41
#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x10, 0x00, 0xB5, 0x00, 0x53
/*
// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1
@ -562,7 +562,7 @@
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
*/
#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xEB, 0x3F, 0x03, 0xF0, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0x2B
#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x83
/*
// Set properties: RF_MODEM_AFC_LIMITER_1_3_1
@ -575,7 +575,7 @@
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
*/
#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x36, 0x80
#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xF5, 0xA0
/*
// Set properties: RF_MODEM_AGC_CONTROL_1_1
@ -608,7 +608,7 @@
// MODEM_OOK_CNT1 - OOK control.
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
*/
#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0E, 0x0E, 0x80, 0x02, 0xDC, 0xB1, 0x00, 0x28, 0x0C, 0x84, 0x23
#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x02, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23
/*
// Set properties: RF_MODEM_RAW_CONTROL_10
@ -628,7 +628,7 @@
// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control.
// MODEM_RSSI_COMP - RSSI compensation value.
*/
#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x06, 0xA8, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40
#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xC0, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40
/*
// Set properties: RF_MODEM_RAW_SEARCH2_2_1
@ -652,7 +652,7 @@
// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection.
// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition.
*/
#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x96, 0xA7
#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07
/*
// Set properties: RF_MODEM_RSSI_MUTE_1_1
@ -678,7 +678,7 @@
// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config
// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits.
*/
#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x44, 0x32, 0x78, 0x20
#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
@ -700,7 +700,7 @@
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2
/*
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
@ -722,7 +722,7 @@
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55
/*
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
@ -744,7 +744,7 @@
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
*/
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F
/*
// Set properties: RF_PA_TC_1_1
@ -755,7 +755,7 @@
// Descriptions:
// PA_TC - Configuration of PA ramping parameters.
*/
#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x3D
#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x1D
/*
// Set properties: RF_SYNTH_PFDCP_CPFF_7_1
@ -790,7 +790,7 @@
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF
#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF
// AUTOMATICALLY GENERATED CODE!

2
sa_cmd.c
Unescape View File

@ -978,7 +978,7 @@ VNA_SHELL_FUNCTION(cmd_scanraw)
for (uint32_t i = 0; i<points; i++) {
int val = perform(false, i, start +(freq_t)(f_step * i), false) + float_TO_PURE_RSSI(config.ext_zero_level);
if (operation_requested && SDU1.config->usbp->state != USB_ACTIVE) // break on operation in perform
if (operation_requested || SDU1.config->usbp->state != USB_ACTIVE) // break on operation in perform
break;
streamPut(shell_stream, 'x');
streamPut(shell_stream, (uint8_t)(val & 0xFF));

2
sa_core.c
Unescape View File

@ -1460,7 +1460,7 @@ static const struct {
{ 3000, 150, 50, 200, -95},
{ 1000, 600, 100, 100, -105},
{ 300, 800, 120, 100, -110},
{ 100, 800, 120, 100, -115},
{ 100, 1500, 120, 100, -115},
{ 30, 1500, 300, 100, -120},
{ 10, 5000, 600, 100, -122},
{ 3, 19000, 12000, 100, -125}

16
ui_sa.c
Unescape View File

@ -1123,6 +1123,21 @@ static UI_FUNCTION_ADV_CALLBACK(menu_debug_freq_acb)
}
#endif
static UI_FUNCTION_CALLBACK(menu_clearconfig_cb)
{
(void)data;
(void)item;
kp_help_text = "Clear unlock code";
ui_mode_keypad(KM_CENTER);
if (uistat.value != 1234)
return;
clear_all_config_prop_data();
reset_settings(M_LOW);
ui_mode_normal();
}
const char * const averageText[] = { "OFF", "MIN", "MAX", "MAXD", " A 4", "A 16","QUASI", "DECONV"};
@ -2461,6 +2476,7 @@ static const menuitem_t menu_settings4[] =
{ MT_KEYPAD, KM_COR_WFM, "COR\nWFM", "Enter WFM modulation correction"},
{ MT_KEYPAD, KM_COR_NFM, "COR\nNFM", "Enter NFM modulation correction"},
#endif
{ MT_CALLBACK, 0 , "CLEAR\nCONFIG", menu_clearconfig_cb},
#ifdef __HARMONIC__
{ MT_SUBMENU,0, "HARMONIC", menu_harmonic},
#endif

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