Improve sweep speed about 60%
Stop generation on pause sweep
Remove all hack for si5351
Reduce code size
Fix integer overflow on big freq values
Additional
Change I2C
Others:
move marker_tracking variable to ui config
move some definition to correct place
reduce tlv320aic3204 code size
Speedup marker move from lever (BUTTON_REPEAT_TICKS = 625)
Need test stability
0x0b,0x82,/* Power up the NDAC divider with value 2 */
0x0c,0x87,/* Power up the MDAC divider with value 7 */
0x0d,0x00,/* Program the OSR of DAC to 128 */
0x0e,0x80,
0x3c,0x08,/* Set the DAC Mode to PRB_P8 */
//0x3c, 25, /* Set the DAC Mode to PRB_P25 */
0x1b,0x0c,/* Set the BCLK,WCLK as output */
0x1e,0x80+28,/* Enable the BCLKN divider with value 28 */
0x25,0xee,/* DAC power up */
// default fs=48kHz
0x12,0x82,/* Power up the NADC divider with value 2 */
staticconstuint8_tconf_data_clk[]={
0x13,0x87,/* Power up the MADC divider with value 7 */
2,0x0b,0x82,/* Power up the NDAC divider with value 2 */
0x14,0x80,/* Program the OSR of ADC to 128 */
2,0x0c,0x87,/* Power up the MDAC divider with value 7 */
0x3d,0x01,/* Select ADC PRB_R1 */
2,0x0d,0x00,/* Program the OSR of DAC to 128 */
// Data routing
2,0x0e,0x80,
0x00,0x01,/* Select Page 1 */
2,0x3c,0x08,/* Set the DAC Mode to PRB_P8 */
0x01,0x08,/* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
//2, 0x3c, 25, /* Set the DAC Mode to PRB_P25 */
0x02,0x01,/* Enable Master Analog Power Control */
2,0x1b,0x0c,/* Set the BCLK,WCLK as output */
0x7b,0x01,/* Set the REF charging time to 40ms */
2,0x1e,0x80+28,/* Enable the BCLKN divider with value 28 */
0x14,0x25,/* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */
2,0x25,0xee,/* DAC power up */
0x0a,0x33,/* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */
2,0x12,0x82,/* Power up the NADC divider with value 2 */
0x3d,0x00,/* Select ADC PTM_R4 */
2,0x13,0x87,/* Power up the MADC divider with value 7 */
0x47,0x32,/* Set MicPGA startup delay to 3.1ms */
2,0x14,0x80,/* Program the OSR of ADC to 128 */
0x7b,0x01,/* Set the REF charging time to 40ms */
2,0x3d,0x01,/* Select ADC PRB_R1 */
0x34,0x10,/* Route IN2L to LEFT_P with 10K */
0// sentinel
0x36,0x10,/* Route IN2R to LEFT_N with 10K */
//0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */
//0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */
//0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */
//0x3c, 0x00, /* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */
};
};
staticconstuint8_tconf_data_routing[]={
staticconstuint8_tconf_data_unmute[]={
2,0x00,0x01,/* Select Page 1 */
// reg, data,
2,0x01,0x08,/* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
0x00,0x00,/* Select Page 0 */
2,0x02,0x01,/* Enable Master Analog Power Control */
0x51,0xc0,/* Power up Left and Right ADC Channels */
2,0x7b,0x01,/* Set the REF charging time to 40ms */
0x52,0x00,/* Unmute Left and Right ADC Digital Volume Control */
2,0x14,0x25,/* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */
};
2,0x0a,0x33,/* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */
2,0x3d,0x00,/* Select ADC PTM_R4 */
staticconstuint8_tconf_data_ch3_select[]={
2,0x47,0x32,/* Set MicPGA startup delay to 3.1ms */
// reg, data,
2,0x7b,0x01,/* Set the REF charging time to 40ms */
0x00,0x01,/* Select Page 1 */
2,0x34,0x10,/* Route IN2L to LEFT_P with 10K */
0x37,0x04,/* Route IN3R to RIGHT_P with input impedance of 10K */
2,0x36,0x10,/* Route IN2R to LEFT_N with 10K */
0x39,0x04,/* Route IN3L to RIGHT_N with input impedance of 10K */
2,0x37,0x04,/* Route IN3R to RIGHT_P with 10K */
2,0x39,0x04,/* Route IN3L to RIGHT_N with 10K */
2,0x3b,0,/* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */
2,0x3c,0,/* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */
0// sentinel
};
};
const uint8_tconf_data_unmute[]={
staticconstuint8_tconf_data_ch1_select[]={
2,0x00,0x00,/* Select Page 0 */
// reg, data,
2,0x51,0xc0,/* Power up Left and Right ADC Channels */
0x00,0x01,/* Select Page 1 */
2,0x52,0x00,/* Unmute Left and Right ADC Digital Volume Control */
0x37,0x40,/* Route IN1R to RIGHT_P with input impedance of 10K */
0// sentinel
0x39,0x10,/* Route IN1L to RIGHT_N with input impedance of 10K */
DiSlord
6 years ago