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@ -223,7 +223,7 @@ void SI4432_Drive(int d)
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void SI4432_Transmit(int d)
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{
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int count = 0;
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SI4432_Write_Byte(SI4432_TX_POWER, (uint8_t) (0x18+(d & 7)));
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SI4432_Drive(d);
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if (( SI4432_Read_Byte(SI4432_DEV_STATUS) & 0x03 ) == 2)
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return; // Already in transmit mode
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chThdSleepMilliseconds(3);
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@ -625,84 +625,40 @@ pureRSSI_t SI4432_RSSI(uint32_t i, int s)
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return RSSI_RAW;
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}
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static uint8_t SI4432_init_script[] =
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{
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SI4432_INT_ENABLE1, 0x0,
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SI4432_INT_ENABLE2, 0x0,
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SI4432_CLOCK_RECOVERY_GEARSHIFT, 0x00,
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SI4432_AGC_OVERRIDE, 0x60,
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SI4432_AFC_LOOP_GEARSHIFT_OVERRIDE, 0x00,
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SI4432_AFC_TIMING_CONTROL, 0x02,
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SI4432_CLOCK_RECOVERY_GEARSHIFT, 0x03,
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SI4432_CLOCK_RECOVERY_OFFSET2, 0x01,
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SI4432_CLOCK_RECOVERY_OFFSET1, 0x11,
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SI4432_CLOCK_RECOVERY_OFFSET0, 0x11,
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SI4432_CLOCK_RECOVERY_TIMING_GAIN1, 0x01,
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SI4432_CLOCK_RECOVERY_TIMING_GAIN0, 0x13,
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SI4432_AFC_LIMITER, 0xFF,
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SI4432_DATAACCESS_CONTROL, 0x61, // Disable all packet handling
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SI4432_AGC_OVERRIDE, 0x60, // AGC, no LNA, fast gain increment
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SI4432_GPIO0_CONF, 0x12, // Normal
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SI4432_GPIO1_CONF, 0x15,
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SI4432_GPIO2_CONF, 0x1F
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};
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void SI4432_Sub_Init(void)
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{
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SI4432_Reset();
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SI4432_Write_Byte(SI4432_AGC_OVERRIDE, 0x60); //AGC override according to WBS3
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#if 0 // Not sure if these add any value
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//set VCO and PLL Only for SI4432 V2
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SI4432_Write_Byte(SI4432_FREQ_DEVIATION, 0x1F); //write 0x1F to the Frequency Deviation register
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// VCO tuning registers
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SI4432_Write_Byte(SI4432_VCO_CURRENT_TRIM, 0x7F); //write 0x7F to the VCO Current Trimming register
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SI4432_Write_Byte(SI4432_CHARGEPUMP_OVERRIDE, 0x80); //write 0xD7 to the ChargepumpCurrentTrimmingOverride register
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SI4432_Write_Byte(SI4432_DIVIDER_CURRENT_TRIM, 0x40); //write 0x40 to the Divider Current Trimming register
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#endif
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#if 0
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//set the AGC, BAD FOR PERFORMANCE!!!!!!
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SI4432_Write_Byte(0x6A, 0x0B); //write 0x0B to the AGC Override 2 register
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//set ADC reference voltage to 0.9V, BAD FOR PERFORMANCE!!!!!!
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SI4432_Write_Byte(0x68, 0x04); //write 0x04 to the Deltasigma ADC Tuning 2 register
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SI4432_Write_Byte(0x1F, 0x03); //write 0x03 to the Clock Recovery Gearshift Override register
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#endif
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SI4432_Write_Byte(SI4432_INT_ENABLE1, 0x0);
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SI4432_Write_Byte(SI4432_INT_ENABLE2, 0x0);
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// Enable receiver chain
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// SI4432_Write_Byte(SI4432_STATE, 0x05);
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// Clock Recovery Gearshift Value
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_GEARSHIFT, 0x00);
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uint8_t *p = SI4432_init_script;
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while (*p) {
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uint8_t r = *p++;
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uint8_t v = *p++;
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SI4432_Write_Byte (r,v);
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}
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// IF Filter Bandwidth
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set_rbw(100) ;
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// // Register 0x75 Frequency Band Select
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// uint8_t sbsel = 1 ; // recommended setting
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// uint8_t hbsel = 0 ; // low bands
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// uint8_t fb = 19 ; // 430<33>439.9 MHz
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// uint8_t FBS = (sbsel << 6 ) | (hbsel << 5 ) | fb ;
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// SI4432_Write_Byte(SI4432_FREQBAND, FBS) ;
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// SI4432_Write_Byte(SI4432_FREQBAND, 0x46) ;
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// Register 0x76 Nominal Carrier Frequency
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// WE USE 433.92 MHz
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// Si443x-Register-Settings_RevB1.xls
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// SI4432_Write_Byte(SI4432_FREQCARRIER_H, 0x62) ;
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// SI4432_Write_Byte(SI4432_FREQCARRIER_H, 0x00) ;
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// Register 0x77 Nominal Carrier Frequency
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// SI4432_Write_Byte(SI4432_FREQCARRIER_L, 0x00) ;
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// RX MODEM SETTINGS
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// SI4432_Write_3_Byte(SI4432_IF_FILTER_BW, 0x81, 0x3C, 0x02) ; // <----------
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// SI4432_Write_Byte(SI4432_IF_FILTER_BW, 0x81) ; // <----------
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SI4432_Write_Byte(SI4432_AFC_LOOP_GEARSHIFT_OVERRIDE, 0x00) ;
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SI4432_Write_Byte(SI4432_AFC_TIMING_CONTROL, 0x02) ;
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_GEARSHIFT, 0x03) ;
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// SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_OVERSAMPLING, 0x78) ; // <----------
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// SI4432_Write_3_Byte(SI4432_CLOCK_RECOVERY_OFFSET2, 0x01, 0x11, 0x11) ; // <----------
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_OFFSET2, 0x01) ;
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_OFFSET1, 0x11) ;
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_OFFSET0, 0x11) ;
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_TIMING_GAIN1, 0x01) ;
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SI4432_Write_Byte(SI4432_CLOCK_RECOVERY_TIMING_GAIN0, 0x13) ;
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SI4432_Write_Byte(SI4432_AFC_LIMITER, 0xFF) ;
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// SI4432_Write_3_Byte(0x2C, 0x28, 0x0c, 0x28) ; // <----------
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// SI4432_Write_Byte(Si4432_OOK_COUNTER_VALUE_1, 0x28) ;
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// SI4432_Write_Byte(Si4432_OOK_COUNTER_VALUE_2, 0x0C) ;
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// SI4432_Write_Byte(Si4432_SLICER_PEAK_HOLD, 0x28) ;
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SI4432_Write_Byte(SI4432_DATAACCESS_CONTROL, 0x61); // Disable all packet handling
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SI4432_Write_Byte(SI4432_AGC_OVERRIDE, 0x60); // AGC, no LNA, fast gain increment
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// GPIO automatic antenna switching
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SI4432_Write_Byte(SI4432_GPIO0_CONF, 0x12) ; // Normal
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SI4432_Write_Byte(SI4432_GPIO1_CONF, 0x15) ;
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// set_rbw(100) ;
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// SI4432_Receive();
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@ -738,24 +694,6 @@ void SI4432_Init()
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SI4432_Sel = SI4432_LO;
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SI4432_Sub_Init();
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//DebugLine("1 init done");
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SI4432_Sel = SI4432_RX;
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// SI4432_Receive();// Enable receiver chain
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// SI4432_Write_Byte(Si4432_CRYSTAL_OSC_LOAD_CAP, V0_XTAL_CAPACITANCE);// Tune the crystal
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// SI4432_Set_Frequency(433800000);
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SI4432_Write_Byte(SI4432_GPIO2_CONF, 0x1F) ; // Set GPIO2 output to ground
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SI4432_Sel = SI4432_LO;
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// SI4432_Write_Byte(Si4432_CRYSTAL_OSC_LOAD_CAP, V1_XTAL_CAPACITANCE);// Tune the crystal
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// SI4432_Set_Frequency(443800000);
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SI4432_Write_Byte(SI4432_GPIO2_CONF, 0x1F) ; // Set GPIO2 output to ground
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// SI4432_Write_Byte(SI4432_TX_POWER, 0x1C);//Set low power
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// SI4432_Transmit(0);
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// SI4432_Write_Byte(SI4432_GPIO2_CONF, 0xC0) ; // Set GPIO2 maximumdrive and clock output
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// SI4432_Write_Byte(Si4432_UC_OUTPUT_CLOCK, 0x02) ; // Set 10MHz output
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}
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void set_calibration_freq(int freq)
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