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All sweep working

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Removed_REF_marker
erikkaashoek 5 years ago
parent c488f83e10
commit 80a02da450
3 changed files with 171 additions and 15 deletions
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26
sa_core.c
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@ -116,11 +116,11 @@ void reset_settings(int m)
switch(m) {
case M_LOW:
minFreq = 0;
maxFreq = 350000000;
maxFreq = 4000000000;
set_sweep_frequency(ST_START, (uint32_t) 0);
set_sweep_frequency(ST_STOP, (uint32_t) 350000000);
setting.attenuate = 30.0;
setting.auto_attenuation = true;
setting.attenuate = 0.0; // <---------------- WARNING -----------------
setting.auto_attenuation = false; // <---------------- WARNING -----------------
setting.sweep_time_us = 0;
break;
#ifdef __ULTRA__
@ -146,8 +146,8 @@ void reset_settings(int m)
minFreq = 00000000;
maxFreq = 2000000000;
#else
minFreq = 24*setting_frequency_10mhz;
maxFreq = 96*setting_frequency_10mhz;
minFreq = 13*setting_frequency_10mhz;
maxFreq = 120*setting_frequency_10mhz;
#endif
set_sweep_frequency(ST_START, minFreq);
set_sweep_frequency(ST_STOP, maxFreq);
@ -1078,9 +1078,12 @@ void set_freq(int V, unsigned long freq) // translate the requested frequency
}
} else
#endif
if (V==2){
if (V==ADF4351_LO){
ADF4351_set_frequency(V-2,freq,3);
}
if (V==SI4463_RX) {
SI4463_set_freq(freq,1000);
}
#ifdef __ULTRA_SA__
else {
ADF4351_set_frequency(V-2,freq,3);
@ -1619,6 +1622,9 @@ pureRSSI_t perform(bool break_on_operation, int i, uint32_t f, int tracking)
if (setting.mode == M_LOW && tracking) { // VERY SPECIAL CASE!!!!! Measure BPF
#ifdef __SI4432__
set_freq (SI4432_RX , local_IF + lf - reffer_freq[setting.refer]); // Offset so fundamental of reffer is visible
#endif
#ifdef __SI4463__
set_freq (SI4463_RX , local_IF + lf - reffer_freq[setting.refer]); // Offset so fundamental of reffer is visible
#endif
} else if (MODE_LOW(setting.mode)) {
if (setting.mode == M_LOW && !in_selftest && avoid_spur(f)) { // check is alternate IF is needed to avoid spur.
@ -1648,11 +1654,17 @@ pureRSSI_t perform(bool break_on_operation, int i, uint32_t f, int tracking)
#ifdef __SI4432__
set_freq (SI4432_RX , local_IF);
#endif
#ifdef __SI4463__
set_freq (SI4463_RX , local_IF);
#endif
#ifdef __ULTRA__
} else if (setting.mode == M_ULTRA) { // No above/below IF mode in Ultra
local_IF = setting.frequency_IF + (int)(actual_rbw < 350.0 ? setting.spur*300000 : 0 );
#ifdef __SI4432__
set_freq (SI4432_RX , local_IF);
#endif
#ifdef __SI4463__
set_freq (SI4463_RX , local_IF);
#endif
// local_IF = setting.frequency_IF + (int)(actual_rbw < 300.0?setting.spur * 1000 * actual_rbw:0);
#endif
@ -1703,6 +1715,8 @@ pureRSSI_t perform(bool break_on_operation, int i, uint32_t f, int tracking)
set_freq (ADF4351_LO, local_IF-lf); // set LO SI4432 to below IF frequency
} else
set_freq (ADF4351_LO, local_IF+lf); // otherwise to above IF
} else if (setting.mode == M_HIGH) {
set_freq (SI4463_RX, local_IF+lf); // sweep RX
}
#endif
#endif

157
si4432.c
Unescape View File

@ -951,16 +951,16 @@ void ADF4351_Setup(void)
void ADF4351_WriteRegister32(int channel, const uint32_t value)
{
// set_SPI_mode(SPI_MODE_SI);
// chThdSleepMicroseconds(10);
set_SPI_mode(SPI_MODE_SI);
chThdSleepMicroseconds(2);
palClearPad(GPIOB, ADF4351_LE[channel]);
// chThdSleepMicroseconds(10);
chThdSleepMicroseconds(2);
for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF);
// chThdSleepMicroseconds(10);
palSetPad(GPIOB, ADF4351_LE[channel]);
// chThdSleepMicroseconds(10);
chThdSleepMicroseconds(2);
palClearPad(GPIOB, ADF4351_LE[channel]);
// chThdSleepMicroseconds(10);
chThdSleepMicroseconds(2);
}
void ADF4351_Set(int channel)
@ -1476,8 +1476,6 @@ again:
if (data[2] == 255)
goto again;
int16_t rssi = data[2] - 120 * 2;
if (rssi > 0)
rssi = -150*2;
return DEVICE_TO_PURE_RSSI(rssi);
}
@ -1495,6 +1493,148 @@ static uint16_t getADC(uint8_t adc_en, uint8_t adc_cfg, uint8_t part)
}
// -------------- 1kHz ----------------------------
#undef RF_MODEM_TX_RAMP_DELAY_8_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
#undef RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xF0, 0x11
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F
uint8_t SI4463_RBW_1kHz[] =
{
0x0C, RF_MODEM_TX_RAMP_DELAY_8_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
0x00
};
// -------------- kHz ----------------------------
#undef RF_MODEM_TX_RAMP_DELAY_8_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
#undef RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
uint8_t SI4463_RBW_kHz[] =
{
0x0C, RF_MODEM_TX_RAMP_DELAY_8_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
0x00
};
// -------------- 850kHz ----------------------------
#undef RF_MODEM_TX_RAMP_DELAY_8_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
#undef RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
uint8_t SI4463_RBW_850kHz[] =
{
0x0C, RF_MODEM_TX_RAMP_DELAY_8_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
0x00
};
void SI4463_set_freq(uint32_t freq, uint32_t step_size)
{
int Odiv;
int D;
float RFout=freq/1000000.0; // To MHz
if (RFout >= 820) { // till 1140MHz
Odiv = 8;
D = 2;
} else if (RFout >= 410) { // works till 570MHz
Odiv = 10;
D = 4;
} else if (RFout >= 272) { // to 380
Odiv = 11;
D = 6;
} else { // 136 { // To 190
Odiv = 13;
D = 12;
}
int32_t R = (RFout * D) / 26.0 - 1;
float MOD = 520251.0;
int32_t F = (((RFout * D) / 26.0) - R) * MOD;
int S = (int)(step_size / 14.305);
if (S == 0) S = 1;
/*
// Set properties: RF_FREQ_CONTROL_INTE_8
// Number of properties: 8
// Group ID: 0x40
// Start ID: 0x00
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
// Descriptions:
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
*/
// #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x00, 0x00, 0x00, 0x51, 0x20, 0xFE
uint8_t data[] = {
0x11, 0x40, 0x08, 0x00,
(uint8_t) R, // R data[4]
(uint8_t) ((F>>16) & 255), // F2,F1,F0 data[5] .. data[7]
(uint8_t) ((F>> 8) & 255), // F2,F1,F0 data[5] .. data[7]
(uint8_t) ((F ) & 255), // F2,F1,F0 data[5] .. data[7]
(uint8_t) ((S>> 8) & 255), // Step size data[8] .. data[9]
(uint8_t) ((S ) & 255), // Step size data[8] .. data[9]
0x20, // Window gate
0xFE // Adj count
};
setState(SI446X_STATE_TX_TUNE);
my_microsecond_delay(200);
SI4463_do_api(data, sizeof(data), NULL, 0);
/*
// Set properties: RF_MODEM_CLKGEN_BAND_1
// Number of properties: 1
// Group ID: 0x20
// Start ID: 0x51
// Default values: 0x08,
// Descriptions:
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
*/
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
uint8_t data2[] = {
0x11, 0x20, 0x01, 0x51,
(uint8_t)Odiv
};
SI4463_do_api(data2, sizeof(data2), NULL, 0);
SI4463_start_rx(0);
my_microsecond_delay(1000);
}
void SI4463_init(void)
{
@ -1519,6 +1659,7 @@ for(uint16_t i=0;i<sizeof(SI4463_config);i++)
#endif
// SI4463_do_api((void *)&SI4463_config[1], SI4463_config[0], NULL, 0);
SI4463_set_freq(433800000,1000);
//#define SI446X_ADC_SPEED 10
// RSSI = getADC(SI446X_ADC_CONV_BATT, (SI446X_ADC_SPEED<<4), 2);
@ -1526,7 +1667,7 @@ volatile si446x_state_t s ;
again:
Si446x_getInfo(&SI4463_info);
// s = getState();
SI4463_start_rx(90);
SI4463_start_rx(0);
my_microsecond_delay(15000);
s = getState();
if (s != SI446X_STATE_RX)

1
si4432.h
Unescape View File

@ -182,6 +182,7 @@ extern si446x_info_t SI4463_info;
void Si446x_getInfo(si446x_info_t* info);
void SI4463_init(void);
#define ADF4351_LO 2
#define SI4463_RX 3
#endif

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