DiSlord
5 years ago
parent
7f54b9e3db
commit
7ff0be62ac
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/*-----------------------------------------------------------------------*/
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/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2019 */
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/*-----------------------------------------------------------------------*/
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/* If a working storage control module is available, it should be */
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/* attached to the FatFs via a glue function rather than modifying it. */
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/* This is an example of glue functions to attach various exsisting */
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/* storage control modules to the FatFs module with a defined API. */
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/*-----------------------------------------------------------------------*/
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#include "ff.h" /* Obtains integer types */
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#include "diskio.h" /* Declarations of disk functions */
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/* Definitions of physical drive number for each drive */
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#define DEV_RAM 0 /* Example: Map Ramdisk to physical drive 0 */
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#define DEV_MMC 1 /* Example: Map MMC/SD card to physical drive 1 */
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#define DEV_USB 2 /* Example: Map USB MSD to physical drive 2 */
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/*-----------------------------------------------------------------------*/
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/* Get Drive Status */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_status (
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BYTE pdrv /* Physical drive nmuber to identify the drive */
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)
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{
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DSTATUS stat;
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int result;
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switch (pdrv) {
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case DEV_RAM :
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result = RAM_disk_status();
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// translate the reslut code here
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return stat;
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case DEV_MMC :
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result = MMC_disk_status();
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// translate the reslut code here
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return stat;
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case DEV_USB :
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result = USB_disk_status();
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// translate the reslut code here
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return stat;
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}
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return STA_NOINIT;
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}
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/*-----------------------------------------------------------------------*/
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/* Inidialize a Drive */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_initialize (
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BYTE pdrv /* Physical drive nmuber to identify the drive */
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)
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{
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DSTATUS stat;
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int result;
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switch (pdrv) {
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case DEV_RAM :
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result = RAM_disk_initialize();
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// translate the reslut code here
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return stat;
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case DEV_MMC :
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result = MMC_disk_initialize();
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// translate the reslut code here
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return stat;
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case DEV_USB :
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result = USB_disk_initialize();
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// translate the reslut code here
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return stat;
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}
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return STA_NOINIT;
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}
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/*-----------------------------------------------------------------------*/
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/* Read Sector(s) */
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/*-----------------------------------------------------------------------*/
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DRESULT disk_read (
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BYTE pdrv, /* Physical drive nmuber to identify the drive */
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BYTE *buff, /* Data buffer to store read data */
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LBA_t sector, /* Start sector in LBA */
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UINT count /* Number of sectors to read */
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)
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{
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DRESULT res;
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int result;
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switch (pdrv) {
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case DEV_RAM :
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// translate the arguments here
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result = RAM_disk_read(buff, sector, count);
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// translate the reslut code here
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return res;
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case DEV_MMC :
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// translate the arguments here
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result = MMC_disk_read(buff, sector, count);
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// translate the reslut code here
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return res;
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case DEV_USB :
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// translate the arguments here
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result = USB_disk_read(buff, sector, count);
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// translate the reslut code here
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return res;
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}
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return RES_PARERR;
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}
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/*-----------------------------------------------------------------------*/
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/* Write Sector(s) */
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/*-----------------------------------------------------------------------*/
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#if FF_FS_READONLY == 0
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DRESULT disk_write (
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BYTE pdrv, /* Physical drive nmuber to identify the drive */
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const BYTE *buff, /* Data to be written */
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LBA_t sector, /* Start sector in LBA */
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UINT count /* Number of sectors to write */
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)
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{
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DRESULT res;
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int result;
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switch (pdrv) {
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case DEV_RAM :
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// translate the arguments here
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result = RAM_disk_write(buff, sector, count);
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// translate the reslut code here
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return res;
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case DEV_MMC :
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// translate the arguments here
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result = MMC_disk_write(buff, sector, count);
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// translate the reslut code here
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return res;
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case DEV_USB :
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// translate the arguments here
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result = USB_disk_write(buff, sector, count);
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// translate the reslut code here
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return res;
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}
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return RES_PARERR;
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}
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#endif
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/*-----------------------------------------------------------------------*/
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/* Miscellaneous Functions */
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/*-----------------------------------------------------------------------*/
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DRESULT disk_ioctl (
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BYTE pdrv, /* Physical drive nmuber (0..) */
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BYTE cmd, /* Control code */
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void *buff /* Buffer to send/receive control data */
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)
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{
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DRESULT res;
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int result;
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switch (pdrv) {
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case DEV_RAM :
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// Process of the command for the RAM drive
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return res;
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case DEV_MMC :
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// Process of the command for the MMC/SD card
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return res;
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case DEV_USB :
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// Process of the command the USB drive
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return res;
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}
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return RES_PARERR;
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}
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@ -0,0 +1,77 @@
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/*-----------------------------------------------------------------------/
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/ Low level disk interface modlue include file (C)ChaN, 2019 /
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/-----------------------------------------------------------------------*/
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#ifndef _DISKIO_DEFINED
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#define _DISKIO_DEFINED
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Status of Disk Functions */
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typedef BYTE DSTATUS;
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/* Results of Disk Functions */
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typedef enum {
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RES_OK = 0, /* 0: Successful */
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RES_ERROR, /* 1: R/W Error */
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RES_WRPRT, /* 2: Write Protected */
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RES_NOTRDY, /* 3: Not Ready */
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RES_PARERR /* 4: Invalid Parameter */
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} DRESULT;
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/*---------------------------------------*/
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/* Prototypes for disk control functions */
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DSTATUS disk_initialize (BYTE pdrv);
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DSTATUS disk_status (BYTE pdrv);
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DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
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DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
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DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
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/* Disk Status Bits (DSTATUS) */
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#define STA_NOINIT 0x01 /* Drive not initialized */
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#define STA_NODISK 0x02 /* No medium in the drive */
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#define STA_PROTECT 0x04 /* Write protected */
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/* Command code for disk_ioctrl fucntion */
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/* Generic command (Used by FatFs) */
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#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
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#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
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#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
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#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
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#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
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/* Generic command (Not used by FatFs) */
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#define CTRL_POWER 5 /* Get/Set power status */
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#define CTRL_LOCK 6 /* Lock/Unlock media removal */
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#define CTRL_EJECT 7 /* Eject media */
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#define CTRL_FORMAT 8 /* Create physical format on the media */
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/* MMC/SDC specific ioctl command */
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#define MMC_GET_TYPE 10 /* Get card type */
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#define MMC_GET_CSD 11 /* Get CSD */
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#define MMC_GET_CID 12 /* Get CID */
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#define MMC_GET_OCR 13 /* Get OCR */
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#define MMC_GET_SDSTAT 14 /* Get SD status */
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#define ISDIO_READ 55 /* Read data form SD iSDIO register */
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#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
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#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
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/* ATA/CF specific ioctl command */
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#define ATA_GET_REV 20 /* Get F/W revision */
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#define ATA_GET_MODEL 21 /* Get model name */
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#define ATA_GET_SN 22 /* Get serial number */
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#ifdef __cplusplus
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}
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#endif
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#endif
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,426 @@
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/*----------------------------------------------------------------------------/
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/ FatFs - Generic FAT Filesystem module R0.14 /
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/-----------------------------------------------------------------------------/
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/
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/ Copyright (C) 2019, ChaN, all right reserved.
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/
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/ FatFs module is an open source software. Redistribution and use of FatFs in
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/ source and binary forms, with or without modification, are permitted provided
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/ that the following condition is met:
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/ 1. Redistributions of source code must retain the above copyright notice,
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/ this condition and the following disclaimer.
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/
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/ This software is provided by the copyright holder and contributors "AS IS"
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/ and any warranties related to this software are DISCLAIMED.
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/ The copyright owner or contributors be NOT LIABLE for any damages caused
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/ by use of this software.
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/
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/----------------------------------------------------------------------------*/
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#ifndef FF_DEFINED
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#define FF_DEFINED 86606 /* Revision ID */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "ffconf.h" /* FatFs configuration options */
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#if FF_DEFINED != FFCONF_DEF
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#error Wrong configuration file (ffconf.h).
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#endif
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/* Integer types used for FatFs API */
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#if defined(_WIN32) /* Main development platform */
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#define FF_INTDEF 2
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#include <windows.h>
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typedef unsigned __int64 QWORD;
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#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
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#define FF_INTDEF 2
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#include <stdint.h>
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typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
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typedef unsigned char BYTE; /* char must be 8-bit */
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typedef uint16_t WORD; /* 16-bit unsigned integer */
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typedef uint32_t DWORD; /* 32-bit unsigned integer */
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typedef uint64_t QWORD; /* 64-bit unsigned integer */
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typedef WORD WCHAR; /* UTF-16 character type */
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#else /* Earlier than C99 */
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#define FF_INTDEF 1
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typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
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typedef unsigned char BYTE; /* char must be 8-bit */
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typedef unsigned short WORD; /* 16-bit unsigned integer */
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typedef unsigned long DWORD; /* 32-bit unsigned integer */
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typedef WORD WCHAR; /* UTF-16 character type */
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#endif
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/* Definitions of volume management */
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#if FF_MULTI_PARTITION /* Multiple partition configuration */
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typedef struct {
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BYTE pd; /* Physical drive number */
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BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
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} PARTITION;
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extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
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#endif
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#if FF_STR_VOLUME_ID
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#ifndef FF_VOLUME_STRS
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extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
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#endif
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#endif
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/* Type of path name strings on FatFs API */
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#ifndef _INC_TCHAR
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#define _INC_TCHAR
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#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
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typedef WCHAR TCHAR;
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#define _T(x) L ## x
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#define _TEXT(x) L ## x
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#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
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typedef char TCHAR;
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#define _T(x) u8 ## x
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#define _TEXT(x) u8 ## x
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#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
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typedef DWORD TCHAR;
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#define _T(x) U ## x
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#define _TEXT(x) U ## x
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#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
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#error Wrong FF_LFN_UNICODE setting
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#else /* ANSI/OEM code in SBCS/DBCS */
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typedef char TCHAR;
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#define _T(x) x
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#define _TEXT(x) x
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#endif
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#endif
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/* Type of file size and LBA variables */
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#if FF_FS_EXFAT
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#if FF_INTDEF != 2
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#error exFAT feature wants C99 or later
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#endif
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typedef QWORD FSIZE_t;
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#if FF_LBA64
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typedef QWORD LBA_t;
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#else
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typedef DWORD LBA_t;
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#endif
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#else
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#if FF_LBA64
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#error exFAT needs to be enabled when enable 64-bit LBA
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#endif
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typedef DWORD FSIZE_t;
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typedef DWORD LBA_t;
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#endif
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/* Filesystem object structure (FATFS) */
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typedef struct {
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BYTE fs_type; /* Filesystem type (0:not mounted) */
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BYTE pdrv; /* Associated physical drive */
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BYTE n_fats; /* Number of FATs (1 or 2) */
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BYTE wflag; /* win[] flag (b0:dirty) */
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BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
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WORD id; /* Volume mount ID */
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WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
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WORD csize; /* Cluster size [sectors] */
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#if FF_MAX_SS != FF_MIN_SS
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WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
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#endif
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#if FF_USE_LFN
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WCHAR* lfnbuf; /* LFN working buffer */
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#endif
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#if FF_FS_EXFAT
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BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
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#endif
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#if FF_FS_REENTRANT
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FF_SYNC_t sobj; /* Identifier of sync object */
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#endif
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#if !FF_FS_READONLY
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DWORD last_clst; /* Last allocated cluster */
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DWORD free_clst; /* Number of free clusters */
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#endif
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#if FF_FS_RPATH
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DWORD cdir; /* Current directory start cluster (0:root) */
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#if FF_FS_EXFAT
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DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
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DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
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DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
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#endif
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#endif
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DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
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DWORD fsize; /* Size of an FAT [sectors] */
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LBA_t volbase; /* Volume base sector */
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LBA_t fatbase; /* FAT base sector */
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LBA_t dirbase; /* Root directory base sector/cluster */
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LBA_t database; /* Data base sector */
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#if FF_FS_EXFAT
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LBA_t bitbase; /* Allocation bitmap base sector */
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#endif
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LBA_t winsect; /* Current sector appearing in the win[] */
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BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
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} FATFS;
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/* Object ID and allocation information (FFOBJID) */
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typedef struct {
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FATFS* fs; /* Pointer to the hosting volume of this object */
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WORD id; /* Hosting volume mount ID */
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BYTE attr; /* Object attribute */
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BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
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DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
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FSIZE_t objsize; /* Object size (valid when sclust != 0) */
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#if FF_FS_EXFAT
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DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
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DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
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DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
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DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
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DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
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#endif
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#if FF_FS_LOCK
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UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
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#endif
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} FFOBJID;
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/* File object structure (FIL) */
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typedef struct {
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FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
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BYTE flag; /* File status flags */
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BYTE err; /* Abort flag (error code) */
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FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
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DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
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LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
|
||||
#if !FF_FS_READONLY
|
||||
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
|
||||
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
|
||||
#endif
|
||||
#if FF_USE_FASTSEEK
|
||||
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
|
||||
#endif
|
||||
#if !FF_FS_TINY
|
||||
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier */
|
||||
DWORD dptr; /* Current read/write offset */
|
||||
DWORD clust; /* Current cluster */
|
||||
LBA_t sect; /* Current sector (0:Read operation has terminated) */
|
||||
BYTE* dir; /* Pointer to the directory item in the win[] */
|
||||
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
|
||||
#if FF_USE_LFN
|
||||
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
|
||||
#endif
|
||||
#if FF_USE_FIND
|
||||
const TCHAR* pat; /* Pointer to the name matching pattern */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File information structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
FSIZE_t fsize; /* File size */
|
||||
WORD fdate; /* Modified date */
|
||||
WORD ftime; /* Modified time */
|
||||
BYTE fattrib; /* File attribute */
|
||||
#if FF_USE_LFN
|
||||
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
|
||||
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
|
||||
#else
|
||||
TCHAR fname[12 + 1]; /* File name */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* Format parameter structure (MKFS_PARM) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
|
||||
BYTE n_fat; /* Number of FATs */
|
||||
UINT align; /* Data area alignment (sector) */
|
||||
UINT n_root; /* Number of root directory entries */
|
||||
DWORD au_size; /* Cluster size (byte) */
|
||||
} MKFS_PARM;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
|
||||
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
|
||||
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
|
||||
FRESULT f_truncate (FIL* fp); /* Truncate the file */
|
||||
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
|
||||
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
|
||||
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
|
||||
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
|
||||
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
|
||||
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
|
||||
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
|
||||
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
|
||||
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
|
||||
FRESULT f_setcp (WORD cp); /* Set current code page */
|
||||
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
|
||||
#define f_error(fp) ((fp)->err)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->obj.objsize)
|
||||
#define f_rewind(fp) f_lseek((fp), 0)
|
||||
#define f_rewinddir(dp) f_readdir((dp), 0)
|
||||
#define f_rmdir(path) f_unlink(path)
|
||||
#define f_unmount(path) f_mount(0, path, 0)
|
||||
|
||||
#ifndef EOF
|
||||
#define EOF (-1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !FF_FS_READONLY && !FF_FS_NORTC
|
||||
DWORD get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* LFN support functions */
|
||||
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
|
||||
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
|
||||
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
|
||||
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
|
||||
#endif
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||
void ff_memfree (void* mblock); /* Free memory block */
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if FF_FS_REENTRANT
|
||||
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
|
||||
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
|
||||
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
|
||||
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access mode and open method flags (3rd argument of f_open) */
|
||||
#define FA_READ 0x01
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA_OPEN_APPEND 0x30
|
||||
|
||||
/* Fast seek controls (2nd argument of f_lseek) */
|
||||
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
|
||||
|
||||
/* Format options (2nd argument of f_mkfs) */
|
||||
#define FM_FAT 0x01
|
||||
#define FM_FAT32 0x02
|
||||
#define FM_EXFAT 0x04
|
||||
#define FM_ANY 0x07
|
||||
#define FM_SFD 0x08
|
||||
|
||||
/* Filesystem type (FATFS.fs_type) */
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
#define FS_EXFAT 4
|
||||
|
||||
/* File attribute bits for directory entry (FILINFO.fattrib) */
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FF_DEFINED */
|
||||
@ -0,0 +1,319 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs Functional Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FFCONF_DEF 86606 /* Revision ID */
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Function Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
#define FF_FS_READONLY 0
|
||||
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
|
||||
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
|
||||
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
|
||||
/ and optional writing functions as well. */
|
||||
|
||||
|
||||
#define FF_FS_MINIMIZE 0
|
||||
/* This option defines minimization level to remove some basic API functions.
|
||||
/
|
||||
/ 0: Basic functions are fully enabled.
|
||||
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
|
||||
/ are removed.
|
||||
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||
/ 3: f_lseek() function is removed in addition to 2. */
|
||||
|
||||
|
||||
#define FF_USE_STRFUNC 0
|
||||
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
|
||||
/
|
||||
/ 0: Disable string functions.
|
||||
/ 1: Enable without LF-CRLF conversion.
|
||||
/ 2: Enable with LF-CRLF conversion. */
|
||||
|
||||
|
||||
#define FF_USE_FIND 0
|
||||
/* This option switches filtered directory read functions, f_findfirst() and
|
||||
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
|
||||
|
||||
|
||||
#define FF_USE_MKFS 0
|
||||
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FASTSEEK 0
|
||||
/* This option switches fast seek function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_EXPAND 0
|
||||
/* This option switches f_expand function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_CHMOD 0
|
||||
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
|
||||
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
|
||||
|
||||
|
||||
#define FF_USE_LABEL 0
|
||||
/* This option switches volume label functions, f_getlabel() and f_setlabel().
|
||||
/ (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FORWARD 0
|
||||
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_CODE_PAGE 866
|
||||
/* This option specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect code page setting can cause a file open failure.
|
||||
/
|
||||
/ 437 - U.S.
|
||||
/ 720 - Arabic
|
||||
/ 737 - Greek
|
||||
/ 771 - KBL
|
||||
/ 775 - Baltic
|
||||
/ 850 - Latin 1
|
||||
/ 852 - Latin 2
|
||||
/ 855 - Cyrillic
|
||||
/ 857 - Turkish
|
||||
/ 860 - Portuguese
|
||||
/ 861 - Icelandic
|
||||
/ 862 - Hebrew
|
||||
/ 863 - Canadian French
|
||||
/ 864 - Arabic
|
||||
/ 865 - Nordic
|
||||
/ 866 - Russian
|
||||
/ 869 - Greek 2
|
||||
/ 932 - Japanese (DBCS)
|
||||
/ 936 - Simplified Chinese (DBCS)
|
||||
/ 949 - Korean (DBCS)
|
||||
/ 950 - Traditional Chinese (DBCS)
|
||||
/ 0 - Include all code pages above and configured by f_setcp()
|
||||
*/
|
||||
|
||||
|
||||
#define FF_USE_LFN 1
|
||||
#define FF_MAX_LFN 32
|
||||
/* The FF_USE_LFN switches the support for LFN (long file name).
|
||||
/
|
||||
/ 0: Disable LFN. FF_MAX_LFN has no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
|
||||
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
|
||||
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
|
||||
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
|
||||
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
|
||||
/ specification.
|
||||
/ When use stack for the working buffer, take care on stack overflow. When use heap
|
||||
/ memory for the working buffer, memory management functions, ff_memalloc() and
|
||||
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
|
||||
|
||||
|
||||
#define FF_LFN_UNICODE 0
|
||||
/* This option switches the character encoding on the API when LFN is enabled.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP (TCHAR = char)
|
||||
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
|
||||
/ 2: Unicode in UTF-8 (TCHAR = char)
|
||||
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
|
||||
/
|
||||
/ Also behavior of string I/O functions will be affected by this option.
|
||||
/ When LFN is not enabled, this option has no effect. */
|
||||
|
||||
|
||||
#define FF_LFN_BUF 32
|
||||
#define FF_SFN_BUF 12
|
||||
/* This set of options defines size of file name members in the FILINFO structure
|
||||
/ which is used to read out directory items. These values should be suffcient for
|
||||
/ the file names to read. The maximum possible length of the read file name depends
|
||||
/ on character encoding. When LFN is not enabled, these options have no effect. */
|
||||
|
||||
|
||||
#define FF_STRF_ENCODE 0
|
||||
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
|
||||
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
|
||||
/ This option selects assumption of character encoding ON THE FILE to be
|
||||
/ read/written via those functions.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP
|
||||
/ 1: Unicode in UTF-16LE
|
||||
/ 2: Unicode in UTF-16BE
|
||||
/ 3: Unicode in UTF-8
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_RPATH 0
|
||||
/* This option configures support for relative path.
|
||||
/
|
||||
/ 0: Disable relative path and remove related functions.
|
||||
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
|
||||
/ 2: f_getcwd() function is available in addition to 1.
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Drive/Volume Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. (1-10) */
|
||||
|
||||
|
||||
#define FF_STR_VOLUME_ID 0
|
||||
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
|
||||
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
|
||||
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
|
||||
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
|
||||
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
|
||||
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
|
||||
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
|
||||
/ not defined, a user defined volume string table needs to be defined as:
|
||||
/
|
||||
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
|
||||
*/
|
||||
|
||||
|
||||
#define FF_MULTI_PARTITION 0
|
||||
/* This option switches support for multiple volumes on the physical drive.
|
||||
/ By default (0), each logical drive number is bound to the same physical drive
|
||||
/ number and only an FAT volume found on the physical drive will be mounted.
|
||||
/ When this function is enabled (1), each logical drive number can be bound to
|
||||
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
|
||||
/ funciton will be available. */
|
||||
|
||||
|
||||
#define FF_MIN_SS 512
|
||||
#define FF_MAX_SS 512
|
||||
/* This set of options configures the range of sector size to be supported. (512,
|
||||
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
|
||||
/ harddisk. But a larger value may be required for on-board flash memory and some
|
||||
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
|
||||
/ for variable sector size mode and disk_ioctl() function needs to implement
|
||||
/ GET_SECTOR_SIZE command. */
|
||||
|
||||
|
||||
#define FF_LBA64 0
|
||||
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
|
||||
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
|
||||
|
||||
|
||||
#define FF_MIN_GPT 0x100000000
|
||||
/* Minimum number of sectors to switch GPT format to create partition in f_mkfs and
|
||||
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
|
||||
|
||||
|
||||
#define FF_USE_TRIM 0
|
||||
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
|
||||
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
|
||||
/ disk_ioctl() function. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_TINY 0
|
||||
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
|
||||
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
|
||||
/ Instead of private sector buffer eliminated from the file object, common sector
|
||||
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
|
||||
|
||||
|
||||
#define FF_FS_EXFAT 1
|
||||
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
|
||||
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
|
||||
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
|
||||
|
||||
|
||||
#define FF_FS_NORTC 0
|
||||
#define FF_NORTC_MON 1
|
||||
#define FF_NORTC_MDAY 1
|
||||
#define FF_NORTC_YEAR 2019
|
||||
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
|
||||
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
|
||||
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
|
||||
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
|
||||
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
|
||||
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
|
||||
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
|
||||
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
|
||||
|
||||
|
||||
#define FF_FS_NOFSINFO 0
|
||||
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
|
||||
/ option, and f_getfree() function at first time after volume mount will force
|
||||
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
|
||||
/
|
||||
/ bit0=0: Use free cluster count in the FSINFO if available.
|
||||
/ bit0=1: Do not trust free cluster count in the FSINFO.
|
||||
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
|
||||
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_LOCK 0
|
||||
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
|
||||
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
|
||||
/ is 1.
|
||||
/
|
||||
/ 0: Disable file lock function. To avoid volume corruption, application program
|
||||
/ should avoid illegal open, remove and rename to the open objects.
|
||||
/ >0: Enable file lock function. The value defines how many files/sub-directories
|
||||
/ can be opened simultaneously under file lock control. Note that the file
|
||||
/ lock control is independent of re-entrancy. */
|
||||
|
||||
|
||||
/* #include <somertos.h> // O/S definitions */
|
||||
#define FF_FS_REENTRANT 0
|
||||
#define FF_FS_TIMEOUT 1000
|
||||
#define FF_SYNC_t HANDLE
|
||||
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
|
||||
/ module itself. Note that regardless of this option, file access to different
|
||||
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
|
||||
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
|
||||
/ to the same volume is under control of this function.
|
||||
/
|
||||
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
|
||||
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
|
||||
/ function, must be added to the project. Samples are available in
|
||||
/ option/syscall.c.
|
||||
/
|
||||
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
|
||||
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
|
||||
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
|
||||
/ included somewhere in the scope of ff.h. */
|
||||
|
||||
|
||||
#define _WORD_ACCESS 1 /* 0 or 1 */
|
||||
/* The _WORD_ACCESS option is an only platform dependent option. It defines
|
||||
/ which access method is used to the word data on the FAT volume.
|
||||
/
|
||||
/ 0: Byte-by-byte access. Always compatible with all platforms.
|
||||
/ 1: Word access. Do not choose this unless under both the following conditions.
|
||||
/
|
||||
/ * Address misaligned memory access is always allowed for ALL instructions.
|
||||
/ * Byte order on the memory is little-endian.
|
||||
/
|
||||
/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and
|
||||
/ reduce code size. Following table shows an example of some processor types.
|
||||
/
|
||||
/ ARM7TDMI 0 ColdFire 0 V850E2 0
|
||||
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
|
||||
/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
|
||||
/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
|
||||
/ AVR32 0 RL78 0 R32C 0
|
||||
/ PIC18 0/1 SH-2 0 M16C 0/1
|
||||
/ PIC24 0 H8S 0 MSP430 0
|
||||
/ PIC32 0 H8/300H 0 x86 0/1
|
||||
*/
|
||||
|
||||
/*--- End of configuration options ---*/
|
||||
@ -0,0 +1,170 @@
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Sample Code of OS Dependent Functions for FatFs */
|
||||
/* (C)ChaN, 2018 */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ff.h"
|
||||
|
||||
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Allocate a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */
|
||||
UINT msize /* Number of bytes to allocate */
|
||||
)
|
||||
{
|
||||
return malloc(msize); /* Allocate a new memory block with POSIX API */
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Free a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void ff_memfree (
|
||||
void* mblock /* Pointer to the memory block to free (nothing to do if null) */
|
||||
)
|
||||
{
|
||||
free(mblock); /* Free the memory block with POSIX API */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if FF_FS_REENTRANT /* Mutal exclusion */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Create a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to create a new
|
||||
/ synchronization object for the volume, such as semaphore and mutex.
|
||||
/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
//const osMutexDef_t Mutex[FF_VOLUMES]; /* Table of CMSIS-RTOS mutex */
|
||||
|
||||
|
||||
int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
|
||||
BYTE vol, /* Corresponding volume (logical drive number) */
|
||||
FF_SYNC_t* sobj /* Pointer to return the created sync object */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
*sobj = CreateMutex(NULL, FALSE, NULL);
|
||||
return (int)(*sobj != INVALID_HANDLE_VALUE);
|
||||
|
||||
/* uITRON */
|
||||
// T_CSEM csem = {TA_TPRI,1,1};
|
||||
// *sobj = acre_sem(&csem);
|
||||
// return (int)(*sobj > 0);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// *sobj = OSMutexCreate(0, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// *sobj = xSemaphoreCreateMutex();
|
||||
// return (int)(*sobj != NULL);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// *sobj = osMutexCreate(&Mutex[vol]);
|
||||
// return (int)(*sobj != NULL);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Delete a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to delete a synchronization
|
||||
/ object that created with ff_cre_syncobj() function. When a 0 is returned,
|
||||
/ the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
|
||||
FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)CloseHandle(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(del_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// vSemaphoreDelete(sobj);
|
||||
// return 1;
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexDelete(sobj) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Request Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on entering file functions to lock the volume.
|
||||
/ When a 0 is returned, the file function fails with FR_TIMEOUT.
|
||||
*/
|
||||
|
||||
int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
|
||||
FF_SYNC_t sobj /* Sync object to wait */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(wai_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Release Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on leaving file functions to unlock the volume.
|
||||
*/
|
||||
|
||||
void ff_rel_grant (
|
||||
FF_SYNC_t sobj /* Sync object to be signaled */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
ReleaseMutex(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// sig_sem(sobj);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OSMutexPost(sobj);
|
||||
|
||||
/* FreeRTOS */
|
||||
// xSemaphoreGive(sobj);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// osMutexRelease(sobj);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,38 @@
|
||||
/*-------------------------------------------*/
|
||||
/* Integer type definitions for FatFs module */
|
||||
/*-------------------------------------------*/
|
||||
|
||||
#ifndef FF_INTEGER
|
||||
#define FF_INTEGER
|
||||
|
||||
#ifdef _WIN32 /* FatFs development platform */
|
||||
|
||||
#include <windows.h>
|
||||
#include <tchar.h>
|
||||
typedef unsigned __int64 QWORD;
|
||||
|
||||
|
||||
#else /* Embedded platform */
|
||||
|
||||
/* These types MUST be 16-bit or 32-bit */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* This type MUST be 8-bit */
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types MUST be 16-bit */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types MUST be 32-bit */
|
||||
typedef long LONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
|
||||
typedef unsigned long long QWORD;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,129 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
// extern void si5351_setup(void);
|
||||
|
||||
/*
|
||||
* Early initialization code.
|
||||
* This initialization must be performed just after stack setup and before
|
||||
* any other initialization.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
// Refer to thess pages for how to start dfu from software
|
||||
// https://community.st.com/s/question/0D50X00009XkeeWSAR/stm32l476rg-jump-to-bootloader-from-software
|
||||
// https://stm32f4-discovery.net/2017/04/tutorial-jump-system-memory-software-stm32/
|
||||
if ( *((unsigned long *)BOOT_FROM_SYTEM_MEMORY_MAGIC_ADDRESS) == BOOT_FROM_SYTEM_MEMORY_MAGIC ) {
|
||||
// require irq
|
||||
// __enable_irq();
|
||||
// reset magic bytes
|
||||
*((unsigned long *)BOOT_FROM_SYTEM_MEMORY_MAGIC_ADDRESS) = 0;
|
||||
#if 1
|
||||
// https://stm32f4-discovery.net/2017/04/tutorial-jump-system-memory-software-stm32/
|
||||
// Step: Disable systick timer and reset it to default values
|
||||
#if 0
|
||||
SysTick->CTRL = 0;
|
||||
SysTick->LOAD = 0;
|
||||
SysTick->VAL = 0;
|
||||
#endif
|
||||
// Step: Disable all interrupts
|
||||
__disable_irq();
|
||||
// Remap system memory to address 0x0000 0000 in address space
|
||||
typedef void (*pFunction)(void);
|
||||
pFunction bootloader;
|
||||
uint32_t msp;
|
||||
uint32_t foo = SYSCFG->CFGR1;
|
||||
foo = (foo & ~SYSCFG_CFGR1_MEM_MODE) || SYSCFG_CFGR1_MEM_MODE_0;
|
||||
SYSCFG->CFGR1 = foo;
|
||||
//foo = SYSCFG->CFGR1;
|
||||
__DSB();
|
||||
__ISB();
|
||||
//__DSB();
|
||||
//__ISB();
|
||||
#if 1
|
||||
bootloader = (void (*)(void)) (*((uint32_t *)(STM32F303xC_SYSTEM_MEMORY+4)));
|
||||
//msp = *(uint32_t *) STM32F303xC_SYSTEM_MEMORY;
|
||||
msp = 0x20002250;
|
||||
#else
|
||||
bootloader = (void (*)(void)) (*((uint32_t *)(4)));
|
||||
//msp = *(uint32_t *) 0;
|
||||
msp = 0x20002250;
|
||||
#endif
|
||||
__set_MSP(msp);
|
||||
bootloader();
|
||||
while(1);
|
||||
#else
|
||||
__set_MSP(SYSTEM_BOOT_MSP);
|
||||
( (void (*)(void)) (*((uint32_t *)(STM32F303xC_SYSTEM_MEMORY+4))) )();
|
||||
while(1);
|
||||
#endif
|
||||
}
|
||||
// si5351_setup();
|
||||
stm32_clock_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* Board-specific initialization code.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
}
|
||||
@ -0,0 +1,788 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* Setup for the Strawberry Linux STbee
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_NANOVNA_STM32_F303
|
||||
#define BOARD_NAME "tinySA-H4"
|
||||
|
||||
/*
|
||||
* Board frequencies.
|
||||
*/
|
||||
#define STM32_LSECLK 32768
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
//#define STM32_HSE_BYPASS
|
||||
|
||||
/*
|
||||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
|
||||
*/
|
||||
#define STM32F303xC
|
||||
|
||||
//#define STM32_HSE_BYPASS
|
||||
|
||||
#define STM32F303xC_SYSTEM_MEMORY 0x1FFFD800
|
||||
#define BOOT_FROM_SYTEM_MEMORY_MAGIC_ADDRESS 0x20009FF0
|
||||
#define BOOT_FROM_SYTEM_MEMORY_MAGIC 0xDEADBEEF
|
||||
//#define SYSTEM_BOOT_MSP *(uint32_t *)0 // 0x20001258
|
||||
#define SYSTEM_BOOT_MSP 0x20001258
|
||||
|
||||
/*
|
||||
* IO pins assignments
|
||||
*/
|
||||
|
||||
/* on-board */
|
||||
|
||||
//#define GPIOA_BUTTON 0
|
||||
#define GPIOA_LEVER1 1
|
||||
#define GPIOA_LEVER2 2
|
||||
#define GPIOA_PUSH 3
|
||||
//#define GPIOA_VBUS 4
|
||||
#define GPIOA_DAC2 5
|
||||
#define GPIOA_XP 6
|
||||
#define GPIOA_YP 7
|
||||
//#define GPIOA_MCO 8
|
||||
#define GPIOA_PE_SEL 9
|
||||
#define GPIOA_RF_PWR 10
|
||||
#define GPIOA_USB_DM 11
|
||||
#define GPIOA_USB_DP 12
|
||||
#define GPIOA_JTMS 13
|
||||
#define GPIOA_JTCK 14
|
||||
#define GPIOA_LCD_RESET 15
|
||||
|
||||
#define GPIOB_XN 0
|
||||
#define GPIOB_YN 1
|
||||
#define GPIOB_RX_SEL 2
|
||||
#define GPIOB_SPI_SCLK 3
|
||||
#define GPIOB_SPI_MISO 4
|
||||
#define GPIOB_SPI_MOSI 5
|
||||
#define GPIOB_LCD_CS 6
|
||||
#define GPIOB_LCD_CD 7
|
||||
#define GPIOB_I2C1_SCL 8
|
||||
#define GPIOB_I2C1_SDA 9
|
||||
#define GPIOB_LO_SEL 10
|
||||
#define GPIOB_SD_CS 11
|
||||
#define GPIOB_I2S2_WCLK 12
|
||||
#define GPIOB_I2S2_BCLK 13
|
||||
#define GPIOB_I2S2_MISO 14
|
||||
#define GPIOB_I2S2_MOSI 15
|
||||
|
||||
#define GPIOC_LED 13
|
||||
|
||||
#define GPIOF_OSC_IN 0
|
||||
#define GPIOF_OSC_OUT 1
|
||||
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_2M(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_25M(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_50M(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_100M(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v##U) << (((n) % 8U) * 4U))
|
||||
|
||||
/*
|
||||
* GPIOA setup:
|
||||
*
|
||||
* PA8 - MCO (alternate 0).
|
||||
* PA11 - USB_DM (alternate 14).
|
||||
* PA12 - USB_DP (alternate 14).
|
||||
* PA13 - SWDIO (alternate 0).
|
||||
* PA14 - SWCLK (alternate 0).
|
||||
*/
|
||||
#define VAL_GPIOA_MODER (PIN_MODE_INPUT(0U) | \
|
||||
PIN_MODE_INPUT(1U) | \
|
||||
PIN_MODE_INPUT(2U) | \
|
||||
PIN_MODE_INPUT(3U) | \
|
||||
PIN_MODE_INPUT(4U) | \
|
||||
PIN_MODE_ANALOG(GPIOA_DAC2) | \
|
||||
PIN_MODE_ANALOG(GPIOA_XP) | \
|
||||
PIN_MODE_ANALOG(GPIOA_YP) | \
|
||||
PIN_MODE_ALTERNATE(8U) | \
|
||||
PIN_MODE_OUTPUT(GPIOA_PE_SEL) | \
|
||||
PIN_MODE_OUTPUT(GPIOA_RF_PWR) | \
|
||||
PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
|
||||
PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
|
||||
PIN_MODE_ALTERNATE(GPIOA_JTMS) | \
|
||||
PIN_MODE_ALTERNATE(GPIOA_JTCK) | \
|
||||
PIN_MODE_OUTPUT(GPIOA_LCD_RESET))
|
||||
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0U) | \
|
||||
PIN_OTYPE_PUSHPULL(1U) | \
|
||||
PIN_OTYPE_PUSHPULL(2U) | \
|
||||
PIN_OTYPE_PUSHPULL(3U) | \
|
||||
PIN_OTYPE_PUSHPULL(4U) | \
|
||||
PIN_OTYPE_PUSHPULL(5U) | \
|
||||
PIN_OTYPE_PUSHPULL(6U) | \
|
||||
PIN_OTYPE_PUSHPULL(7U) | \
|
||||
PIN_OTYPE_PUSHPULL(8U) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_PE_SEL) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_RF_PWR) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOA_LCD_RESET))
|
||||
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(0) | \
|
||||
PIN_OSPEED_2M(1) | \
|
||||
PIN_OSPEED_2M(2) | \
|
||||
PIN_OSPEED_2M(3) | \
|
||||
PIN_OSPEED_2M(4) | \
|
||||
PIN_OSPEED_2M(5) | \
|
||||
PIN_OSPEED_2M(6) | \
|
||||
PIN_OSPEED_2M(7) | \
|
||||
PIN_OSPEED_100M(8U) | \
|
||||
PIN_OSPEED_100M(GPIOA_PE_SEL) | \
|
||||
PIN_OSPEED_100M(GPIOA_RF_PWR) | \
|
||||
PIN_OSPEED_100M(GPIOA_USB_DM) | \
|
||||
PIN_OSPEED_100M(GPIOA_USB_DP) | \
|
||||
PIN_OSPEED_100M(GPIOA_JTMS) | \
|
||||
PIN_OSPEED_100M(GPIOA_JTCK) | \
|
||||
PIN_OSPEED_100M(GPIOA_LCD_RESET))
|
||||
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \
|
||||
PIN_PUPDR_PULLDOWN(1) | \
|
||||
PIN_PUPDR_PULLDOWN(2) | \
|
||||
PIN_PUPDR_PULLDOWN(3) | \
|
||||
PIN_PUPDR_PULLUP(4) | \
|
||||
PIN_PUPDR_FLOATING(5) | \
|
||||
PIN_PUPDR_FLOATING(6) | \
|
||||
PIN_PUPDR_FLOATING(7) | \
|
||||
PIN_PUPDR_PULLUP(8U) | \
|
||||
PIN_PUPDR_PULLUP(GPIOA_PE_SEL) | \
|
||||
PIN_PUPDR_PULLUP(GPIOA_RF_PWR) | \
|
||||
PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
|
||||
PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
|
||||
PIN_PUPDR_PULLDOWN(GPIOA_JTMS) | \
|
||||
PIN_PUPDR_PULLDOWN(GPIOA_JTCK) | \
|
||||
PIN_PUPDR_PULLDOWN(GPIOA_LCD_RESET))
|
||||
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(2) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_LOW(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(8U) | \
|
||||
PIN_ODR_HIGH(GPIOA_PE_SEL) | \
|
||||
PIN_ODR_HIGH(GPIOA_RF_PWR) | \
|
||||
PIN_ODR_HIGH(GPIOA_USB_DM) | \
|
||||
PIN_ODR_HIGH(GPIOA_USB_DP) | \
|
||||
PIN_ODR_HIGH(GPIOA_JTMS) | \
|
||||
PIN_ODR_HIGH(GPIOA_JTCK) | \
|
||||
PIN_ODR_HIGH(GPIOA_LCD_RESET))
|
||||
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(2, 0) | \
|
||||
PIN_AFIO_AF(3, 0) | \
|
||||
PIN_AFIO_AF(4, 0) | \
|
||||
PIN_AFIO_AF(5, 0) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8U, 0) | \
|
||||
PIN_AFIO_AF(GPIOA_PE_SEL, 0) | \
|
||||
PIN_AFIO_AF(GPIOA_RF_PWR, 0) | \
|
||||
PIN_AFIO_AF(GPIOA_USB_DM, 14) | \
|
||||
PIN_AFIO_AF(GPIOA_USB_DP, 14) | \
|
||||
PIN_AFIO_AF(GPIOA_JTMS, 0) | \
|
||||
PIN_AFIO_AF(GPIOA_JTCK, 0) | \
|
||||
PIN_AFIO_AF(GPIOA_LCD_RESET, 0))
|
||||
|
||||
/*
|
||||
* GPIOB setup:
|
||||
*
|
||||
* PB0 - XN analog
|
||||
* PB1 - YN analog
|
||||
* PB3 - SPI1_SCLK (alternate 5).
|
||||
* PB4 - SPI1_MISO (alternate 5).
|
||||
* PB5 - SPI1_MOSI (alternate 5).
|
||||
* PB8 - I2C1_SCL (alternate 4).
|
||||
* PB9 - I2C1_SDA (alternate 4).
|
||||
* PB12 - I2S2_WCLK (alternate 5).
|
||||
* PB13 - I2S2_BCLK (alternate 5).
|
||||
* PB15 - I2S2_MOSI (alternate 5).
|
||||
*/
|
||||
#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_XN) | \
|
||||
PIN_MODE_ANALOG(GPIOB_YN) | \
|
||||
PIN_MODE_OUTPUT(GPIOB_RX_SEL) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_SPI_SCLK) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_SPI_MISO) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_SPI_MOSI) | \
|
||||
PIN_MODE_OUTPUT(6) | \
|
||||
PIN_MODE_OUTPUT(7) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
|
||||
PIN_MODE_OUTPUT(GPIOB_LO_SEL) | \
|
||||
PIN_MODE_OUTPUT(11) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_I2S2_WCLK) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_I2S2_BCLK) | \
|
||||
PIN_MODE_ALTERNATE(14) | \
|
||||
PIN_MODE_ALTERNATE(GPIOB_I2S2_MOSI))
|
||||
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
|
||||
PIN_OTYPE_PUSHPULL(1) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_RX_SEL) | \
|
||||
PIN_OTYPE_PUSHPULL(3) | \
|
||||
PIN_OTYPE_PUSHPULL(4) | \
|
||||
PIN_OTYPE_PUSHPULL(5) | \
|
||||
PIN_OTYPE_PUSHPULL(6) | \
|
||||
PIN_OTYPE_PUSHPULL(7) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_LO_SEL) | \
|
||||
PIN_OTYPE_PUSHPULL(11) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_WCLK) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_BCLK) | \
|
||||
PIN_OTYPE_PUSHPULL(14) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_MOSI))
|
||||
#define VAL_GPIOB_OSPEEDR (PIN_PUPDR_FLOATING(GPIOB_XN) | \
|
||||
PIN_PUPDR_FLOATING(GPIOB_YN) | \
|
||||
PIN_OSPEED_100M(GPIOB_RX_SEL) | \
|
||||
PIN_OSPEED_100M(3) | \
|
||||
PIN_OSPEED_100M(4) | \
|
||||
PIN_OSPEED_100M(5) | \
|
||||
PIN_OSPEED_100M(6) | \
|
||||
PIN_OSPEED_100M(7) | \
|
||||
PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
|
||||
PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
|
||||
PIN_OSPEED_100M(GPIOB_LO_SEL) | \
|
||||
PIN_OSPEED_100M(11) | \
|
||||
PIN_OSPEED_100M(GPIOB_I2S2_WCLK) | \
|
||||
PIN_OSPEED_100M(GPIOB_I2S2_BCLK) | \
|
||||
PIN_OSPEED_100M(14) | \
|
||||
PIN_OSPEED_100M(GPIOB_I2S2_MOSI))
|
||||
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(0) | \
|
||||
PIN_PUPDR_PULLUP(1) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_RX_SEL) | \
|
||||
PIN_PUPDR_PULLUP(3) | \
|
||||
PIN_PUPDR_PULLUP(4) | \
|
||||
PIN_PUPDR_PULLUP(5) | \
|
||||
PIN_PUPDR_PULLUP(6) | \
|
||||
PIN_PUPDR_PULLUP(7) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_LO_SEL) | \
|
||||
PIN_PUPDR_PULLUP(11) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_I2S2_WCLK) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_I2S2_BCLK) | \
|
||||
PIN_PUPDR_PULLUP(14) | \
|
||||
PIN_PUPDR_PULLUP(GPIOB_I2S2_MOSI))
|
||||
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(GPIOB_RX_SEL) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_HIGH(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
|
||||
PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
|
||||
PIN_ODR_HIGH(GPIOB_LO_SEL) | \
|
||||
PIN_ODR_HIGH(11) | \
|
||||
PIN_ODR_HIGH(GPIOB_I2S2_WCLK) | \
|
||||
PIN_ODR_HIGH(GPIOB_I2S2_BCLK) | \
|
||||
PIN_ODR_HIGH(14) | \
|
||||
PIN_ODR_HIGH(GPIOB_I2S2_MOSI))
|
||||
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(GPIOB_RX_SEL, 0) | \
|
||||
PIN_AFIO_AF(GPIOB_SPI_SCLK, 5) | \
|
||||
PIN_AFIO_AF(GPIOB_SPI_MOSI, 5) | \
|
||||
PIN_AFIO_AF(GPIOB_SPI_MISO, 5) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
|
||||
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
|
||||
PIN_AFIO_AF(GPIOB_LO_SEL, 0) | \
|
||||
PIN_AFIO_AF(11, 0) | \
|
||||
PIN_AFIO_AF(GPIOB_I2S2_WCLK, 5) | \
|
||||
PIN_AFIO_AF(GPIOB_I2S2_BCLK, 5) | \
|
||||
PIN_AFIO_AF(14, 0) | \
|
||||
PIN_AFIO_AF(GPIOB_I2S2_MOSI, 5))
|
||||
/*
|
||||
* GPIOC setup:
|
||||
*
|
||||
* PC13 - LED (output pushpull maximum).
|
||||
* PC14 - USB DISC (output pushpull maximum).
|
||||
*/
|
||||
#define GPIOC_LED 13
|
||||
|
||||
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \
|
||||
PIN_MODE_INPUT(1) | \
|
||||
PIN_MODE_INPUT(2) | \
|
||||
PIN_MODE_INPUT(3) | \
|
||||
PIN_MODE_INPUT(4) | \
|
||||
PIN_MODE_INPUT(5) | \
|
||||
PIN_MODE_INPUT(6) | \
|
||||
PIN_MODE_INPUT(7) | \
|
||||
PIN_MODE_INPUT(8) | \
|
||||
PIN_MODE_INPUT(9) | \
|
||||
PIN_MODE_INPUT(10) | \
|
||||
PIN_MODE_INPUT(11) | \
|
||||
PIN_MODE_INPUT(12) | \
|
||||
PIN_MODE_OUTPUT(GPIOC_LED) | \
|
||||
PIN_MODE_INPUT(14) | \
|
||||
PIN_MODE_INPUT(15))
|
||||
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
|
||||
PIN_OTYPE_PUSHPULL(1) | \
|
||||
PIN_OTYPE_PUSHPULL(2) | \
|
||||
PIN_OTYPE_PUSHPULL(3) | \
|
||||
PIN_OTYPE_PUSHPULL(4) | \
|
||||
PIN_OTYPE_PUSHPULL(5) | \
|
||||
PIN_OTYPE_PUSHPULL(6) | \
|
||||
PIN_OTYPE_PUSHPULL(7) | \
|
||||
PIN_OTYPE_PUSHPULL(8) | \
|
||||
PIN_OTYPE_PUSHPULL(9) | \
|
||||
PIN_OTYPE_PUSHPULL(10) | \
|
||||
PIN_OTYPE_PUSHPULL(11) | \
|
||||
PIN_OTYPE_PUSHPULL(12) | \
|
||||
PIN_OTYPE_PUSHPULL(GPIOC_LED) | \
|
||||
PIN_OTYPE_PUSHPULL(14) | \
|
||||
PIN_OTYPE_PUSHPULL(15))
|
||||
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) | \
|
||||
PIN_OSPEED_100M(1) | \
|
||||
PIN_OSPEED_100M(2) | \
|
||||
PIN_OSPEED_100M(3) | \
|
||||
PIN_OSPEED_100M(4) | \
|
||||
PIN_OSPEED_100M(5) | \
|
||||
PIN_OSPEED_100M(6) | \
|
||||
PIN_OSPEED_100M(7) | \
|
||||
PIN_OSPEED_100M(8) | \
|
||||
PIN_OSPEED_100M(9) | \
|
||||
PIN_OSPEED_100M(10) | \
|
||||
PIN_OSPEED_100M(11) | \
|
||||
PIN_OSPEED_100M(12) | \
|
||||
PIN_OSPEED_100M(GPIOC_LED) | \
|
||||
PIN_OSPEED_100M(14) | \
|
||||
PIN_OSPEED_100M(15))
|
||||
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(0) | \
|
||||
PIN_PUPDR_PULLUP(1) | \
|
||||
PIN_PUPDR_PULLUP(2) | \
|
||||
PIN_PUPDR_PULLUP(3) | \
|
||||
PIN_PUPDR_PULLUP(4) | \
|
||||
PIN_PUPDR_PULLUP(5) | \
|
||||
PIN_PUPDR_PULLUP(6) | \
|
||||
PIN_PUPDR_PULLUP(7) | \
|
||||
PIN_PUPDR_PULLUP(8) | \
|
||||
PIN_PUPDR_PULLUP(9) | \
|
||||
PIN_PUPDR_PULLUP(10) | \
|
||||
PIN_PUPDR_PULLUP(11) | \
|
||||
PIN_PUPDR_PULLUP(12) | \
|
||||
PIN_PUPDR_FLOATING(GPIOC_LED) | \
|
||||
PIN_PUPDR_FLOATING(14) | \
|
||||
PIN_PUPDR_PULLUP(15))
|
||||
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(2) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_HIGH(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(8) | \
|
||||
PIN_ODR_HIGH(9) | \
|
||||
PIN_ODR_HIGH(10) | \
|
||||
PIN_ODR_HIGH(11) | \
|
||||
PIN_ODR_HIGH(12) | \
|
||||
PIN_ODR_HIGH(GPIOC_LED) | \
|
||||
PIN_ODR_HIGH(14) | \
|
||||
PIN_ODR_HIGH(15))
|
||||
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(2, 0) | \
|
||||
PIN_AFIO_AF(3, 0) | \
|
||||
PIN_AFIO_AF(4, 0) | \
|
||||
PIN_AFIO_AF(5, 0) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 0) | \
|
||||
PIN_AFIO_AF(9, 0) | \
|
||||
PIN_AFIO_AF(10, 0) | \
|
||||
PIN_AFIO_AF(11, 0) | \
|
||||
PIN_AFIO_AF(12, 0) | \
|
||||
PIN_AFIO_AF(GPIOC_LED, 0) | \
|
||||
PIN_AFIO_AF(14, 0) | \
|
||||
PIN_AFIO_AF(15, 0))
|
||||
|
||||
/*
|
||||
* GPIOD setup:
|
||||
*/
|
||||
#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \
|
||||
PIN_MODE_INPUT(1) | \
|
||||
PIN_MODE_INPUT(2) | \
|
||||
PIN_MODE_INPUT(3) | \
|
||||
PIN_MODE_INPUT(4) | \
|
||||
PIN_MODE_INPUT(5) | \
|
||||
PIN_MODE_INPUT(6) | \
|
||||
PIN_MODE_INPUT(7) | \
|
||||
PIN_MODE_INPUT(8) | \
|
||||
PIN_MODE_INPUT(9) | \
|
||||
PIN_MODE_INPUT(10) | \
|
||||
PIN_MODE_INPUT(11) | \
|
||||
PIN_MODE_INPUT(12) | \
|
||||
PIN_MODE_INPUT(13) | \
|
||||
PIN_MODE_INPUT(14) | \
|
||||
PIN_MODE_INPUT(15))
|
||||
#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
|
||||
PIN_OTYPE_PUSHPULL(1) | \
|
||||
PIN_OTYPE_PUSHPULL(2) | \
|
||||
PIN_OTYPE_PUSHPULL(3) | \
|
||||
PIN_OTYPE_PUSHPULL(4) | \
|
||||
PIN_OTYPE_PUSHPULL(5) | \
|
||||
PIN_OTYPE_PUSHPULL(6) | \
|
||||
PIN_OTYPE_PUSHPULL(7) | \
|
||||
PIN_OTYPE_PUSHPULL(8) | \
|
||||
PIN_OTYPE_PUSHPULL(9) | \
|
||||
PIN_OTYPE_PUSHPULL(10) | \
|
||||
PIN_OTYPE_PUSHPULL(11) | \
|
||||
PIN_OTYPE_PUSHPULL(12) | \
|
||||
PIN_OTYPE_PUSHPULL(13) | \
|
||||
PIN_OTYPE_PUSHPULL(14) | \
|
||||
PIN_OTYPE_PUSHPULL(15))
|
||||
#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(0) | \
|
||||
PIN_OSPEED_100M(1) | \
|
||||
PIN_OSPEED_100M(2) | \
|
||||
PIN_OSPEED_100M(3) | \
|
||||
PIN_OSPEED_100M(4) | \
|
||||
PIN_OSPEED_100M(5) | \
|
||||
PIN_OSPEED_100M(6) | \
|
||||
PIN_OSPEED_100M(7) | \
|
||||
PIN_OSPEED_100M(8) | \
|
||||
PIN_OSPEED_100M(9) | \
|
||||
PIN_OSPEED_100M(10) | \
|
||||
PIN_OSPEED_100M(11) | \
|
||||
PIN_OSPEED_100M(12) | \
|
||||
PIN_OSPEED_100M(13) | \
|
||||
PIN_OSPEED_100M(14) | \
|
||||
PIN_OSPEED_100M(15))
|
||||
#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(0) | \
|
||||
PIN_PUPDR_PULLUP(1) | \
|
||||
PIN_PUPDR_PULLUP(2) | \
|
||||
PIN_PUPDR_PULLUP(3) | \
|
||||
PIN_PUPDR_PULLUP(4) | \
|
||||
PIN_PUPDR_PULLUP(5) | \
|
||||
PIN_PUPDR_PULLUP(6) | \
|
||||
PIN_PUPDR_PULLUP(7) | \
|
||||
PIN_PUPDR_PULLUP(8) | \
|
||||
PIN_PUPDR_PULLUP(9) | \
|
||||
PIN_PUPDR_PULLUP(10) | \
|
||||
PIN_PUPDR_PULLUP(11) | \
|
||||
PIN_PUPDR_PULLUP(12) | \
|
||||
PIN_PUPDR_PULLUP(13) | \
|
||||
PIN_PUPDR_PULLUP(14) | \
|
||||
PIN_PUPDR_PULLUP(15))
|
||||
#define VAL_GPIOD_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(2) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_HIGH(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(8) | \
|
||||
PIN_ODR_HIGH(9) | \
|
||||
PIN_ODR_HIGH(10) | \
|
||||
PIN_ODR_HIGH(11) | \
|
||||
PIN_ODR_HIGH(12) | \
|
||||
PIN_ODR_HIGH(13) | \
|
||||
PIN_ODR_HIGH(14) | \
|
||||
PIN_ODR_HIGH(15))
|
||||
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(2, 0) | \
|
||||
PIN_AFIO_AF(3, 0) | \
|
||||
PIN_AFIO_AF(4, 0) | \
|
||||
PIN_AFIO_AF(5, 0) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 0) | \
|
||||
PIN_AFIO_AF(9, 0) | \
|
||||
PIN_AFIO_AF(10, 0) | \
|
||||
PIN_AFIO_AF(11, 0) | \
|
||||
PIN_AFIO_AF(12, 0) | \
|
||||
PIN_AFIO_AF(13, 0) | \
|
||||
PIN_AFIO_AF(14, 0) | \
|
||||
PIN_AFIO_AF(15, 0))
|
||||
|
||||
/*
|
||||
* GPIOE setup:
|
||||
*
|
||||
* PE0 - PIN0 (input pullup).
|
||||
* PE1 - PIN1 (input pullup).
|
||||
* PE2 - PIN2 (input floating).
|
||||
* PE3 - PIN3 (input pullup).
|
||||
* PE4 - PIN4 (input floating).
|
||||
* PE5 - PIN5 (input floating).
|
||||
* PE6 - PIN6 (input floating).
|
||||
* PE7 - PIN7 (input floating).
|
||||
* PE8 - PIN8 (input floating).
|
||||
* PE9 - PIN9 (input floating).
|
||||
* PE10 - PIN10 (input floating).
|
||||
* PE11 - PIN11 (input floating).
|
||||
* PE12 - PIN12 (input floating).
|
||||
* PE13 - PIN13 (input floating).
|
||||
* PE14 - PIN14 (input floating).
|
||||
* PE15 - PIN15 (input floating).
|
||||
*/
|
||||
#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \
|
||||
PIN_MODE_INPUT(1) | \
|
||||
PIN_MODE_INPUT(2) | \
|
||||
PIN_MODE_INPUT(3) | \
|
||||
PIN_MODE_INPUT(4) | \
|
||||
PIN_MODE_INPUT(5) | \
|
||||
PIN_MODE_INPUT(6) | \
|
||||
PIN_MODE_INPUT(7) | \
|
||||
PIN_MODE_INPUT(8) | \
|
||||
PIN_MODE_INPUT(9) | \
|
||||
PIN_MODE_INPUT(10) | \
|
||||
PIN_MODE_INPUT(11) | \
|
||||
PIN_MODE_INPUT(12) | \
|
||||
PIN_MODE_INPUT(13) | \
|
||||
PIN_MODE_INPUT(14) | \
|
||||
PIN_MODE_INPUT(15))
|
||||
#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
|
||||
PIN_OTYPE_PUSHPULL(1) | \
|
||||
PIN_OTYPE_PUSHPULL(2) | \
|
||||
PIN_OTYPE_PUSHPULL(3) | \
|
||||
PIN_OTYPE_PUSHPULL(4) | \
|
||||
PIN_OTYPE_PUSHPULL(5) | \
|
||||
PIN_OTYPE_PUSHPULL(6) | \
|
||||
PIN_OTYPE_PUSHPULL(7) | \
|
||||
PIN_OTYPE_PUSHPULL(8) | \
|
||||
PIN_OTYPE_PUSHPULL(9) | \
|
||||
PIN_OTYPE_PUSHPULL(10) | \
|
||||
PIN_OTYPE_PUSHPULL(11) | \
|
||||
PIN_OTYPE_PUSHPULL(12) | \
|
||||
PIN_OTYPE_PUSHPULL(13) | \
|
||||
PIN_OTYPE_PUSHPULL(14) | \
|
||||
PIN_OTYPE_PUSHPULL(15))
|
||||
#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(0) | \
|
||||
PIN_OSPEED_100M(1) | \
|
||||
PIN_OSPEED_100M(2) | \
|
||||
PIN_OSPEED_100M(3) | \
|
||||
PIN_OSPEED_100M(4) | \
|
||||
PIN_OSPEED_100M(5) | \
|
||||
PIN_OSPEED_100M(6) | \
|
||||
PIN_OSPEED_100M(7) | \
|
||||
PIN_OSPEED_100M(8) | \
|
||||
PIN_OSPEED_100M(9) | \
|
||||
PIN_OSPEED_100M(10) | \
|
||||
PIN_OSPEED_100M(11) | \
|
||||
PIN_OSPEED_100M(12) | \
|
||||
PIN_OSPEED_100M(13) | \
|
||||
PIN_OSPEED_100M(14) | \
|
||||
PIN_OSPEED_100M(15))
|
||||
#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(0) | \
|
||||
PIN_PUPDR_PULLUP(1) | \
|
||||
PIN_PUPDR_FLOATING(2) | \
|
||||
PIN_PUPDR_PULLUP(3) | \
|
||||
PIN_PUPDR_FLOATING(4) | \
|
||||
PIN_PUPDR_FLOATING(5) | \
|
||||
PIN_PUPDR_FLOATING(6) | \
|
||||
PIN_PUPDR_FLOATING(7) | \
|
||||
PIN_PUPDR_FLOATING(8) | \
|
||||
PIN_PUPDR_FLOATING(9) | \
|
||||
PIN_PUPDR_FLOATING(10) | \
|
||||
PIN_PUPDR_FLOATING(11) | \
|
||||
PIN_PUPDR_FLOATING(12) | \
|
||||
PIN_PUPDR_FLOATING(13) | \
|
||||
PIN_PUPDR_FLOATING(14) | \
|
||||
PIN_PUPDR_FLOATING(15))
|
||||
#define VAL_GPIOE_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(2) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_HIGH(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(8) | \
|
||||
PIN_ODR_HIGH(9) | \
|
||||
PIN_ODR_HIGH(10) | \
|
||||
PIN_ODR_HIGH(11) | \
|
||||
PIN_ODR_HIGH(12) | \
|
||||
PIN_ODR_HIGH(13) | \
|
||||
PIN_ODR_HIGH(14) | \
|
||||
PIN_ODR_HIGH(15))
|
||||
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(2, 0) | \
|
||||
PIN_AFIO_AF(3, 0) | \
|
||||
PIN_AFIO_AF(4, 0) | \
|
||||
PIN_AFIO_AF(5, 0) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0) | \
|
||||
PIN_AFIO_AF(9, 0) | \
|
||||
PIN_AFIO_AF(10, 0) | \
|
||||
PIN_AFIO_AF(11, 0) | \
|
||||
PIN_AFIO_AF(12, 0) | \
|
||||
PIN_AFIO_AF(13, 0) | \
|
||||
PIN_AFIO_AF(14, 0) | \
|
||||
PIN_AFIO_AF(15, 0))
|
||||
|
||||
/*
|
||||
* GPIOF setup:
|
||||
*
|
||||
*/
|
||||
#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \
|
||||
PIN_MODE_INPUT(1) | \
|
||||
PIN_MODE_INPUT(2) | \
|
||||
PIN_MODE_INPUT(3) | \
|
||||
PIN_MODE_INPUT(4) | \
|
||||
PIN_MODE_INPUT(5) | \
|
||||
PIN_MODE_INPUT(6) | \
|
||||
PIN_MODE_INPUT(7) | \
|
||||
PIN_MODE_INPUT(8) | \
|
||||
PIN_MODE_INPUT(9) | \
|
||||
PIN_MODE_INPUT(10) | \
|
||||
PIN_MODE_INPUT(11) | \
|
||||
PIN_MODE_INPUT(12) | \
|
||||
PIN_MODE_INPUT(13) | \
|
||||
PIN_MODE_INPUT(14) | \
|
||||
PIN_MODE_INPUT(15))
|
||||
#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
|
||||
PIN_OTYPE_PUSHPULL(1) | \
|
||||
PIN_OTYPE_PUSHPULL(2) | \
|
||||
PIN_OTYPE_PUSHPULL(3) | \
|
||||
PIN_OTYPE_PUSHPULL(4) | \
|
||||
PIN_OTYPE_PUSHPULL(5) | \
|
||||
PIN_OTYPE_PUSHPULL(6) | \
|
||||
PIN_OTYPE_PUSHPULL(7) | \
|
||||
PIN_OTYPE_PUSHPULL(8) | \
|
||||
PIN_OTYPE_PUSHPULL(9) | \
|
||||
PIN_OTYPE_PUSHPULL(10) | \
|
||||
PIN_OTYPE_PUSHPULL(11) | \
|
||||
PIN_OTYPE_PUSHPULL(12) | \
|
||||
PIN_OTYPE_PUSHPULL(13) | \
|
||||
PIN_OTYPE_PUSHPULL(14) | \
|
||||
PIN_OTYPE_PUSHPULL(15))
|
||||
#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(0) | \
|
||||
PIN_OSPEED_100M(1) | \
|
||||
PIN_OSPEED_100M(2) | \
|
||||
PIN_OSPEED_100M(3) | \
|
||||
PIN_OSPEED_100M(4) | \
|
||||
PIN_OSPEED_100M(5) | \
|
||||
PIN_OSPEED_100M(6) | \
|
||||
PIN_OSPEED_100M(7) | \
|
||||
PIN_OSPEED_100M(8) | \
|
||||
PIN_OSPEED_100M(9) | \
|
||||
PIN_OSPEED_100M(10) | \
|
||||
PIN_OSPEED_100M(11) | \
|
||||
PIN_OSPEED_100M(12) | \
|
||||
PIN_OSPEED_100M(13) | \
|
||||
PIN_OSPEED_100M(14) | \
|
||||
PIN_OSPEED_100M(15))
|
||||
#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(0) | \
|
||||
PIN_PUPDR_FLOATING(1) | \
|
||||
PIN_PUPDR_FLOATING(2) | \
|
||||
PIN_PUPDR_FLOATING(3) | \
|
||||
PIN_PUPDR_FLOATING(4) | \
|
||||
PIN_PUPDR_FLOATING(5) | \
|
||||
PIN_PUPDR_FLOATING(6) | \
|
||||
PIN_PUPDR_FLOATING(7) | \
|
||||
PIN_PUPDR_FLOATING(8) | \
|
||||
PIN_PUPDR_FLOATING(9) | \
|
||||
PIN_PUPDR_FLOATING(10) | \
|
||||
PIN_PUPDR_FLOATING(11) | \
|
||||
PIN_PUPDR_FLOATING(12) | \
|
||||
PIN_PUPDR_FLOATING(13) | \
|
||||
PIN_PUPDR_FLOATING(14) | \
|
||||
PIN_PUPDR_FLOATING(15))
|
||||
#define VAL_GPIOF_ODR (PIN_ODR_HIGH(0) | \
|
||||
PIN_ODR_HIGH(1) | \
|
||||
PIN_ODR_HIGH(2) | \
|
||||
PIN_ODR_HIGH(3) | \
|
||||
PIN_ODR_HIGH(4) | \
|
||||
PIN_ODR_HIGH(5) | \
|
||||
PIN_ODR_HIGH(6) | \
|
||||
PIN_ODR_HIGH(7) | \
|
||||
PIN_ODR_HIGH(8) | \
|
||||
PIN_ODR_HIGH(9) | \
|
||||
PIN_ODR_HIGH(10) | \
|
||||
PIN_ODR_HIGH(11) | \
|
||||
PIN_ODR_HIGH(12) | \
|
||||
PIN_ODR_HIGH(13) | \
|
||||
PIN_ODR_HIGH(14) | \
|
||||
PIN_ODR_HIGH(15))
|
||||
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0) | \
|
||||
PIN_AFIO_AF(1, 0) | \
|
||||
PIN_AFIO_AF(2, 0) | \
|
||||
PIN_AFIO_AF(3, 0) | \
|
||||
PIN_AFIO_AF(4, 0) | \
|
||||
PIN_AFIO_AF(5, 0) | \
|
||||
PIN_AFIO_AF(6, 0) | \
|
||||
PIN_AFIO_AF(7, 0))
|
||||
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0) | \
|
||||
PIN_AFIO_AF(9, 0) | \
|
||||
PIN_AFIO_AF(10, 0) | \
|
||||
PIN_AFIO_AF(11, 0) | \
|
||||
PIN_AFIO_AF(12, 0) | \
|
||||
PIN_AFIO_AF(13, 0) | \
|
||||
PIN_AFIO_AF(14, 0) | \
|
||||
PIN_AFIO_AF(15, 0))
|
||||
//#define TINYSA_F303
|
||||
//#define USB_DP_R_VDD
|
||||
|
||||
#ifdef TINYSA_F303
|
||||
/*
|
||||
* USB bus activation/de-activation macro, required by the USB driver.
|
||||
*/
|
||||
#ifdef USB_DP_R_PA10
|
||||
#define usb_lld_connect_bus(usbp) palSetPad(GPIOA, GPIOA_USB_DISC)
|
||||
#define usb_lld_disconnect_bus(usbp) palClearPad(GPIO, GPIOA_USB_DISC)
|
||||
#endif
|
||||
|
||||
#ifdef USB_DP_R_VDD
|
||||
#define usb_lld_connect_bus(usbp)
|
||||
#define usb_lld_disconnect_bus(usbp)
|
||||
#else // USB_DP connect to VDD by 1.5K R, and USB_DP short with PA10
|
||||
#define usb_lld_connect_bus(usbp) palSetPadMode(GPIOA, GPIOA_USB_DISC, PAL_MODE_INPUT)
|
||||
#define usb_lld_disconnect_bus(usbp) palClearPad(GPIOA, GPIOA_USB_DISC)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
@ -0,0 +1,7 @@
|
||||
# List of all the board related files.
|
||||
#BOARDSRC = ${CHIBIOS}/os/hal/boards/NANOVNA_STM32_F303/board.c
|
||||
BOARDSRC = ${PROJ}/NANOVNA_STM32_F303/board.c
|
||||
|
||||
# Required include directories
|
||||
#BOARDINC = ${CHIBIOS}/os/hal/boards/NANOSDR_STM32_F303
|
||||
BOARDINC = ${PROJ}/NANOVNA_STM32_F303
|
||||
@ -0,0 +1,96 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32F303xC memory setup.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
flash0 : org = 0x08000000, len = 192k
|
||||
flash1 : org = 0x00000000, len = 0
|
||||
flash2 : org = 0x00000000, len = 0
|
||||
flash3 : org = 0x00000000, len = 0
|
||||
flash4 : org = 0x00000000, len = 0
|
||||
flash5 : org = 0x00000000, len = 0
|
||||
flash6 : org = 0x00000000, len = 0
|
||||
flash7 : org = 0x08030000, len = 64k
|
||||
ram0 : org = 0x20000000, len = 40k
|
||||
ram1 : org = 0x00000000, len = 0
|
||||
ram2 : org = 0x00000000, len = 0
|
||||
ram3 : org = 0x00000000, len = 0
|
||||
ram4 : org = 0x10000000, len = 8k
|
||||
ram5 : org = 0x00000000, len = 0
|
||||
ram6 : org = 0x00000000, len = 0
|
||||
ram7 : org = 0x00000000, len = 0
|
||||
}
|
||||
|
||||
/* For each data/text section two region are defined, a virtual region
|
||||
and a load region (_LMA suffix).*/
|
||||
|
||||
/* Flash region to be used for exception vectors.*/
|
||||
REGION_ALIAS("VECTORS_FLASH", flash0);
|
||||
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for constructors and destructors.*/
|
||||
REGION_ALIAS("XTORS_FLASH", flash0);
|
||||
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for code text.*/
|
||||
REGION_ALIAS("TEXT_FLASH", flash0);
|
||||
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for read only data.*/
|
||||
REGION_ALIAS("RODATA_FLASH", flash0);
|
||||
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for various.*/
|
||||
REGION_ALIAS("VARIOUS_FLASH", flash0);
|
||||
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be used for RAM(n) initialization data.*/
|
||||
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
|
||||
|
||||
/* Flash region to be saved calibration data */
|
||||
REGION_ALIAS("CALDATA_FLASH", flash7);
|
||||
|
||||
/* RAM region to be used for Main stack. This stack accommodates the processing
|
||||
of all exceptions and interrupts.*/
|
||||
REGION_ALIAS("MAIN_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the process stack. This is the stack used by
|
||||
the main() function.*/
|
||||
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for data segment.*/
|
||||
REGION_ALIAS("DATA_RAM", ram0);
|
||||
REGION_ALIAS("DATA_RAM_LMA", flash0);
|
||||
|
||||
/* RAM region to be used for BSS segment.*/
|
||||
REGION_ALIAS("BSS_RAM", ram0);
|
||||
|
||||
/* RAM region to be used for the default heap.*/
|
||||
REGION_ALIAS("HEAP_RAM", ram0);
|
||||
|
||||
/* Generic rules inclusion.*/
|
||||
INCLUDE rules.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.calsave (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.calsave)
|
||||
} > CALDATA_FLASH
|
||||
}
|
||||
@ -0,0 +1,41 @@
|
||||
|
||||
// F303 related ADC defines
|
||||
|
||||
|
||||
#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */
|
||||
#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */
|
||||
|
||||
|
||||
#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
|
||||
#define ADC_CHSELR_CHSEL6 ADC_CHANNEL_IN3
|
||||
#define ADC_CHSELR_CHSEL7 ADC_CHANNEL_IN4
|
||||
#define ADC_SMPR_SMP_239P5 7U
|
||||
#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */
|
||||
#define ADC_CFGR_RES_12BIT (0 << 3)
|
||||
/*
|
||||
msg_t adcConvert(ADCDriver *adcp,
|
||||
const ADCConversionGroup *grpp,
|
||||
adcsample_t *samples,
|
||||
size_t depth);
|
||||
*/
|
||||
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
|
||||
//ADC_Common_TypeDef *adcc;
|
||||
#define ADC_CHSELR_VREFINT ADC_CHANNEL_IN18
|
||||
#define ADC_CHSELR_VBAT ADC_CHANNEL_IN17
|
||||
|
||||
#define ADC_ISR_ADRDY_Pos (0U)
|
||||
#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
|
||||
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
|
||||
#define ADC_IER_ADRDYIE_Pos (0U)
|
||||
#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
|
||||
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
|
||||
#define ADC_IER_AWD1IE_Pos (7U)
|
||||
#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
|
||||
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
|
||||
#define ADC_IER_EOCIE_Pos (2U)
|
||||
#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
|
||||
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
|
||||
#define ADC_IER_EOSMPIE_Pos (1U)
|
||||
#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
|
||||
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
|
||||
|
||||
@ -0,0 +1,938 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ADCv3/hal_adc_lld.c
|
||||
* @brief STM32F3xx ADC subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define ADC1_DMA_CHANNEL \
|
||||
STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
|
||||
|
||||
#define ADC2_DMA_CHANNEL \
|
||||
STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
|
||||
|
||||
#define ADC3_DMA_CHANNEL \
|
||||
STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
|
||||
|
||||
#define ADC4_DMA_CHANNEL \
|
||||
STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN)
|
||||
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
#if STM32_ADC_COMPACT_SAMPLES
|
||||
/* Compact type dual mode.*/
|
||||
#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
|
||||
#define ADC_DMA_MDMA ADC_CCR_MDMA_HWORD
|
||||
|
||||
#else /* !STM32_ADC_COMPACT_SAMPLES */
|
||||
/* Large type dual mode.*/
|
||||
#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
|
||||
#define ADC_DMA_MDMA ADC_CCR_MDMA_WORD
|
||||
#endif /* !STM32_ADC_COMPACT_SAMPLES */
|
||||
|
||||
#else /* !STM32_ADC_DUAL_MODE */
|
||||
#if STM32_ADC_COMPACT_SAMPLES
|
||||
/* Compact type single mode.*/
|
||||
#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
|
||||
#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
|
||||
|
||||
#else /* !STM32_ADC_COMPACT_SAMPLES */
|
||||
/* Large type single mode.*/
|
||||
#define ADC_DMA_SIZE (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
|
||||
#define ADC_DMA_MDMA ADC_CCR_MDMA_DISABLED
|
||||
#endif /* !STM32_ADC_COMPACT_SAMPLES */
|
||||
#endif /* !STM32_ADC_DUAL_MODE */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/** @brief ADC1 driver identifier.*/
|
||||
#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
|
||||
ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
/** @brief ADC2 driver identifier.*/
|
||||
#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
|
||||
ADCDriver ADCD2;
|
||||
#endif
|
||||
|
||||
/** @brief ADC3 driver identifier.*/
|
||||
#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
|
||||
ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
/** @brief ADC4 driver identifier.*/
|
||||
#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
|
||||
ADCDriver ADCD4;
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static const ADCConfig default_config = {
|
||||
difsel: 0
|
||||
};
|
||||
|
||||
static uint32_t clkmask;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC voltage regulator.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_vreg_on(ADCDriver *adcp) {
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
adcp->adcm->CR = 0; /* RM 12.4.3.*/
|
||||
adcp->adcm->CR = ADC_CR_ADVREGEN_0;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR = ADC_CR_ADVREGEN_0;
|
||||
#endif
|
||||
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
adcp->adcm->CR = 0; /* RM 16.3.6.*/
|
||||
adcp->adcm->CR = ADC_CR_ADVREGEN;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR = ADC_CR_ADVREGEN;
|
||||
#endif
|
||||
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the ADC voltage regulator.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_vreg_off(ADCDriver *adcp) {
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
adcp->adcm->CR = 0; /* RM 12.4.3.*/
|
||||
adcp->adcm->CR = ADC_CR_ADVREGEN_1;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR = 0;
|
||||
adcp->adcs->CR = ADC_CR_ADVREGEN_1;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
adcp->adcm->CR = 0; /* RM 12.4.3.*/
|
||||
adcp->adcm->CR = ADC_CR_DEEPPWD;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR = 0;
|
||||
adcp->adcs->CR = ADC_CR_DEEPPWD;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC analog circuit.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_analog_on(ADCDriver *adcp) {
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
adcp->adcm->CR |= ADC_CR_ADEN;
|
||||
while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
|
||||
;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR |= ADC_CR_ADEN;
|
||||
while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
|
||||
;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
adcp->adcm->CR |= ADC_CR_ADEN;
|
||||
while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)
|
||||
;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR |= ADC_CR_ADEN;
|
||||
while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)
|
||||
;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the ADC analog circuit.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_analog_off(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcm->CR |= ADC_CR_ADDIS;
|
||||
while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
|
||||
;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcs->CR |= ADC_CR_ADDIS;
|
||||
while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
|
||||
;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calibrates and ADC unit.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_calibrate(ADCDriver *adcp) {
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
|
||||
adcp->adcm->CR |= ADC_CR_ADCAL;
|
||||
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
|
||||
;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
|
||||
adcp->adcs->CR |= ADC_CR_ADCAL;
|
||||
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
|
||||
;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");
|
||||
adcp->adcm->CR |= ADC_CR_ADCAL;
|
||||
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
|
||||
;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");
|
||||
adcp->adcs->CR |= ADC_CR_ADCAL;
|
||||
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
|
||||
;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops an ongoing conversion, if any.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*/
|
||||
static void adc_lld_stop_adc(ADCDriver *adcp) {
|
||||
|
||||
if (adcp->adcm->CR & ADC_CR_ADSTART) {
|
||||
adcp->adcm->CR |= ADC_CR_ADSTP;
|
||||
while (adcp->adcm->CR & ADC_CR_ADSTP)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC DMA ISR service routine.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
* @param[in] flags pre-shifted content of the ISR register
|
||||
*/
|
||||
static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
|
||||
|
||||
/* DMA errors handling.*/
|
||||
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
|
||||
/* DMA, this could help only if the DMA tries to access an unmapped
|
||||
address space or violates alignment rules.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
|
||||
}
|
||||
else {
|
||||
/* It is possible that the conversion group has already be reset by the
|
||||
ADC error handler, in this case this interrupt is spurious.*/
|
||||
if (adcp->grpp != NULL) {
|
||||
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
|
||||
/* Transfer complete processing.*/
|
||||
_adc_isr_full_code(adcp);
|
||||
}
|
||||
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
|
||||
/* Half transfer processing.*/
|
||||
_adc_isr_half_code(adcp);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC ISR service routine.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
* @param[in] isr content of the ISR register
|
||||
*/
|
||||
static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
|
||||
|
||||
/* It could be a spurious interrupt caused by overflows after DMA disabling,
|
||||
just ignore it in this case.*/
|
||||
if (adcp->grpp != NULL) {
|
||||
/* Note, an overflow may occur after the conversion ended before the driver
|
||||
is able to stop the ADC, this is why the DMA channel is checked too.*/
|
||||
if ((isr & ADC_ISR_OVR) &&
|
||||
(dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
|
||||
/* ADC overflow condition, this could happen only if the DMA is unable
|
||||
to read data fast enough.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
|
||||
}
|
||||
if (isr & ADC_ISR_AWD1) {
|
||||
/* Analog watchdog error.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_AWD1);
|
||||
}
|
||||
if (isr & ADC_ISR_AWD2) {
|
||||
/* Analog watchdog error.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_AWD2);
|
||||
}
|
||||
if (isr & ADC_ISR_AWD3) {
|
||||
/* Analog watchdog error.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_AWD3);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC1/ADC2 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
__attribute__((weak)) OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {
|
||||
uint32_t isr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
isr = ADC1->ISR;
|
||||
isr |= ADC2->ISR;
|
||||
ADC1->ISR = isr;
|
||||
ADC2->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD1, isr);
|
||||
#else /* !STM32_ADC_DUAL_MODE */
|
||||
#if STM32_ADC_USE_ADC1
|
||||
isr = ADC1->ISR;
|
||||
ADC1->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD1, isr);
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC2
|
||||
isr = ADC2->ISR;
|
||||
ADC2->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD2, isr);
|
||||
#endif
|
||||
#endif /* !STM32_ADC_DUAL_MODE */
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC3 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(STM32_ADC3_HANDLER) {
|
||||
uint32_t isr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
isr = ADC3->ISR;
|
||||
ADC3->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD3, isr);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
/**
|
||||
* @brief ADC4 interrupt handler (as ADC3 slave).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
|
||||
uint32_t isr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
isr = ADC4->ISR;
|
||||
ADC4->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD3, isr);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_ADC_DUAL_MODE */
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC4 interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
|
||||
uint32_t isr;
|
||||
|
||||
OSAL_IRQ_PROLOGUE();
|
||||
|
||||
isr = ADC4->ISR;
|
||||
ADC4->ISR = isr;
|
||||
|
||||
adc_lld_serve_interrupt(&ADCD4, isr);
|
||||
|
||||
OSAL_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC4 */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level ADC driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_init(void) {
|
||||
|
||||
clkmask = 0;
|
||||
|
||||
#if STM32_ADC_USE_ADC1
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD1);
|
||||
#if defined(ADC1_2_COMMON)
|
||||
ADCD1.adcc = ADC1_2_COMMON;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADCD1.adcc = ADC123_COMMON;
|
||||
#else
|
||||
ADCD1.adcc = ADC1_COMMON;
|
||||
#endif
|
||||
ADCD1.adcm = ADC1;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ADCD1.adcs = ADC2;
|
||||
#endif
|
||||
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
|
||||
ADCD1.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD2);
|
||||
#if defined(ADC1_2_COMMON)
|
||||
ADCD2.adcc = ADC1_2_COMMON;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADCD2.adcc = ADC123_COMMON;
|
||||
#endif
|
||||
ADCD2.adcm = ADC2;
|
||||
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
|
||||
ADCD2.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD3);
|
||||
#if defined(ADC3_4_COMMON)
|
||||
ADCD3.adcc = ADC3_4_COMMON;
|
||||
#elif defined(ADC123_COMMON)
|
||||
ADCD1.adcc = ADC123_COMMON;
|
||||
#else
|
||||
ADCD3.adcc = ADC3_COMMON;
|
||||
#endif
|
||||
ADCD3.adcm = ADC3;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ADCD3.adcs = ADC4;
|
||||
#endif
|
||||
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
|
||||
ADCD3.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD4);
|
||||
ADCD4.adcc = ADC3_4_COMMON;
|
||||
ADCD4.adcm = ADC4;
|
||||
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
|
||||
ADCD4.dmamode = ADC_DMA_SIZE |
|
||||
STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_DIR_P2M |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
|
||||
#endif /* STM32_ADC_USE_ADC4 */
|
||||
|
||||
/* IRQs setup.*/
|
||||
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
|
||||
nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC3
|
||||
nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#endif
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC4
|
||||
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* ADC units pre-initializations.*/
|
||||
#if defined(STM32F3XX)
|
||||
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
|
||||
rccEnableADC12(FALSE);
|
||||
rccResetADC12();
|
||||
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC12(FALSE);
|
||||
#endif
|
||||
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
|
||||
rccEnableADC34(FALSE);
|
||||
rccResetADC34();
|
||||
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC34(FALSE);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(FALSE);
|
||||
rccResetADC123();
|
||||
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
rccDisableADC123(FALSE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start(ADCDriver *adcp) {
|
||||
|
||||
/* Handling the default configuration.*/
|
||||
if (adcp->config == NULL) {
|
||||
adcp->config = &default_config;
|
||||
}
|
||||
|
||||
/* If in stopped state then enables the ADC and DMA clocks.*/
|
||||
if (adcp->state == ADC_STOP) {
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 0);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC12(FALSE);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(FALSE);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC1 */
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
if (&ADCD2 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 1);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC12(FALSE);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(FALSE);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC2 */
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
if (&ADCD3 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 2);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC34(FALSE);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(FALSE);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC3 */
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
if (&ADCD4 == adcp) {
|
||||
bool b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC4_DMA_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
|
||||
(void *)adcp);
|
||||
osalDbgAssert(!b, "stream already allocated");
|
||||
|
||||
clkmask |= (1 << 3);
|
||||
#if defined(STM32F3XX)
|
||||
rccEnableADC34(FALSE);
|
||||
#endif
|
||||
#if defined(STM32L4XX)
|
||||
rccEnableADC123(FALSE);
|
||||
#endif
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC4 */
|
||||
|
||||
/* Setting DMA peripheral-side pointer.*/
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
|
||||
#else
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
|
||||
#endif
|
||||
|
||||
/* Differential channels setting.*/
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
adcp->adcm->DIFSEL = adcp->config->difsel;
|
||||
adcp->adcs->DIFSEL = adcp->config->difsel;
|
||||
#else
|
||||
adcp->adcm->DIFSEL = adcp->config->difsel;
|
||||
#endif
|
||||
|
||||
/* Master ADC calibration.*/
|
||||
adc_lld_vreg_on(adcp);
|
||||
adc_lld_calibrate(adcp);
|
||||
|
||||
/* Master ADC enabled here in order to reduce conversions latencies.*/
|
||||
adc_lld_analog_on(adcp);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop(ADCDriver *adcp) {
|
||||
|
||||
/* If in ready state then disables the ADC clock and analog part.*/
|
||||
if (adcp->state == ADC_READY) {
|
||||
|
||||
/* Releasing the associated DMA channel.*/
|
||||
dmaStreamRelease(adcp->dmastp);
|
||||
|
||||
/* Stopping the ongoing conversion, if any.*/
|
||||
adc_lld_stop_adc(adcp);
|
||||
|
||||
/* Disabling ADC analog circuit and regulator.*/
|
||||
adc_lld_analog_off(adcp);
|
||||
adc_lld_vreg_off(adcp);
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC2
|
||||
if (&ADCD1 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3
|
||||
if (&ADCD1 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 2);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC4
|
||||
if (&ADCD1 == adcp) {
|
||||
#if defined(STM32F3XX)
|
||||
/* Resetting CCR options except default ones.*/
|
||||
adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
|
||||
#endif
|
||||
clkmask &= ~(1 << 3);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32F3XX)
|
||||
if ((clkmask & 0x3) == 0) {
|
||||
rccDisableADC12(FALSE);
|
||||
}
|
||||
if ((clkmask & 0xC) == 0) {
|
||||
rccDisableADC34(FALSE);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4XX)
|
||||
if ((clkmask & 0x7) == 0) {
|
||||
rccDisableADC123(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts an ADC conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start_conversion(ADCDriver *adcp) {
|
||||
uint32_t dmamode, cfgr;
|
||||
const ADCConversionGroup *grpp = adcp->grpp;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
uint32_t ccr = grpp->ccr & ~(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK);
|
||||
#endif
|
||||
|
||||
osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
|
||||
"odd number of channels in dual mode");
|
||||
|
||||
/* Calculating control registers values.*/
|
||||
dmamode = adcp->dmamode;
|
||||
cfgr = grpp->cfgr | ADC_CFGR_DMAEN;
|
||||
if (grpp->circular) {
|
||||
dmamode |= STM32_DMA_CR_CIRC;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
ccr |= ADC_CCR_DMACFG_CIRCULAR;
|
||||
#else
|
||||
cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
|
||||
#endif
|
||||
if (adcp->depth > 1) {
|
||||
/* If circular buffer depth > 1, then the half transfer interrupt
|
||||
is enabled in order to allow streaming processing.*/
|
||||
dmamode |= STM32_DMA_CR_HTIE;
|
||||
}
|
||||
}
|
||||
|
||||
/* DMA setup.*/
|
||||
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
|
||||
(uint32_t)adcp->depth);
|
||||
#else
|
||||
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
|
||||
(uint32_t)adcp->depth);
|
||||
#endif
|
||||
dmaStreamSetMode(adcp->dmastp, dmamode);
|
||||
dmaStreamEnable(adcp->dmastp);
|
||||
|
||||
/* ADC setup, if it is defined a callback for the analog watch dog then it
|
||||
is enabled.*/
|
||||
adcp->adcm->ISR = adcp->adcm->ISR;
|
||||
adcp->adcm->IER = ADC_IER_OVR | ADC_IER_AWD1;
|
||||
adcp->adcm->TR1 = grpp->tr1;
|
||||
#if STM32_ADC_DUAL_MODE
|
||||
|
||||
/* Configuring the CCR register with the user-specified settings
|
||||
in the conversion group configuration structure, static settings are
|
||||
preserved.*/
|
||||
adcp->adcc->CCR = (adcp->adcc->CCR &
|
||||
(ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK)) | ccr;
|
||||
|
||||
adcp->adcm->SMPR1 = grpp->smpr[0];
|
||||
adcp->adcm->SMPR2 = grpp->smpr[1];
|
||||
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
|
||||
adcp->adcm->SQR2 = grpp->sqr[1];
|
||||
adcp->adcm->SQR3 = grpp->sqr[2];
|
||||
adcp->adcm->SQR4 = grpp->sqr[3];
|
||||
adcp->adcs->SMPR1 = grpp->ssmpr[0];
|
||||
adcp->adcs->SMPR2 = grpp->ssmpr[1];
|
||||
adcp->adcs->SQR1 = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
|
||||
adcp->adcs->SQR2 = grpp->ssqr[1];
|
||||
adcp->adcs->SQR3 = grpp->ssqr[2];
|
||||
adcp->adcs->SQR4 = grpp->ssqr[3];
|
||||
|
||||
#else /* !STM32_ADC_DUAL_MODE */
|
||||
adcp->adcm->SMPR1 = grpp->smpr[0];
|
||||
adcp->adcm->SMPR2 = grpp->smpr[1];
|
||||
adcp->adcm->SQR1 = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
|
||||
adcp->adcm->SQR2 = grpp->sqr[1];
|
||||
adcp->adcm->SQR3 = grpp->sqr[2];
|
||||
adcp->adcm->SQR4 = grpp->sqr[3];
|
||||
#endif /* !STM32_ADC_DUAL_MODE */
|
||||
|
||||
/* ADC configuration.*/
|
||||
adcp->adcm->CFGR = cfgr;
|
||||
|
||||
/* Starting conversion.*/
|
||||
adcp->adcm->CR |= ADC_CR_ADSTART;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops an ongoing conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp) {
|
||||
|
||||
dmaStreamDisable(adcp->dmastp);
|
||||
adc_lld_stop_adc(adcp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VREFEN bit.
|
||||
* @details The VREFEN bit is required in order to sample the VREF channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableVREF(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC12_CCR_VREFEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VREFEN bit.
|
||||
* @details The VREFEN bit is required in order to sample the VREF channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableVREF(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC12_CCR_VREFEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the TSEN bit.
|
||||
* @details The TSEN bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableTS(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC_CCR_TSEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the TSEN bit.
|
||||
* @details The TSEN bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableTS(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC_CCR_TSEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VBATEN bit.
|
||||
* @details The VBATEN bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32EnableVBAT(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR |= ADC12_CCR_VBATEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VBATEN bit.
|
||||
* @details The VBATEN bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adcSTM32DisableVBAT(ADCDriver *adcp) {
|
||||
|
||||
adcp->adcc->CCR &= ~ADC12_CCR_VBATEN;
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
/** @} */
|
||||
@ -0,0 +1,254 @@
|
||||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F3xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F3xx_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#define STM32_HSI_ENABLED FALSE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#define STM32_PREDIV_VALUE 1
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
// Set SPI1 more faster use PPRE2 max speed
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2
|
||||
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
|
||||
//#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
|
||||
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||
//#define STM32_USART2SW STM32_USART2SW_PCLK
|
||||
//#define STM32_USART3SW STM32_USART3SW_PCLK
|
||||
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
|
||||
//#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
|
||||
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
|
||||
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
|
||||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
/*
|
||||
* RTC driver system settings for stm32f303
|
||||
*/
|
||||
|
||||
#ifndef VNA_USE_LSE
|
||||
// Use 40kHz LSI
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#define STM32_RTC_PRESA_VALUE 40
|
||||
#define STM32_RTC_PRESS_VALUE 1000
|
||||
#else
|
||||
// Use 32768Hz LSE
|
||||
#define STM32_LSE_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED FALSE
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
||||
#define STM32_RTC_PRESA_VALUE 32
|
||||
#define STM32_RTC_PRESS_VALUE 1024
|
||||
#define STM32_LSEDRV (3 << 3)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#define STM32_ADC_USE_ADC2 TRUE
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||
//#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||
//#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||
#define STM32_ADC_ADC12_DMA_PRIORITY 2
|
||||
//#define STM32_ADC_ADC34_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY 2
|
||||
//#define STM32_ADC_ADC34_IRQ_PRIORITY 5
|
||||
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
|
||||
//#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
|
||||
//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
|
||||
//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
//#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC_DUAL_MODE FALSE
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE FALSE
|
||||
#define STM32_DAC_USE_DAC1_CH1 TRUE
|
||||
#define STM32_DAC_USE_DAC1_CH2 TRUE
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
|
||||
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
|
||||
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
|
||||
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
|
||||
|
||||
#define STM32_DISABLE_EXTI2122_HANDLER TRUE
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 TRUE
|
||||
#define STM32_GPT_USE_TIM4 TRUE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 2
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 2
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 TRUE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 3
|
||||
#define STM32_I2C_USE_DMA FALSE
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI1 FALSE
|
||||
#define STM32_I2S_USE_SPI2 TRUE
|
||||
#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
|
||||
STM32_I2S_MODE_RX)
|
||||
#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \
|
||||
STM32_I2S_MODE_RX )
|
||||
#define STM32_I2S_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_I2S_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 3
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 3
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 FALSE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 3
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 3
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 TRUE
|
||||
#define STM32_SERIAL_USE_USART2 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 3
|
||||
#define STM32_SERIAL_USART2_PRIORITY 3
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 TRUE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 2
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY 2
|
||||
#define STM32_ST_USE_TIMER 2
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 3
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 TRUE
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG FALSE
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
@ -0,0 +1,145 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2020, Dmitry (DiSlord) dislordlive@gmail.com
|
||||
* All rights reserved.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 3, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* The software is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GNU Radio; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
#include "nanovna.h"
|
||||
|
||||
#ifdef __USE_RTC__
|
||||
|
||||
// Compact STM32 RTC time library
|
||||
#if HAL_USE_RTC == TRUE
|
||||
#error "Error VNA use self RTC lib, define HAL_USE_RTC = FALSE in halconf.h"
|
||||
#endif
|
||||
|
||||
// Get RTC time as binary structure in 0x00HHMMSS
|
||||
uint32_t rtc_get_tr_bin(void){
|
||||
uint32_t tr = RTC->TR;
|
||||
uint32_t v = (tr&0x0F0F0F) + ((tr&0x707070)>>1) + ((tr&0x707070)>>3);
|
||||
return v;
|
||||
}
|
||||
|
||||
// Get RTC time as binary structure in 0x00YYMMDD
|
||||
uint32_t rtc_get_dr_bin(void){
|
||||
uint32_t dr = RTC->DR;
|
||||
uint32_t v = (dr&0x000F0F0F) + ((dr&0x00F01030)>>1) + ((dr&0x00F01030)>>3);
|
||||
return v;// | ((dr&0xE000)<<15); // day of week at end
|
||||
}
|
||||
|
||||
uint32_t rtc_get_FAT(void) {
|
||||
uint32_t fattime;
|
||||
uint32_t tr = rtc_get_tr_bin();
|
||||
uint32_t dr = rtc_get_dr_bin();
|
||||
fattime = ((tr>> 0)&0xFF) >> 1U; // Seconds / 2
|
||||
fattime |= ((tr>> 8)&0xFF) << 5U; // Minutes
|
||||
fattime |= ((tr>>16)&0xFF) << 11U; // Hour
|
||||
fattime |= ((dr>> 0)&0xFF) << 16U; // Day
|
||||
fattime |= ((dr>> 8)&0xFF) << 21U; // Month
|
||||
fattime |= (((dr>>16)&0xFF) + RTC_START_YEAR - 1980) << 25U; // Local year begin from 2000, fat from 1980
|
||||
return fattime;
|
||||
}
|
||||
|
||||
void rtc_set_time(uint32_t dr, uint32_t tr) {
|
||||
// Beginning of configuration procedure.
|
||||
RTC->ISR |= RTC_ISR_INIT;
|
||||
while ((RTC->ISR & RTC_ISR_INITF) == 0)
|
||||
;
|
||||
// Writing the registers.
|
||||
RTC->TR = tr;
|
||||
RTC->DR = dr;
|
||||
RTC->ISR &= ~RTC_ISR_INIT;
|
||||
}
|
||||
|
||||
#define RTC_PRER(a, s) ((((a) - 1) << 16) | ((s) - 1))
|
||||
|
||||
// Initiate RTC clock, LSE or LSI generators initiate by ChibiOS !!!
|
||||
void rtc_init(void){
|
||||
// Disable write protection.
|
||||
RTC->WPR = 0xCA;
|
||||
RTC->WPR = 0x53;
|
||||
// If calendar has not been initialized yet then proceed with the initial setup.
|
||||
if (!(RTC->ISR & RTC_ISR_INITS)) {
|
||||
// Beginning of configuration procedure.
|
||||
RTC->ISR |= RTC_ISR_INIT;
|
||||
while ((RTC->ISR & RTC_ISR_INITF) == 0)
|
||||
;
|
||||
RTC->CR = 0;
|
||||
RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT.
|
||||
RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE);
|
||||
RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE);
|
||||
RTC->ISR &= ~RTC_ISR_INIT;
|
||||
}
|
||||
else
|
||||
RTC->ISR &= ~RTC_ISR_RSF;
|
||||
#if 0
|
||||
// ChibiOS init BDCR by self!!
|
||||
// For add auto select RTC source need rewrite it
|
||||
// see hal_lld_backup_domain_init() in hal_lld.c for every CPU
|
||||
// Default RTC clock is LSE, but it possible not launch if no quartz installed
|
||||
uint32_t rtc_drv = STM32_RTCSEL_LSI;
|
||||
uint32_t rtc_prer = RTC_PRER(40, 1000);
|
||||
|
||||
// If LSE off try launch it
|
||||
if ((RCC->BDCR & RCC_BDCR_LSEON) == 0){
|
||||
// Try start LSE
|
||||
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
|
||||
uint32_t count = 65535;
|
||||
do{
|
||||
if (RCC->BDCR & RCC_BDCR_LSERDY) break;
|
||||
}while (--count);// Waits until LSE is stable. or count == 0
|
||||
}
|
||||
// Check, if LSE ready, then prepare it data
|
||||
if (RCC->BDCR & RCC_BDCR_LSERDY){
|
||||
rtc_drv = STM32_RTCSEL_LSE;
|
||||
rtc_prer = RTC_PRER(32, 1024);
|
||||
} else{
|
||||
// Try start LSI
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
|
||||
;
|
||||
}
|
||||
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
// If the backup domain hasn't been initialized yet then proceed with initialization or source different
|
||||
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0 || (RCC->BDCR & STM32_RTCSEL_MASK)!=rtc_drv) {
|
||||
// Backup domain reset.
|
||||
RCC->BDCR = RCC_BDCR_BDRST;
|
||||
RCC->BDCR = 0;
|
||||
// Selects clock source.
|
||||
RCC->BDCR |= rtc_drv;
|
||||
// Disable write protection.
|
||||
RTC->WPR = 0xCA;
|
||||
RTC->WPR = 0x53;
|
||||
// Beginning of configuration procedure.
|
||||
RTC->ISR |= RTC_ISR_INIT;
|
||||
while ((RTC->ISR & RTC_ISR_INITF) == 0)
|
||||
;
|
||||
// Prescaler value loaded in registers.
|
||||
RTC->CR = 0;
|
||||
RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT.
|
||||
RTC->PRER = rtc_prer;
|
||||
RTC->PRER = rtc_prer;
|
||||
// Finalizing of configuration procedure.
|
||||
RTC->ISR &= ~RTC_ISR_INIT;
|
||||
RCC->BDCR |= RCC_BDCR_RTCEN; // RTC clock enabled.
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in new issue