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42 lines
2.2 KiB
42 lines
2.2 KiB
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// F303 related ADC defines
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#define ADC_SMPR_SMP_247P5 6 /**< @brief 260 cycles conversion time. */
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#define ADC_SMPR_SMP_24P5 3 /**< @brief 37 cycles conversion time. */
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#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
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#define ADC_CHSELR_CHSEL6 ADC_CHANNEL_IN3
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#define ADC_CHSELR_CHSEL7 ADC_CHANNEL_IN4
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#define ADC_SMPR_SMP_239P5 7U
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#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */
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#define ADC_CFGR_RES_12BIT (0 << 3)
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/*
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msg_t adcConvert(ADCDriver *adcp,
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const ADCConversionGroup *grpp,
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adcsample_t *samples,
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size_t depth);
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*/
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#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
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//ADC_Common_TypeDef *adcc;
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#define ADC_CHSELR_VREFINT ADC_CHANNEL_IN18
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#define ADC_CHSELR_VBAT ADC_CHANNEL_IN17
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#define ADC_ISR_ADRDY_Pos (0U)
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#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
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#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
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#define ADC_IER_ADRDYIE_Pos (0U)
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#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
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#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
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#define ADC_IER_AWD1IE_Pos (7U)
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#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
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#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
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#define ADC_IER_EOCIE_Pos (2U)
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#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
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#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
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#define ADC_IER_EOSMPIE_Pos (1U)
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#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
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#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
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