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V0.2 pinning and power RF control

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tinySA-v0.2
erikkaashoek 6 years ago
parent f2137f4f97
commit 730fd6558d
2 changed files with 92 additions and 83 deletions
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124
NANOVNA_STM32_F072/board.h
Unescape View File

@ -47,12 +47,12 @@
/* on-board */ /* on-board */
#define GPIOA_PE_SEL 0 //#define GPIO_PE_SEL 0
#define GPIOA_LEVER1 1 #define GPIOA_LEVER1 1
#define GPIOA_LEVER2 2 #define GPIOA_LEVER2 2
#define GPIOA_PUSH 3 #define GPIOA_PUSH 3
#define GPIOA_RX_SEL 4 //#define GPIO_RX_SEL 4
#define GPIOA_LO_SEL 5 //#define GPIO_LO_SEL 5
#define GPIOA_XP 6 #define GPIOA_XP 6
#define GPIOA_YP 7 #define GPIOA_YP 7
#define GPIOA_MCO 8 #define GPIOA_MCO 8
@ -72,12 +72,17 @@
#define GPIOB_LCD_CS 6 #define GPIOB_LCD_CS 6
#define GPIOB_LCD_CD 7 #define GPIOB_LCD_CD 7
#define GPIOB_I2C1_SCL 8 #define GPIOB_I2C1_SCL 8
#define GPIOB_I2C1_SDA 9 #define GPIO_RF_PWR 9
#define GPIOB_SD_GP2 10 #define GPIO_SPI2_CLK 10
#define GPIOB_SD_CS 11 #define GPIOB_SD_CS 11
#define GPIOB_SPI2_CLK 12 #define GPIO_SPI2_SDO 14
#define GPIOB_SPI2_SDO 13 #define GPIO_SPI2_SDI 15
#define GPIOB_SPI2_SDI 15
// Port C
#define GPIO_PE_SEL 13
#define GPIO_RX_SEL 14
#define GPIO_LO_SEL 15
#define GPIOC_LED 13 #define GPIOC_LED 13
@ -116,12 +121,12 @@
* PA13 - SWDIO (alternate 0). * PA13 - SWDIO (alternate 0).
* PA14 - SWCLK (alternate 0). * PA14 - SWCLK (alternate 0).
*/ */
#define VAL_GPIOA_MODER (PIN_MODE_OUTPUT(GPIOA_PE_SEL) | \ #define VAL_GPIOA_MODER (PIN_MODE_INPUT(0U) | \
PIN_MODE_INPUT(1U) | \ PIN_MODE_INPUT(1U) | \
PIN_MODE_INPUT(2U) | \ PIN_MODE_INPUT(2U) | \
PIN_MODE_INPUT(3U) | \ PIN_MODE_INPUT(3U) | \
PIN_MODE_OUTPUT(GPIOA_RX_SEL) | \ PIN_MODE_INPUT(4U) | \
PIN_MODE_OUTPUT(GPIOA_LO_SEL) | \ PIN_MODE_INPUT(5U) | \
PIN_MODE_ANALOG(GPIOA_XP) | \ PIN_MODE_ANALOG(GPIOA_XP) | \
PIN_MODE_ANALOG(GPIOA_YP) | \ PIN_MODE_ANALOG(GPIOA_YP) | \
PIN_MODE_ALTERNATE(GPIOA_MCO) | \ PIN_MODE_ALTERNATE(GPIOA_MCO) | \
@ -132,7 +137,7 @@
PIN_MODE_ALTERNATE(GPIOA_JTMS) | \ PIN_MODE_ALTERNATE(GPIOA_JTMS) | \
PIN_MODE_ALTERNATE(GPIOA_JTCK) | \ PIN_MODE_ALTERNATE(GPIOA_JTCK) | \
PIN_MODE_OUTPUT(GPIOA_LCD_RESET)) PIN_MODE_OUTPUT(GPIOA_LCD_RESET))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PE_SEL) | \ #define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0U) | \
PIN_OTYPE_PUSHPULL(1U) | \ PIN_OTYPE_PUSHPULL(1U) | \
PIN_OTYPE_PUSHPULL(2U) | \ PIN_OTYPE_PUSHPULL(2U) | \
PIN_OTYPE_PUSHPULL(3U) | \ PIN_OTYPE_PUSHPULL(3U) | \
@ -148,7 +153,7 @@
PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \
PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \
PIN_OTYPE_PUSHPULL(GPIOA_LCD_RESET)) PIN_OTYPE_PUSHPULL(GPIOA_LCD_RESET))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_PE_SEL) | \ #define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(0) | \
PIN_OSPEED_2M(1) | \ PIN_OSPEED_2M(1) | \
PIN_OSPEED_2M(2) | \ PIN_OSPEED_2M(2) | \
PIN_OSPEED_2M(3) | \ PIN_OSPEED_2M(3) | \
@ -164,7 +169,7 @@
PIN_OSPEED_100M(GPIOA_JTMS) | \ PIN_OSPEED_100M(GPIOA_JTMS) | \
PIN_OSPEED_100M(GPIOA_JTCK) | \ PIN_OSPEED_100M(GPIOA_JTCK) | \
PIN_OSPEED_100M(GPIOA_LCD_RESET)) PIN_OSPEED_100M(GPIOA_LCD_RESET))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(GPIOA_PE_SEL) | \ #define VAL_GPIOA_PUPDR ( PIN_PUPDR_PULLDOWN(0) | \
PIN_PUPDR_PULLDOWN(1) | \ PIN_PUPDR_PULLDOWN(1) | \
PIN_PUPDR_PULLDOWN(2) | \ PIN_PUPDR_PULLDOWN(2) | \
PIN_PUPDR_PULLDOWN(3) | \ PIN_PUPDR_PULLDOWN(3) | \
@ -180,7 +185,7 @@
PIN_PUPDR_PULLDOWN(GPIOA_JTMS) | \ PIN_PUPDR_PULLDOWN(GPIOA_JTMS) | \
PIN_PUPDR_PULLDOWN(GPIOA_JTCK) | \ PIN_PUPDR_PULLDOWN(GPIOA_JTCK) | \
PIN_PUPDR_PULLDOWN(GPIOA_LCD_RESET)) PIN_PUPDR_PULLDOWN(GPIOA_LCD_RESET))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PE_SEL) | \ #define VAL_GPIOA_ODR ( PIN_ODR_HIGH(0) | \
PIN_ODR_HIGH(1) | \ PIN_ODR_HIGH(1) | \
PIN_ODR_HIGH(2) | \ PIN_ODR_HIGH(2) | \
PIN_ODR_HIGH(3) | \ PIN_ODR_HIGH(3) | \
@ -196,7 +201,7 @@
PIN_ODR_HIGH(GPIOA_JTMS) | \ PIN_ODR_HIGH(GPIOA_JTMS) | \
PIN_ODR_HIGH(GPIOA_JTCK) | \ PIN_ODR_HIGH(GPIOA_JTCK) | \
PIN_ODR_HIGH(GPIOA_LCD_RESET)) PIN_ODR_HIGH(GPIOA_LCD_RESET))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PE_SEL, 0) | \ #define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \
PIN_AFIO_AF(1, 0) | \ PIN_AFIO_AF(1, 0) | \
PIN_AFIO_AF(2, 0) | \ PIN_AFIO_AF(2, 0) | \
PIN_AFIO_AF(3, 0) | \ PIN_AFIO_AF(3, 0) | \
@ -235,14 +240,14 @@
PIN_MODE_ALTERNATE(GPIOB_SPI_MOSI) | \ PIN_MODE_ALTERNATE(GPIOB_SPI_MOSI) | \
PIN_MODE_OUTPUT(6) | \ PIN_MODE_OUTPUT(6) | \
PIN_MODE_OUTPUT(7) | \ PIN_MODE_OUTPUT(7) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ PIN_MODE_OUTPUT(8) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ PIN_MODE_OUTPUT(GPIO_RF_PWR) | \
PIN_MODE_OUTPUT(10) | \ PIN_MODE_OUTPUT(GPIO_SPI2_CLK) | \
PIN_MODE_OUTPUT(11) | \ PIN_MODE_OUTPUT(11) | \
PIN_MODE_OUTPUT(GPIOB_SPI2_CLK) | \ PIN_MODE_OUTPUT(12) | \
PIN_MODE_INPUT(GPIOB_SPI2_SDO) | \ PIN_MODE_OUTPUT(13) | \
PIN_MODE_ALTERNATE(14) | \ PIN_MODE_INPUT(GPIO_SPI2_SDO) | \
PIN_MODE_OUTPUT(GPIOB_SPI2_SDI)) PIN_MODE_OUTPUT(GPIO_SPI2_SDI))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ #define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
PIN_OTYPE_PUSHPULL(1) | \ PIN_OTYPE_PUSHPULL(1) | \
PIN_OTYPE_PUSHPULL(2) | \ PIN_OTYPE_PUSHPULL(2) | \
@ -251,14 +256,14 @@
PIN_OTYPE_PUSHPULL(5) | \ PIN_OTYPE_PUSHPULL(5) | \
PIN_OTYPE_PUSHPULL(6) | \ PIN_OTYPE_PUSHPULL(6) | \
PIN_OTYPE_PUSHPULL(7) | \ PIN_OTYPE_PUSHPULL(7) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \ PIN_OTYPE_PUSHPULL(8) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \ PIN_OTYPE_PUSHPULL(GPIO_RF_PWR) | \
PIN_OTYPE_PUSHPULL(10) | \ PIN_OTYPE_PUSHPULL(GPIO_SPI2_CLK) | \
PIN_OTYPE_PUSHPULL(11) | \ PIN_OTYPE_PUSHPULL(11) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI2_CLK) | \ PIN_OTYPE_PUSHPULL(12) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SDO) | \ PIN_OTYPE_PUSHPULL(13) | \
PIN_OTYPE_PUSHPULL(14) | \ PIN_OTYPE_PUSHPULL(GPIO_SPI2_SDO) | \
PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SDI)) PIN_OTYPE_PUSHPULL(GPIO_SPI2_SDI))
#define VAL_GPIOB_OSPEEDR (PIN_PUPDR_FLOATING(GPIOB_XN) | \ #define VAL_GPIOB_OSPEEDR (PIN_PUPDR_FLOATING(GPIOB_XN) | \
PIN_PUPDR_FLOATING(GPIOB_YN) | \ PIN_PUPDR_FLOATING(GPIOB_YN) | \
PIN_OSPEED_100M(2) | \ PIN_OSPEED_100M(2) | \
@ -267,14 +272,14 @@
PIN_OSPEED_100M(5) | \ PIN_OSPEED_100M(5) | \
PIN_OSPEED_100M(6) | \ PIN_OSPEED_100M(6) | \
PIN_OSPEED_100M(7) | \ PIN_OSPEED_100M(7) | \
PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ PIN_OSPEED_100M(8) | \
PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ PIN_OSPEED_100M(9) | \
PIN_OSPEED_100M(10) | \ PIN_OSPEED_100M(10) | \
PIN_OSPEED_100M(11) | \ PIN_OSPEED_100M(11) | \
PIN_OSPEED_100M(GPIOB_SPI2_CLK) | \ PIN_OSPEED_100M(12) | \
PIN_OSPEED_100M(GPIOB_SPI2_SDO) | \ PIN_OSPEED_100M(13) | \
PIN_OSPEED_100M(14) | \ PIN_OSPEED_100M(14) | \
PIN_OSPEED_100M(GPIOB_SPI2_SDI)) PIN_OSPEED_100M(15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(0) | \ #define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(0) | \
PIN_PUPDR_PULLUP(1) | \ PIN_PUPDR_PULLUP(1) | \
PIN_PUPDR_PULLUP(2) | \ PIN_PUPDR_PULLUP(2) | \
@ -283,14 +288,14 @@
PIN_PUPDR_PULLUP(5) | \ PIN_PUPDR_PULLUP(5) | \
PIN_PUPDR_PULLUP(6) | \ PIN_PUPDR_PULLUP(6) | \
PIN_PUPDR_PULLUP(7) | \ PIN_PUPDR_PULLUP(7) | \
PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ PIN_PUPDR_PULLUP(8) | \
PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ PIN_PUPDR_PULLUP(9) | \
PIN_PUPDR_PULLUP(10) | \ PIN_PUPDR_PULLUP(10) | \
PIN_PUPDR_PULLUP(11) | \ PIN_PUPDR_PULLUP(11) | \
PIN_PUPDR_PULLUP(GPIOB_SPI2_CLK) | \ PIN_PUPDR_PULLUP(12) | \
PIN_PUPDR_PULLUP(GPIOB_SPI2_SDO) | \ PIN_PUPDR_PULLUP(13) | \
PIN_PUPDR_PULLUP(14) | \ PIN_PUPDR_PULLUP(14) | \
PIN_PUPDR_PULLUP(GPIOB_SPI2_SDI)) PIN_PUPDR_PULLUP(14))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \ #define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \
PIN_ODR_HIGH(1) | \ PIN_ODR_HIGH(1) | \
PIN_ODR_HIGH(2) | \ PIN_ODR_HIGH(2) | \
@ -299,14 +304,14 @@
PIN_ODR_HIGH(5) | \ PIN_ODR_HIGH(5) | \
PIN_ODR_HIGH(6) | \ PIN_ODR_HIGH(6) | \
PIN_ODR_HIGH(7) | \ PIN_ODR_HIGH(7) | \
PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ PIN_ODR_HIGH(8) | \
PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ PIN_ODR_HIGH(9) | \
PIN_ODR_HIGH(10) | \ PIN_ODR_HIGH(10) | \
PIN_ODR_HIGH(11) | \ PIN_ODR_HIGH(11) | \
PIN_ODR_HIGH(GPIOB_SPI2_CLK) | \ PIN_ODR_HIGH(12) | \
PIN_ODR_HIGH(GPIOB_SPI2_SDO) | \ PIN_ODR_HIGH(13) | \
PIN_ODR_HIGH(14) | \ PIN_ODR_HIGH(14) | \
PIN_ODR_HIGH(GPIOB_SPI2_SDI)) PIN_ODR_HIGH(15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \ #define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \
PIN_AFIO_AF(1, 0) | \ PIN_AFIO_AF(1, 0) | \
PIN_AFIO_AF(2, 0) | \ PIN_AFIO_AF(2, 0) | \
@ -315,20 +320,21 @@
PIN_AFIO_AF(GPIOB_SPI_MISO, 0) | \ PIN_AFIO_AF(GPIOB_SPI_MISO, 0) | \
PIN_AFIO_AF(6, 0) | \ PIN_AFIO_AF(6, 0) | \
PIN_AFIO_AF(7, 0)) PIN_AFIO_AF(7, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 1) | \ #define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 1) | \
PIN_AFIO_AF(GPIOB_I2C1_SDA, 1) | \ PIN_AFIO_AF(9, 1) | \
PIN_AFIO_AF(10, 0) | \ PIN_AFIO_AF(10, 0) | \
PIN_AFIO_AF(11, 0) | \ PIN_AFIO_AF(11, 0) | \
PIN_AFIO_AF(GPIOB_SPI2_CLK, 0) | \ PIN_AFIO_AF(12, 0) | \
PIN_AFIO_AF(GPIOB_SPI2_SDO, 0) | \ PIN_AFIO_AF(13, 0) | \
PIN_AFIO_AF(14, 0) | \ PIN_AFIO_AF(14, 0) | \
PIN_AFIO_AF(GPIOB_SPI2_SDI, 0)) PIN_AFIO_AF(15, 0))
/* /*
* GPIOC setup: * GPIOC setup:
* *
* PC13 - LED (output pushpull maximum). * PC13 - LED (output pushpull maximum).
* PC14 - USB DISC (output pushpull maximum). * PC14 - USB DISC (output pushpull maximum).
*/ */
#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \ #define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \
PIN_MODE_INPUT(1) | \ PIN_MODE_INPUT(1) | \
PIN_MODE_INPUT(2) | \ PIN_MODE_INPUT(2) | \
@ -342,9 +348,9 @@
PIN_MODE_INPUT(10) | \ PIN_MODE_INPUT(10) | \
PIN_MODE_INPUT(11) | \ PIN_MODE_INPUT(11) | \
PIN_MODE_INPUT(12) | \ PIN_MODE_INPUT(12) | \
PIN_MODE_OUTPUT(GPIOC_LED) | \ PIN_MODE_OUTPUT(GPIO_PE_SEL) | \
PIN_MODE_INPUT(14) | \ PIN_MODE_OUTPUT(GPIO_RX_SEL) | \
PIN_MODE_INPUT(15)) PIN_MODE_OUTPUT(GPIO_LO_SEL))
#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ #define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
PIN_OTYPE_PUSHPULL(1) | \ PIN_OTYPE_PUSHPULL(1) | \
PIN_OTYPE_PUSHPULL(2) | \ PIN_OTYPE_PUSHPULL(2) | \
@ -358,7 +364,7 @@
PIN_OTYPE_PUSHPULL(10) | \ PIN_OTYPE_PUSHPULL(10) | \
PIN_OTYPE_PUSHPULL(11) | \ PIN_OTYPE_PUSHPULL(11) | \
PIN_OTYPE_PUSHPULL(12) | \ PIN_OTYPE_PUSHPULL(12) | \
PIN_OTYPE_PUSHPULL(GPIOC_LED) | \ PIN_OTYPE_PUSHPULL(13) | \
PIN_OTYPE_PUSHPULL(14) | \ PIN_OTYPE_PUSHPULL(14) | \
PIN_OTYPE_PUSHPULL(15)) PIN_OTYPE_PUSHPULL(15))
#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) | \ #define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) | \
@ -374,7 +380,7 @@
PIN_OSPEED_100M(10) | \ PIN_OSPEED_100M(10) | \
PIN_OSPEED_100M(11) | \ PIN_OSPEED_100M(11) | \
PIN_OSPEED_100M(12) | \ PIN_OSPEED_100M(12) | \
PIN_OSPEED_100M(GPIOC_LED) | \ PIN_OSPEED_100M(13) | \
PIN_OSPEED_100M(14) | \ PIN_OSPEED_100M(14) | \
PIN_OSPEED_100M(15)) PIN_OSPEED_100M(15))
#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(0) | \ #define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(0) | \
@ -390,8 +396,8 @@
PIN_PUPDR_PULLUP(10) | \ PIN_PUPDR_PULLUP(10) | \
PIN_PUPDR_PULLUP(11) | \ PIN_PUPDR_PULLUP(11) | \
PIN_PUPDR_PULLUP(12) | \ PIN_PUPDR_PULLUP(12) | \
PIN_PUPDR_FLOATING(GPIOC_LED) | \ PIN_PUPDR_PULLUP(13) | \
PIN_PUPDR_FLOATING(14) | \ PIN_PUPDR_PULLUP(14) | \
PIN_PUPDR_PULLUP(15)) PIN_PUPDR_PULLUP(15))
#define VAL_GPIOC_ODR (PIN_ODR_HIGH(0) | \ #define VAL_GPIOC_ODR (PIN_ODR_HIGH(0) | \
PIN_ODR_HIGH(1) | \ PIN_ODR_HIGH(1) | \
@ -406,7 +412,7 @@
PIN_ODR_HIGH(10) | \ PIN_ODR_HIGH(10) | \
PIN_ODR_HIGH(11) | \ PIN_ODR_HIGH(11) | \
PIN_ODR_HIGH(12) | \ PIN_ODR_HIGH(12) | \
PIN_ODR_HIGH(GPIOC_LED) | \ PIN_ODR_HIGH(13) | \
PIN_ODR_HIGH(14) | \ PIN_ODR_HIGH(14) | \
PIN_ODR_HIGH(15)) PIN_ODR_HIGH(15))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) | \ #define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) | \
@ -422,7 +428,7 @@
PIN_AFIO_AF(10, 0) | \ PIN_AFIO_AF(10, 0) | \
PIN_AFIO_AF(11, 0) | \ PIN_AFIO_AF(11, 0) | \
PIN_AFIO_AF(12, 0) | \ PIN_AFIO_AF(12, 0) | \
PIN_AFIO_AF(GPIOC_LED, 0) | \ PIN_AFIO_AF(13, 0) | \
PIN_AFIO_AF(14, 0) | \ PIN_AFIO_AF(14, 0) | \
PIN_AFIO_AF(15, 0)) PIN_AFIO_AF(15, 0))

51
si4432.c
Unescape View File

@ -22,21 +22,24 @@
#include "si4432.h" #include "si4432.h"
#define CS_SI0_HIGH palSetPad(GPIOA, GPIOA_RX_SEL) #define CS_SI0_HIGH palSetPad(GPIOC, GPIO_RX_SEL)
#define CS_SI1_HIGH palSetPad(GPIOA, GPIOA_LO_SEL) #define CS_SI1_HIGH palSetPad(GPIOC, GPIO_LO_SEL)
#define CS_PE_HIGH palSetPad(GPIOA, GPIOA_PE_SEL) #define CS_PE_HIGH palSetPad(GPIOC, GPIO_PE_SEL)
#define CS_SI0_LOW palClearPad(GPIOA, GPIOA_RX_SEL) #define RF_POWER_HIGH palSetPad(GPIOC, GPIO_RF_PWR)
#define CS_SI1_LOW palClearPad(GPIOA, GPIOA_LO_SEL)
#define CS_PE_LOW palClearPad(GPIOA, GPIOA_PE_SEL)
#define SPI2_CLK_HIGH palSetPad(GPIOB, GPIOB_SPI2_CLK)
#define SPI2_CLK_LOW palClearPad(GPIOB, GPIOB_SPI2_CLK)
#define SPI2_SDI_HIGH palSetPad(GPIOB, GPIOB_SPI2_SDI) #define CS_SI0_LOW palClearPad(GPIOC, GPIO_RX_SEL)
#define SPI2_SDI_LOW palClearPad(GPIOB, GPIOB_SPI2_SDI) #define CS_SI1_LOW palClearPad(GPIOC, GPIO_LO_SEL)
#define CS_PE_LOW palClearPad(GPIOC, GPIO_PE_SEL)
#define SPI2_SDO ((palReadPort(GPIOB) & (1<<GPIOB_SPI2_SDO))?1:0) #define SPI2_CLK_HIGH palSetPad(GPIOB, GPIO_SPI2_CLK)
#define SPI2_CLK_LOW palClearPad(GPIOB, GPIO_SPI2_CLK)
#define SPI2_SDI_HIGH palSetPad(GPIOB, GPIO_SPI2_SDI)
#define SPI2_SDI_LOW palClearPad(GPIOB, GPIO_SPI2_SDI)
#define SPI2_SDO ((palReadPort(GPIOB) & (1<<GPIO_SPI2_SDO))?1:0)
//#define MAXLOG 1024 //#define MAXLOG 1024
@ -72,7 +75,7 @@ uint8_t shiftIn(void) {
return value; return value;
} }
const int SI_nSEL[3] = { GPIOA_RX_SEL, GPIOA_LO_SEL, 0}; // #3 is dummy!!!!!! const int SI_nSEL[3] = { GPIO_RX_SEL, GPIO_LO_SEL, 0}; // #3 is dummy!!!!!!
volatile int SI4432_Sel = 0; // currently selected SI4432 volatile int SI4432_Sel = 0; // currently selected SI4432
// volatile int SI4432_guard = 0; // volatile int SI4432_guard = 0;
@ -85,12 +88,12 @@ void SI4432_Write_Byte(byte ADR, byte DATA )
// while(1) ; // while(1) ;
// SI4432_guard = 1; // SI4432_guard = 1;
SPI2_CLK_LOW; SPI2_CLK_LOW;
palClearPad(GPIOA, SI_nSEL[SI4432_Sel]); palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
// chThdSleepMicroseconds(SELECT_DELAY); // chThdSleepMicroseconds(SELECT_DELAY);
ADR |= 0x80 ; // RW = 1 ADR |= 0x80 ; // RW = 1
shiftOut( ADR ); shiftOut( ADR );
shiftOut( DATA ); shiftOut( DATA );
palSetPad(GPIOA, SI_nSEL[SI4432_Sel]); palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
// SI4432_guard = 0; // SI4432_guard = 0;
} }
@ -100,14 +103,14 @@ void SI4432_Write_3_Byte(byte ADR, byte DATA1, byte DATA2, byte DATA3 )
// while(1) ; // while(1) ;
// SI4432_guard = 1; // SI4432_guard = 1;
SPI2_CLK_LOW; SPI2_CLK_LOW;
palClearPad(GPIOA, SI_nSEL[SI4432_Sel]); palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
// chThdSleepMicroseconds(SELECT_DELAY); // chThdSleepMicroseconds(SELECT_DELAY);
ADR |= 0x80 ; // RW = 1 ADR |= 0x80 ; // RW = 1
shiftOut( ADR ); shiftOut( ADR );
shiftOut( DATA1 ); shiftOut( DATA1 );
shiftOut( DATA2 ); shiftOut( DATA2 );
shiftOut( DATA3 ); shiftOut( DATA3 );
palSetPad(GPIOA, SI_nSEL[SI4432_Sel]); palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
// SI4432_guard = 0; // SI4432_guard = 0;
} }
@ -118,10 +121,10 @@ byte SI4432_Read_Byte( byte ADR )
// while(1) ; // while(1) ;
// SI4432_guard = 1; // SI4432_guard = 1;
SPI2_CLK_LOW; SPI2_CLK_LOW;
palClearPad(GPIOA, SI_nSEL[SI4432_Sel]); palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
shiftOut( ADR ); shiftOut( ADR );
DATA = shiftIn(); DATA = shiftIn();
palSetPad(GPIOA, SI_nSEL[SI4432_Sel]); palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
// SI4432_guard = 0; // SI4432_guard = 0;
return DATA ; return DATA ;
} }
@ -132,7 +135,6 @@ void SI4432_Reset(void)
{ {
int count = 0; int count = 0;
// always perform a system reset (don't send 0x87) // always perform a system reset (don't send 0x87)
again:
SI4432_Write_Byte( 0x07, 0x80); SI4432_Write_Byte( 0x07, 0x80);
chThdSleepMilliseconds(25); chThdSleepMilliseconds(25);
// wait for chiprdy bit // wait for chiprdy bit
@ -147,7 +149,6 @@ void SI4432_Transmit(int d)
SI4432_Write_Byte(0x6D, (byte) (0x1C+d)); SI4432_Write_Byte(0x6D, (byte) (0x1C+d));
if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 2) if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 2)
return; // Already in transmit mode return; // Already in transmit mode
again:
chThdSleepMilliseconds(20); chThdSleepMilliseconds(20);
SI4432_Write_Byte( 0x07, 0x0b); SI4432_Write_Byte( 0x07, 0x0b);
chThdSleepMilliseconds(20); chThdSleepMilliseconds(20);
@ -161,7 +162,6 @@ void SI4432_Receive(void)
int count = 0; int count = 0;
if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 1) if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 1)
return; // Already in receive mode return; // Already in receive mode
again:
SI4432_Write_Byte( 0x07, 0x07); SI4432_Write_Byte( 0x07, 0x07);
chThdSleepMilliseconds(10); chThdSleepMilliseconds(10);
while (count++ < 100 && ( SI4432_Read_Byte ( 0x02 ) & 0x03 ) != 1) { while (count++ < 100 && ( SI4432_Read_Byte ( 0x02 ) & 0x03 ) != 1) {
@ -188,7 +188,7 @@ static short RBW_choices[] = { // Each triple is: ndec, fils, WISH*10
float SI4432_SET_RBW(float w) { float SI4432_SET_RBW(float w) {
uint8_t dwn3=0; uint8_t dwn3=0;
uint32_t WISH = (uint32_t)(w * 10.0); int32_t WISH = (uint32_t)(w * 10.0);
uint8_t ndec, fils, i; uint8_t ndec, fils, i;
if (WISH > 6207) WISH=6207; // Final value in RBW_choices[] if (WISH > 6207) WISH=6207; // Final value in RBW_choices[]
if (WISH > 1379) dwn3 = 1 ; if (WISH > 1379) dwn3 = 1 ;
@ -231,6 +231,7 @@ int settingSpeed = 0;
float SI4432_RSSI(uint32_t i, int s) float SI4432_RSSI(uint32_t i, int s)
{ {
(void) i;
int RSSI_RAW; int RSSI_RAW;
// SEE DATASHEET PAGE 61 // SEE DATASHEET PAGE 61
#ifdef USE_SI4463 #ifdef USE_SI4463
@ -252,7 +253,7 @@ float SI4432_RSSI(uint32_t i, int s)
} }
void SI4432_Sub_Init() void SI4432_Sub_Init(void)
{ {
SI4432_Reset(); SI4432_Reset();
SI4432_Write_Byte(0x05, 0x0); SI4432_Write_Byte(0x05, 0x0);
@ -311,8 +312,10 @@ void SI4432_Sub_Init()
void SI4432_Init() void SI4432_Init()
{ {
RF_POWER_HIGH; // Power the RF part
chThdSleepMilliseconds(25);
//DebugLine("IO set"); //DebugLine("IO set");
SI4432_Sel = 0; SI4432_Sel = 0;
SI4432_Sub_Init(); SI4432_Sub_Init();

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