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@ -876,9 +876,11 @@ float Simulated_SI4432_RSSI(uint32_t i, int s)
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#define CS_ADF1_LOW palClearLine(LINE_LO_SEL)
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//uint32_t registers[6] = {0x320000, 0x8008011, 0x4E42, 0x4B3,0x8C803C , 0x580005} ; //25 MHz ref
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#ifdef TINYSA4_PROTO
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uint32_t registers[6] = {0xA00000, 0x8000011, 0x4042, 0x4B3,0xDC003C , 0x580005} ; //10 MHz ref
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#else
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uint32_t registers[6] = {0xA00000, 0x8000011, 0x4E42, 0x4B3,0xDC003C , 0x580005} ; //10 MHz ref
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#endif
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int debug = 0;
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ioline_t ADF4351_LE[2] = { LINE_LO_SEL, LINE_LO_SEL};
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//int ADF4351_Mux = 7;
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@ -1396,7 +1398,7 @@ static uint8_t gpio_state[4] = { 7,8,0,0 };
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void SI4463_refresh_gpio(void)
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{
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#ifndef TINYSA4_PROTO
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#ifndef TINYSA4_PROTO // Force clock to max frequency for ADF
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uint8_t data[] =
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{
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0x11, 0x00, 0x01, 0x01, 0x40 // GLOBAL_CLK_CFG Enable divided clock
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@ -1565,10 +1567,7 @@ void set_calibration_freq(int ref)
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#endif
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if (ref >= 0) {
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uint8_t data[8] = {
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0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 // GPIO_PIN_CFG GPIO 0 input ,1 CTS, clock div out
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};
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SI4463_do_api(data, 8, NULL, 0);
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SI4463_set_gpio(0, 7); // GPIO 0 dic clock out
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uint8_t data2[5] = {
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0x11, 0x00, 0x01, 0x01, 0x40 // GLOBAL_CLK_CFG Clock config
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@ -1576,11 +1575,7 @@ void set_calibration_freq(int ref)
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data2[4] |= ref<<3;
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SI4463_do_api(data2, 5, NULL, 0);
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} else {
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uint8_t data[8] = {
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0x13, 0x01, 0x08, 0x01, 0x12, 0x00, 0x00, 0x00 // GPIO_PIN_CFG GLOBAL_CLK_CFG GPIO 0,1 CTS, GPIO 2 clock div out
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};
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SI4463_do_api(data, 8, NULL, 0);
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SI4463_set_gpio(0, 1); // stop clock out
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}
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}
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@ -2324,9 +2319,9 @@ void enable_extra_lna(int s)
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static int old_extra_lna = -1;
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if (s != old_extra_lna) {
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if (s)
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palClearLine(LINE_LNA); // Inverted logic!!!
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else
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palSetLine(LINE_LNA);
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else
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palClearLine(LINE_LNA);
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old_extra_lna = s;
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}
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#else
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@ -2340,9 +2335,9 @@ void enable_ultra(int s)
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static int old_ultra = -1;
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if (s != old_ultra) {
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if (s)
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palSetLine(LINE_ULTRA);
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else
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palClearLine(LINE_ULTRA);
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else
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palSetLine(LINE_ULTRA);
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old_ultra = s;
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}
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#else
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