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@ -22,32 +22,34 @@
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#ifdef __SI5351__
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#include "si5351.h"
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inline int palReadLine(uint32_t line) {
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return ( palReadPort(PAL_PORT(line)) & (1<<PAL_PAD(line)) )
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}
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//inline int palReadLine(uint32_t line) {
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// return ( palReadPort(PAL_PORT(line)) & (1<<PAL_PAD(line)) )
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//}
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char pll_lock_failed = 0;
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int si5351_available = false;
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/*
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* Software i2c bus
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*/
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#define I2C_DELAY my_microsecond_delay(10);
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#define I2C_DELAY my_microsecond_delay(20);
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static inline void scl_low(void) {
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palClearLine(LINE_PB13);
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palClearLine(LINE_SCL);
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I2C_DELAY;
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}
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static inline void scl_high(void) {
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palSetLine(LINE_PB13);
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palSetLine(LINE_SCL);
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I2C_DELAY;
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}
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static inline void sda_low(void) {
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palClearLine(LINE_PB14);
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palClearLine(LINE_SDA);
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I2C_DELAY;
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}
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static inline void sda_high(void) {
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palSetLine(LINE_PB14);
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palSetLine(LINE_SDA);
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I2C_DELAY;
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}
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@ -68,7 +70,7 @@ inline int palReadLine(uint32_t line) {
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while(bits--) {
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scl_high();
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ret<<= 1;
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if (palReadLine(LINE_PB14)) ret|=1;
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if (palReadLine(LINE_SDA)) ret|=1;
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scl_low();
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}
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// soft_i2c_sda.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, LOW); // Output low
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@ -91,12 +93,14 @@ inline int palReadLine(uint32_t line) {
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return ret;
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}
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void i2c_init() {
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void i2c_init(void) {
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// soft_i2c_clk.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL);
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// soft_i2c_sda.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL);
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i2c_begin();
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i2c_end();
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}
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#define I2C_WRITE 0
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#define I2C_READ 1
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bool i2c_probe(uint8_t devAddr) {
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i2c_begin();
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@ -162,7 +166,7 @@ static bool si5351_read(uint8_t reg, uint8_t* buf)
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int v = i2c_read(addr, reg);
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if (v < 0)
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return false;
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*buf = (uint8_t) v
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*buf = (uint8_t) v;
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return true;
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}
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@ -176,21 +180,21 @@ static bool si5351_write(uint8_t reg, uint8_t dat)
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static bool si5351_bulk_write(const uint8_t *buf, int len)
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{
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int addr = SI5351_I2C_ADDR>>1;
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int s = i2c_write_buf(addr, buf, len);
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return s > 0;
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int s = i2c_write_buf(addr, (uint8_t* )buf, len);
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return s >= 0;
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}
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// register addr, length, data, ...
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static const uint8_t si5351_configs[] = {
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff,
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4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN,
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2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF,
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// setup PLL (26MHz * 32 = 832MHz, 32/2-2=14)
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9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0,
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// 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF,
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// setup PLL (30MHz * 30 = 900MHz, 30/2-2=13)
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9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 13, 0, /*P3/P2*/0, 0, 0,
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// RESET PLL
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2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B,
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// setup multisynth (832MHz / 104 = 8MHz, 104/2-2=50)
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9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0,
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// setup multisynth (900MHz / 30 = 30MHz, 30/2-2=13)
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9, SI5351_REG_42_MULTISYNTH0, /*P3*/0, 1, /*P1*/0, 13, 0, /*P2|P3*/0, 0, 0,
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#ifdef __ENABLE_CLK2__
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2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE,
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0,
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@ -216,7 +220,7 @@ static bool si5351_wait_ready(void)
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return false;
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}
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#if 0
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#if 1
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static void si5351_wait_pll_lock(void)
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{
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systime_t start = chVTGetSystemTime();
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@ -242,6 +246,7 @@ bool si5351_init(void)
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{
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if (!si5351_wait_ready())
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return false;
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my_microsecond_delay(200);
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const uint8_t *p = si5351_configs;
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while (*p) {
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uint8_t len = *p++;
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@ -249,6 +254,9 @@ bool si5351_init(void)
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return false;
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p += len;
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}
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si5351_wait_pll_lock();
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if (pll_lock_failed)
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return false;
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return true;
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}
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@ -421,8 +429,8 @@ static uint32_t gcd(uint32_t x, uint32_t y)
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return x;
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}
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#define XTALFREQ 26000000L
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#define PLL_N 32
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#define XTALFREQ 30000000L
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#define PLL_N 30
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#define PLLFREQ (XTALFREQ * PLL_N)
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static void si5351_set_frequency_fixedpll(
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@ -470,7 +478,7 @@ static void si5351_set_frequency_fixeddiv(
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void si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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{
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if (freq <= 100000000) {
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si5351_setupPLL(SI5351_PLL_B, 32, 0, 1);
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si5351_setupPLL(SI5351_PLL_B, 30, 0, 1);
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si5351_set_frequency_fixedpll(channel, SI5351_PLL_B, PLLFREQ, freq, SI5351_R_DIV_1, drive_strength);
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} else if (freq < 150000000) {
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_B, freq, 6, drive_strength);
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@ -531,7 +539,7 @@ int si5351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_st
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// fractional divider mode. only PLL A is used.
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if (current_band == 1 || current_band == 2){
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si5351_reset_pll();
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si5351_setupPLL(SI5351_PLL_A, 32, 0, 1);
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si5351_setupPLL(SI5351_PLL_A, PLL_N, 0, 1);
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}
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if (rdiv == SI5351_R_DIV_8) {
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erikkaashoek
4 years ago