diff --git a/NANOVNA_STM32_F303/board.h b/NANOVNA_STM32_F303/board.h index 909867b..0469adf 100644 --- a/NANOVNA_STM32_F303/board.h +++ b/NANOVNA_STM32_F303/board.h @@ -115,8 +115,12 @@ #endif #define GPIO_PB13 13 #define LINE_PB13 PAL_LINE(GPIOB, GPIO_PB13) +#define GPIO_SCL 13 +#define LINE_SCL PAL_LINE(GPIOB, GPIO_PB13) #define GPIO_PB14 14 #define LINE_PB14 PAL_LINE(GPIOB, GPIO_PB14) +#define GPIO_SDA 14 +#define LINE_SDA PAL_LINE(GPIOB, GPIO_PB14) #define GPIO_ULTRA 15 #define LINE_ULTRA PAL_LINE(GPIOB,GPIO_ULTRA) @@ -299,8 +303,8 @@ PIN_OTYPE_PUSHPULL(10) | \ PIN_OTYPE_PUSHPULL(11) | \ PIN_OTYPE_PUSHPULL(12) | \ - PIN_OTYPE_PUSHPULL(13) | \ - PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_OPENDRAIN(13) | \ + PIN_OTYPE_OPENDRAIN(14) | \ PIN_OTYPE_PUSHPULL(15)) #define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_XN) | \ PIN_OSPEED_100M(GPIOB_YN) | \ diff --git a/main.c b/main.c index 3c8b38f..95e1321 100644 --- a/main.c +++ b/main.c @@ -913,7 +913,7 @@ config_t config = { .vbat_offset = 220, .frequency_IF1 = DEFAULT_IF, .frequency_IF2 = 0, - .ultra_threshold = 800000000, + .ultra_threshold = 0, .low_level_offset = 100.0, // Uncalibrated .high_level_offset = 100, // Uncalibrated .lna_level_offset = 100, @@ -929,10 +929,10 @@ config_t config = { }, .correction_value = { - { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // low in - { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // lna in - { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +3.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // low ultra in - { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +3.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // lna ultra in + { 10.5, +3, +1 , -0.1, 0, 0, +1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // low in + { 10.5, +3, +1 , -0.1, 0, 0, +1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // lna in + { 10.5, +3, +1 , -0.1, 0, 0, +1.1, +1.5, +1.8, +3.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // low ultra in + { 10.5, +3, +1 , -0.1, 0, 0, +1.1, +1.5, +1.8, +3.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // lna ultra in { 11.5, 7, 6, 3.5, 1.5, 0.5, -0.2, 0, 0, -0.5, +1.5, +2, +4, +6.5, +9, +13, +13, +13, +13, +13, }, // low out }, .setting_frequency_30mhz = 30000000ULL * FREQ_MULTIPLIER, @@ -1075,8 +1075,11 @@ VNA_SHELL_FUNCTION(cmd_hop) } } else step = 1; - - pause_sweep(); + int old_sweep = sweep_mode; + if (old_sweep & SWEEP_ENABLE) + pause_sweep(); + else + dirty = true; // Output data after if set (faster data recive) uint16_t mask = 3; if (argc == 4) { @@ -1092,7 +1095,6 @@ VNA_SHELL_FUNCTION(cmd_hop) shell_printf("frequency range is invalid\r\n"); return; } - if (mask) { int old_vbwSteps = vbwSteps; // vbwSteps = 1; @@ -1106,7 +1108,8 @@ VNA_SHELL_FUNCTION(cmd_hop) } vbwSteps = old_vbwSteps; } - resume_sweep(); + if (old_sweep & SWEEP_ENABLE) + resume_sweep(); } #endif diff --git a/nanovna.h b/nanovna.h index 28d8d75..7931088 100644 --- a/nanovna.h +++ b/nanovna.h @@ -96,6 +96,9 @@ #define __WAIT_CTS_WHILE_SLEEPING__ #define __MARKER_CACHE__ #define TINYSA4_4 +#ifdef TINYSA4_4 +#define __SI5351__ +#endif //#define __FFT_VBW__ //#define __FFT_DECONV__ #else diff --git a/sa_core.c b/sa_core.c index c61698e..872d585 100644 --- a/sa_core.c +++ b/sa_core.c @@ -1629,8 +1629,8 @@ static const struct { { 8500, 150, 50, 400, -90, 0.7}, { 6000, 150, 50, 300, -95, 0.8}, { 3000, 150, 50, 200, -95, 1.3}, - { 1000, 170, 100, 100, -105, 0.3}, - { 300, 300, 120, 100, -110, 0.7}, + { 1000, 300, 100, 100, -105, 0.3}, + { 300, 400, 120, 100, -110, 0.7}, { 100, 700, 120, 100, -115, 0.5}, { 30, 1600, 300, 100, -120, 0.7}, { 10, 4000, 600, 100, -122, 1.1}, @@ -3642,6 +3642,49 @@ again: // Spur redu #define TCXO 30000000 #define TXCO_DIV3 10000000 +#ifdef __SI5351__ + if (si5351_available) { + if (setting.R == 0) { + setting.increased_R = false; + if (setting.mode == M_GENLOW) { + if (local_modulo == 0) ADF4351_modulo(1000); + ADF4350_shift_ref(false); + ADF4351_R_counter(3); + } else if (lf > 8000000 && MODE_INPUT(setting.mode)) { + if (local_modulo == 0) ADF4351_modulo(4000); + + freq_t tf = ((lf + actual_rbw_x10*200) / TXCO_DIV3) * TXCO_DIV3; + if (tf + actual_rbw_x10*200 >= lf && tf < lf + actual_rbw_x10*200) { // 10MHz + ADF4350_shift_ref(true); + } else { + ADF4350_shift_ref(false); + } + } + if (get_sweep_frequency(ST_SPAN)<5000000) { // When scanning less then 5MHz + if (actual_rbw_x10 <= 3000) { + setting.increased_R = true; + freq_t tf = ((lf + actual_rbw_x10*1000) / TXCO_DIV3) * TXCO_DIV3; + if (tf + actual_rbw_x10*100 >= lf && tf < lf + actual_rbw_x10*100) // 10MHz + ADF4351_R_counter(4); // To avoid PLL Loop shoulders at multiple of 10MHz + else + ADF4351_R_counter(3); // To avoid PLL Loop shoulders + } else + ADF4351_R_counter(1); + } else + ADF4351_R_counter(1); + + } else { + freq_t tf = ((lf + actual_rbw_x10*200) / TXCO_DIV3) * TXCO_DIV3; + if (tf + actual_rbw_x10*200 >= lf && tf < lf + actual_rbw_x10*200) { // 30MHz + ADF4350_shift_ref(true); + } else { + ADF4350_shift_ref(false); + } + ADF4351_R_counter(setting.R); + } + } else +#endif + { if (setting.R == 0) { setting.increased_R = false; if (setting.mode == M_GENLOW) { @@ -3700,6 +3743,7 @@ again: // Spur redu } else { ADF4351_R_counter(setting.R); } + } #endif // __ADF4351__ #if 0 freq_t target_f; diff --git a/si4432.h b/si4432.h index 656b5b3..7edfa81 100644 --- a/si4432.h +++ b/si4432.h @@ -173,9 +173,11 @@ void ADF4351_enable(int p); void ADF4351_enable_aux_out(int p); void ADF4351_enable_out(int p); int ADF4351_locked(void); +void ADF4350_shift_ref(int f); void ADF4351_enable(int s); void ADF4351_enable_aux_out(int s); +extern int si5351_available; #endif #ifdef __SI4463__ diff --git a/si4468.c b/si4468.c index 92f26ba..59dd77e 100644 --- a/si4468.c +++ b/si4468.c @@ -259,7 +259,7 @@ bool PE4302_Write_Byte(unsigned char DATA ) #define maskedWrite(reg, bit, mask, value) (reg) &= ~(((uint32_t)mask) << (bit)); (reg) |= ((((uint32_t) (value)) & ((uint32_t)mask)) << (bit)); - +freq_t local_setting_frequency_30mhz_x100 = 3000000000; #define CS_ADF0_HIGH {palSetLine(LINE_LO_SEL);ADF_CS_DELAY;} #define CS_ADF1_HIGH {ADF_CS_DELAY;palSetLine(LINE_LO_SEL);} @@ -295,11 +295,26 @@ int64_t int old_R = 0; +#ifdef __SI5351__ +#include "si5351.h" +#else +int si5351_available = false; +#endif + + void ADF4351_Setup(void) { // palSetPadMode(GPIOA, 1, PAL_MODE_OUTPUT_PUSHPULL ); // palSetPadMode(GPIOA, 2, PAL_MODE_OUTPUT_PUSHPULL ); + + local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz; +#ifdef __SI5351__ + si5351_available = si5351_init(); + if (si5351_available) + si5351_set_frequency(0, 29999000, 0); +#endif + // SPI3_CLK_HIGH; // SPI3_SDI_HIGH; CS_ADF0_HIGH; @@ -415,10 +430,9 @@ void ADF4351_R_counter(int R) } if (R<1) return; - bitWrite(registers[2], 25, dbl); // Reference doubler for (int channel=0; channel < 6; channel++) { - PFDRFout[channel] = (config.setting_frequency_30mhz * (dbl?2:1)) / R; + PFDRFout[channel] = (local_setting_frequency_30mhz_x100 * (dbl?2:1)) / R; } clear_frequency_cache(); // When R changes the possible frequencies will change maskedWrite(registers[2],14, 0x3FF, R); @@ -430,9 +444,27 @@ void ADF4351_R_counter(int R) void ADF4351_recalculate_PFDRFout(void){ int local_r = old_R; old_R = -1; +#ifdef __SI5351__ + if (si5351_available) + si5351_set_frequency(0, local_setting_frequency_30mhz_x100/100, 0); +#endif ADF4351_R_counter(local_r); } +#ifdef __SI5351__ +static int shifted = -2; +void ADF4350_shift_ref(int f) { + if (f == shifted) + return; + shifted = f; + if (f) + local_setting_frequency_30mhz_x100 = 2999000000; + else + local_setting_frequency_30mhz_x100 = 3000000000; + ADF4351_recalculate_PFDRFout(); +} +#endif + void ADF4351_mux(int R) { maskedWrite(registers[2],26, 0x7, R); @@ -1703,10 +1735,10 @@ freq_t SI4463_set_freq(freq_t freq) si_set_offset(0); SI4463_offset_active = false; } - uint32_t R = (freq * output_divider) / (Npresc ? 2*config.setting_frequency_30mhz : 4*config.setting_frequency_30mhz) - 1; // R between 0x00 and 0x7f (127) + uint32_t R = (freq * output_divider) / (Npresc ? 2*local_setting_frequency_30mhz_x100 : 4*local_setting_frequency_30mhz_x100) - 1; // R between 0x00 and 0x7f (127) uint64_t MOD = 524288; // = 2^19 - uint32_t F = ((freq * output_divider*MOD) / (Npresc ? 2*config.setting_frequency_30mhz : 4*config.setting_frequency_30mhz)) - R*MOD; - freq_t actual_freq = (R*MOD + F) * (Npresc ? 2*config.setting_frequency_30mhz : 4*config.setting_frequency_30mhz)/ output_divider/MOD; + uint32_t F = ((freq * output_divider*MOD) / (Npresc ? 2*local_setting_frequency_30mhz_x100 : 4*local_setting_frequency_30mhz_x100)) - R*MOD; + freq_t actual_freq = (R*MOD + F) * (Npresc ? 2*local_setting_frequency_30mhz_x100 : 4*local_setting_frequency_30mhz_x100)/ output_divider/MOD; #if 0 // Only for debugging int delta = freq - actual_freq; if (delta < -100 || delta > 100 ){ diff --git a/si5351.c b/si5351.c index e2e5232..b71d031 100644 --- a/si5351.c +++ b/si5351.c @@ -22,32 +22,34 @@ #ifdef __SI5351__ #include "si5351.h" -inline int palReadLine(uint32_t line) { - return ( palReadPort(PAL_PORT(line)) & (1<>1; - int s = i2c_write_buf(addr, buf, len); - return s > 0; + int s = i2c_write_buf(addr, (uint8_t* )buf, len); + return s >= 0; } // register addr, length, data, ... static const uint8_t si5351_configs[] = { 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff, 4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, - 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF, - // setup PLL (26MHz * 32 = 832MHz, 32/2-2=14) - 9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 14, 0, /*P3/P2*/0, 0, 0, +// 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF, + // setup PLL (30MHz * 30 = 900MHz, 30/2-2=13) + 9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 13, 0, /*P3/P2*/0, 0, 0, // RESET PLL 2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B, - // setup multisynth (832MHz / 104 = 8MHz, 104/2-2=50) - 9, SI5351_REG_58_MULTISYNTH2, /*P3*/0, 1, /*P1*/0, 50, 0, /*P2|P3*/0, 0, 0, + // setup multisynth (900MHz / 30 = 30MHz, 30/2-2=13) + 9, SI5351_REG_42_MULTISYNTH0, /*P3*/0, 1, /*P1*/0, 13, 0, /*P2|P3*/0, 0, 0, #ifdef __ENABLE_CLK2__ 2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE, 2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0, @@ -216,7 +220,7 @@ static bool si5351_wait_ready(void) return false; } -#if 0 +#if 1 static void si5351_wait_pll_lock(void) { systime_t start = chVTGetSystemTime(); @@ -242,6 +246,7 @@ bool si5351_init(void) { if (!si5351_wait_ready()) return false; + my_microsecond_delay(200); const uint8_t *p = si5351_configs; while (*p) { uint8_t len = *p++; @@ -249,6 +254,9 @@ bool si5351_init(void) return false; p += len; } + si5351_wait_pll_lock(); + if (pll_lock_failed) + return false; return true; } @@ -421,8 +429,8 @@ static uint32_t gcd(uint32_t x, uint32_t y) return x; } -#define XTALFREQ 26000000L -#define PLL_N 32 +#define XTALFREQ 30000000L +#define PLL_N 30 #define PLLFREQ (XTALFREQ * PLL_N) static void si5351_set_frequency_fixedpll( @@ -470,7 +478,7 @@ static void si5351_set_frequency_fixeddiv( void si5351_set_frequency(int channel, int freq, uint8_t drive_strength) { if (freq <= 100000000) { - si5351_setupPLL(SI5351_PLL_B, 32, 0, 1); + si5351_setupPLL(SI5351_PLL_B, 30, 0, 1); si5351_set_frequency_fixedpll(channel, SI5351_PLL_B, PLLFREQ, freq, SI5351_R_DIV_1, drive_strength); } else if (freq < 150000000) { si5351_set_frequency_fixeddiv(channel, SI5351_PLL_B, freq, 6, drive_strength); @@ -531,7 +539,7 @@ int si5351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_st // fractional divider mode. only PLL A is used. if (current_band == 1 || current_band == 2){ si5351_reset_pll(); - si5351_setupPLL(SI5351_PLL_A, 32, 0, 1); + si5351_setupPLL(SI5351_PLL_A, PLL_N, 0, 1); } if (rdiv == SI5351_R_DIV_8) { diff --git a/si5351.h b/si5351.h index 6792143..6ebe3b1 100644 --- a/si5351.h +++ b/si5351.h @@ -76,10 +76,11 @@ #define SI5351_CRYSTAL_LOAD_8PF (2<<6) #define SI5351_CRYSTAL_LOAD_10PF (3<<6) -#define SI5351_CRYSTAL_FREQ_25MHZ 25000000 +//#define SI5351_CRYSTAL_FREQ_25MHZ 25000000 bool si5351_init(void); void si5351_set_frequency(int channel, int freq, uint8_t drive_strength); int si5351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_strength); +extern char pll_lock_failed; #endif //__SI5351_H__ diff --git a/ui_sa.c b/ui_sa.c index 3eac69e..d2a1ff2 100644 --- a/ui_sa.c +++ b/ui_sa.c @@ -2711,7 +2711,7 @@ static const menuitem_t menu_settings3[] = // { MT_KEYPAD, KM_GRIDLINES, "MINIMUM\nGRIDLINES", "Enter minimum horizontal grid divisions"}, { MT_ADV_CALLBACK, 0, "ADF OUT", menu_adf_out_acb}, { MT_ADV_CALLBACK, 0, "ENABLE\nULTRA", menu_ultra_acb}, - { MT_KEYPAD, KM_ULTRA_START,"ULTRASTART\n\b%s", "Enter ULTRA mode start freq"}, + { MT_KEYPAD, KM_ULTRA_START,"ULTRASTART\n\b%s", "0=auto"}, { MT_ADV_CALLBACK, 0, "ENABLE\nDIRECT", menu_direct_acb}, // { MT_KEYPAD | MT_LOW, KM_IF2, "IF2 FREQ", "Set to zero for no IF2"}, { MT_KEYPAD, KM_R, "R\n\b%s", "Set R"}, @@ -3464,7 +3464,7 @@ set_numeric_value(void) case KM_ULTRA_START: config.ultra_threshold = uistat.value; reset_settings(setting.mode); - config_save(); +// config_save(); // TODO not now //ultra_threshold = config.ultra_threshold; break; case KM_DIRECT_START: