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build: port firmware to ChibiOS 21.11.5

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pull/166/head
PhysicistJohn 7 days ago
parent c97938697b
commit 02bbc6592d
21 changed files with 434 additions and 206 deletions
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4
.gitmodules vendored
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@ -1,4 +1,4 @@
[submodule "ChibiOS"] [submodule "ChibiOS"]
path = ChibiOS path = ChibiOS
url = https://github.com/edy555/ChibiOS.git url = https://github.com/PhysicistJohn/chibios.git
branch = I2SFULLDUPLEX branch = codex/integration-tinysa-21.11.5

2
ChibiOS

@ -1 +1 @@
Subproject commit ade76dea89cd093650552328e881252a06486094 Subproject commit db35f6df137058c612dc13e4488ac923219d881a

31
Makefile
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@ -115,6 +115,8 @@ endif
#CHIBIOS = ../ChibiOS-RT #CHIBIOS = ../ChibiOS-RT
CHIBIOS = ChibiOS CHIBIOS = ChibiOS
PROJ = . PROJ = .
# ChibiOS 21.11.x keeps its license policy header in a dedicated include.
include $(CHIBIOS)/os/license/license.mk
# Startup files. # Startup files.
ifeq ($(TARGET),F303) ifeq ($(TARGET),F303)
@ -130,13 +132,13 @@ include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk
include NANOVNA_STM32_F072/board.mk include NANOVNA_STM32_F072/board.mk
endif endif
include $(CHIBIOS)/os/hal/osal/rt/osal.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional). # RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/rt.mk
ifeq ($(TARGET),F303) ifeq ($(TARGET),F303)
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk
else else
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk include $(CHIBIOS)/os/common/ports/ARMv6-M/compilers/GCC/mk/port.mk
endif endif
# Other files (optional). # Other files (optional).
#include $(CHIBIOS)/test/rt/test.mk #include $(CHIBIOS)/test/rt/test.mk
@ -156,6 +158,7 @@ endif
ifeq ($(TARGET),F303) ifeq ($(TARGET),F303)
CSRC = $(STARTUPSRC) \ CSRC = $(STARTUPSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(OSLIBSRC) \
$(PORTSRC) \ $(PORTSRC) \
$(OSALSRC) \ $(OSALSRC) \
$(HALSRC) \ $(HALSRC) \
@ -170,6 +173,7 @@ CSRC = $(STARTUPSRC) \
else else
CSRC = $(STARTUPSRC) \ CSRC = $(STARTUPSRC) \
$(KERNSRC) \ $(KERNSRC) \
$(OSLIBSRC) \
$(PORTSRC) \ $(PORTSRC) \
$(OSALSRC) \ $(OSALSRC) \
$(HALSRC) \ $(HALSRC) \
@ -205,10 +209,11 @@ TCSRC =
# option that results in lower performance and larger code size. # option that results in lower performance and larger code size.
TCPPSRC = TCPPSRC =
# List ASM source files here # ChibiOS startup and port assembly is preprocessed (.S), not plain assembly.
ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) ASMSRC =
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ INCDIR = $(LICINC) $(STARTUPINC) $(KERNINC) $(OSLIBINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
$(STREAMSINC) $(STREAMSINC)
@ -266,7 +271,7 @@ CPPWARN = -Wall -Wextra -Wundef
# List all user C define here, like -D_DEBUG=1 # List all user C define here, like -D_DEBUG=1
ifeq ($(TARGET),F303) ifeq ($(TARGET),F303)
UDEFS = -DARM_MATH_CM4 -DVERSION=\"$(VERSION)\" -DTINYSA_F303 -D__FPU_USED -DST7796S -DTINYSA4 UDEFS = -DARM_MATH_CM4 -DVERSION=\"$(VERSION)\" -DTINYSA_F303 -DST7796S -DTINYSA4
#Enable if install external 32.768kHz clock quartz on PC14 and PC15 pins on STM32 CPU #Enable if install external 32.768kHz clock quartz on PC14 and PC15 pins on STM32 CPU
UDEFS+= -DVNA_USE_LSE UDEFS+= -DVNA_USE_LSE
# Use R as usb pullup # Use R as usb pullup
@ -292,19 +297,12 @@ ULIBS = -lm
# End of user defines # End of user defines
############################################################################## ##############################################################################
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
include $(RULESPATH)/arm-none-eabi.mk
include $(RULESPATH)/rules.mk include $(RULESPATH)/rules.mk
#include $(CHIBIOS)/memory.mk #include $(CHIBIOS)/memory.mk
ifeq ($(TARGET),F303)
clean:
rm -f -rf build/tinySA4.* build/lst/*.* build/obj/*.*
else
clean:
rm -f -rf build/$(PROJECT).* build/lst/*.* build/obj/*.*
endif
flash: build/$(PROJECT).bin flash: build/$(PROJECT).bin
-@printf "reset dfu\r" >/dev/cu.usbmodem401 # mac -@printf "reset dfu\r" >/dev/cu.usbmodem401 # mac
-@printf "reset dfu\r" >/dev/ttyACM0 # linux -@printf "reset dfu\r" >/dev/ttyACM0 # linux
@ -323,4 +321,3 @@ else
@etags *.[ch] NANOVNA_STM32_F072/*.[ch] $(shell find ChibiOS/os/hal/ports/STM32/STM32F0xx ChibiOS/os -name \*.\[ch\] -print) @etags *.[ch] NANOVNA_STM32_F072/*.[ch] $(shell find ChibiOS/os/hal/ports/STM32/STM32F0xx ChibiOS/os -name \*.\[ch\] -print)
endif endif
@ls -l TAGS @ls -l TAGS

2
NANOVNA_STM32_F072/adc.c
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@ -80,7 +80,7 @@ int16_t adc_vbat_read(void)
// Vbat measure averange count = 2^VBAT_AVERAGE // Vbat measure averange count = 2^VBAT_AVERAGE
#define VBAT_AVERAGE 4 #define VBAT_AVERAGE 4
// Measure vbat every 5 second // Measure vbat every 5 second
#define VBAT_MEASURE_INTERVAL S2ST(5) #define VBAT_MEASURE_INTERVAL TIME_S2I(5)
static int16_t vbat_raw = 0; static int16_t vbat_raw = 0;
static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1; static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1;

83
NANOVNA_STM32_F072/board.c
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@ -14,15 +14,41 @@
limitations under the License. limitations under the License.
*/ */
#include "hal.h" #include "hal.h"
#include "stm32_gpio.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/** typedef struct {
* @brief PAL setup. uint32_t moder;
* @details Digital I/O ports static configuration as defined in @p board.h. uint32_t otyper;
* This variable is used by the HAL when initializing the PAL driver. uint32_t ospeedr;
*/ uint32_t pupdr;
const PALConfig pal_default_config = { uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
typedef struct {
#if STM32_HAS_GPIOA
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF
gpio_setup_t PFData;
#endif
} gpio_config_t;
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA #if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
@ -59,8 +85,40 @@ const PALConfig pal_default_config = {
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif #endif
}; };
#endif
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
rccResetAHB(STM32_GPIO_EN_MASK);
rccEnableAHB(STM32_GPIO_EN_MASK, true);
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
}
static bool needDFU(void) { static bool needDFU(void) {
// Magick data in memory before reset // Magick data in memory before reset
@ -105,7 +163,8 @@ void __early_init(void) {
} }
//si5351_setup(); //si5351_setup();
stm32_clock_init(); stm32_gpio_init();
stm32_clock_init();
} }
/* /*

95
NANOVNA_STM32_F303/adc.c
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@ -36,54 +36,67 @@ static adcsample_t samplesVBAT[ADC_GRP_NUM_CHANNELS_VBAT];
static adcsample_t samples[1]; static adcsample_t samples[1];
static const ADCConversionGroup adcgrpcfgVBAT = { static const ADCConversionGroup adcgrpcfgVBAT = {
FALSE, .circular = false,
ADC_GRP_NUM_CHANNELS_VBAT, .num_channels = ADC_GRP_NUM_CHANNELS_VBAT,
NULL, .end_cb = NULL,
NULL, .error_cb = NULL,
ADC_CFGR_CONT | ADC_CFGR1_RES_12BIT, // CFGR1 .cfgr = ADC_CFGR_CONT | ADC_CFGR_RES_12BITS,
ADC_TR(0, 0), // ADC watchdog threshold TR1 .tr1 = ADC_TR(0, 0),
{0, ADC_SMPR2_SMP_AN16(ADC_VBAT_SMP_TIME) | ADC_SMPR2_SMP_AN17(ADC_VBAT_SMP_TIME)/*| ADC_SMPR2_SMP_AN18(ADC_VBAT_SMP_TIME)*/}, // SMPR .tr2 = ADC_TR_DISABLED,
{ADC_SQR1_SQ1_N(ADC_CHANNEL_IN17) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN18)/*| ADC_SQR1_SQ3_N(ADC_CHANNEL_IN16)*/, 0, 0, 0} // CHSELR .tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {0, ADC_SMPR2_SMP_AN16(ADC_VBAT_SMP_TIME) |
ADC_SMPR2_SMP_AN17(ADC_VBAT_SMP_TIME)},
.sqr = {ADC_SQR1_SQ1_N(ADC_CHANNEL_IN17) |
ADC_SQR1_SQ2_N(ADC_CHANNEL_IN18), 0, 0, 0}
}; };
static const ADCConversionGroup adcgrpcfgVersion = { static const ADCConversionGroup adcgrpcfgVersion = {
FALSE, .circular = false,
1, .num_channels = 1,
NULL, .end_cb = NULL,
NULL, .error_cb = NULL,
ADC_CFGR1_RES_12BIT, // CFGR1 .cfgr = ADC_CFGR_RES_12BITS,
ADC_TR(0, 0), // ADC watchdog threshold TR1 .tr1 = ADC_TR(0, 0),
{ADC_SMPR1_SMP_AN1(ADC_TOUCH_XY_SMP_TIME), 0}, /* SMPR[2] */ .tr2 = ADC_TR_DISABLED,
{ADC_SQR1_SQ1_N(ADC_CHANNEL_IN1), 0, 0, 0} /* SQR[4] */ .tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {ADC_SMPR1_SMP_AN1(ADC_TOUCH_XY_SMP_TIME), 0},
.sqr = {ADC_SQR1_SQ1_N(ADC_CHANNEL_IN1), 0, 0, 0}
}; };
static const ADCConversionGroup adcgrpcfgTouch = { static const ADCConversionGroup adcgrpcfgTouch = {
TRUE, // Enables the circular buffer mode for the group. .circular = true,
1, // Number of the analog channels belonging to the conversion group. .num_channels = 1,
NULL, // adccallback_touch .end_cb = NULL,
NULL, // adcerrorcallback_touch .error_cb = NULL,
// CFGR .cfgr = ADC_CFGR_EXTEN_0 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 |
ADC_CFGR_EXTEN_0 // rising edge of external trigger ADC_CFGR_AWD1EN,
.tr1 = ADC_TR(0, TOUCH_THRESHOLD),
| ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 // EXT4 0x1001 event (TIM1_TRGO) .tr2 = ADC_TR_DISABLED,
// | ADC_CFGR_EXTSEL_2 // EXT4 0x100 event (TIM3_TRGO) .tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
| ADC_CFGR_AWD1EN, // Enable Analog watchdog check interrupt .smpr = {ADC_SMPR1_SMP_AN4(ADC_TOUCH_SMP_TIME), 0},
ADC_TR(0, TOUCH_THRESHOLD), // Analog watchdog threshold TR1, interrupt on touch press .sqr = {ADC_SQR1_SQ1_N(ADC_CHANNEL_IN4), 0, 0, 0}
{ADC_SMPR1_SMP_AN4(ADC_TOUCH_SMP_TIME), 0}, // SMPR[2]
{ADC_SQR1_SQ1_N(ADC_CHANNEL_IN4), 0, 0, 0} // SQR[4]
}; };
static ADCConversionGroup adcgrpcfgXY = { static ADCConversionGroup adcgrpcfgXY = {
FALSE, .circular = false,
1, .num_channels = 1,
NULL, /* adccallback_touch */ .end_cb = NULL,
NULL, /* adcerrorcallback_touch */ .error_cb = NULL,
ADC_CFGR1_RES_12BIT, /* CFGR */ .cfgr = ADC_CFGR_RES_12BITS,
ADC_TR(0, 0), /* TR1 */ .tr1 = ADC_TR(0, 0),
{ADC_SMPR1_SMP_AN3(ADC_TOUCH_XY_SMP_TIME) | ADC_SMPR1_SMP_AN4(ADC_TOUCH_XY_SMP_TIME), 0}, /* SMPR[2] */ .tr2 = ADC_TR_DISABLED,
{ADC_SQR1_SQ1_N(ADC_CHANNEL_IN3), 0, 0, 0} /* SQR[4] */ .tr3 = ADC_TR_DISABLED,
.awd2cr = 0U,
.awd3cr = 0U,
.smpr = {ADC_SMPR1_SMP_AN3(ADC_TOUCH_XY_SMP_TIME) |
ADC_SMPR1_SMP_AN4(ADC_TOUCH_XY_SMP_TIME), 0},
.sqr = {ADC_SQR1_SQ1_N(ADC_CHANNEL_IN3), 0, 0, 0}
}; };
void adc_init(void) void adc_init(void)
@ -120,7 +133,7 @@ int16_t adc_vbat_read(void)
// Vbat measure averange count = 2^VBAT_AVERAGE // Vbat measure averange count = 2^VBAT_AVERAGE
#define VBAT_AVERAGE 4 #define VBAT_AVERAGE 4
// Measure vbat every 5 second // Measure vbat every 5 second
#define VBAT_MEASURE_INTERVAL S2ST(5) #define VBAT_MEASURE_INTERVAL TIME_S2I(5)
static int16_t vbat_raw = 0; static int16_t vbat_raw = 0;
static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1; static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1;
@ -219,7 +232,7 @@ uint16_t adc_multi_read(uint32_t chsel, uint16_t *result, uint32_t count)
VNA_ADC->IER = 0; VNA_ADC->IER = 0;
VNA_ADC->TR = ADC_TR(0, 0); VNA_ADC->TR = ADC_TR(0, 0);
VNA_ADC->SMPR = ADC_SMPR_SMP_1P5; VNA_ADC->SMPR = ADC_SMPR_SMP_1P5;
VNA_ADC->CFGR1 = ADC_CFGR1_RES_12BIT; VNA_ADC->CFGR = ADC_CFGR_RES_12BITS;
VNA_ADC->CHSELR = chsel; VNA_ADC->CHSELR = chsel;

73
NANOVNA_STM32_F303/board.c
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@ -15,14 +15,40 @@
*/ */
#include "hal.h" #include "hal.h"
#include "stm32_gpio.h"
#if HAL_USE_PAL || defined(__DOXYGEN__) typedef struct {
/** uint32_t moder;
* @brief PAL setup. uint32_t otyper;
* @details Digital I/O ports static configuration as defined in @p board.h. uint32_t ospeedr;
* This variable is used by the HAL when initializing the PAL driver. uint32_t pupdr;
*/ uint32_t odr;
const PALConfig pal_default_config = { uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
typedef struct {
#if STM32_HAS_GPIOA
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF
gpio_setup_t PFData;
#endif
} gpio_config_t;
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA #if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
@ -60,7 +86,39 @@ const PALConfig pal_default_config = {
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif #endif
}; };
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
rccResetAHB(STM32_GPIO_EN_MASK);
rccEnableAHB(STM32_GPIO_EN_MASK, true);
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif #endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
}
// extern void si5351_setup(void); // extern void si5351_setup(void);
@ -129,6 +187,7 @@ void __early_init(void) {
#endif #endif
} }
// si5351_setup(); // si5351_setup();
stm32_gpio_init();
stm32_clock_init(); stm32_clock_init();
} }

2
NANOVNA_STM32_F303/board.h
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@ -27,8 +27,6 @@
#define BOARD_NANOVNA_STM32_F303 #define BOARD_NANOVNA_STM32_F303
#define BOARD_NAME "tinySA ULTRA" #define BOARD_NAME "tinySA ULTRA"
#include <stm32f303xc.h>
//#include "..\nanovna.h"
/* /*
* Board frequencies. * Board frequencies.
*/ */

23
NANOVNA_STM32_F303/mcuconf.h
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@ -32,6 +32,7 @@
*/ */
#define STM32F3xx_MCUCONF #define STM32F3xx_MCUCONF
#define STM32F303_MCUCONF
/* /*
* HAL driver system settings. * HAL driver system settings.
@ -111,9 +112,9 @@
//#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) //#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC12_DMA_PRIORITY 2 #define STM32_ADC_ADC12_DMA_PRIORITY 2
//#define STM32_ADC_ADC34_DMA_PRIORITY 2 //#define STM32_ADC_ADC34_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 2 #define STM32_ADC_ADC12_IRQ_PRIORITY 3
//#define STM32_ADC_ADC34_IRQ_PRIORITY 5 //#define STM32_ADC_ADC34_IRQ_PRIORITY 5
#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2 #define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 3
//#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 //#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5
//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK //#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 //#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
@ -157,10 +158,10 @@
#define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 TRUE #define STM32_GPT_USE_TIM4 TRUE
#define STM32_GPT_TIM1_IRQ_PRIORITY 2 #define STM32_GPT_TIM1_IRQ_PRIORITY 3
#define STM32_GPT_TIM2_IRQ_PRIORITY 2 #define STM32_GPT_TIM2_IRQ_PRIORITY 3
#define STM32_GPT_TIM3_IRQ_PRIORITY 2 #define STM32_GPT_TIM3_IRQ_PRIORITY 3
#define STM32_GPT_TIM4_IRQ_PRIORITY 2 #define STM32_GPT_TIM4_IRQ_PRIORITY 3
/* /*
* I2C driver system settings. * I2C driver system settings.
@ -184,8 +185,8 @@
STM32_I2S_MODE_RX) STM32_I2S_MODE_RX)
#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ #define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \
STM32_I2S_MODE_RX ) STM32_I2S_MODE_RX )
#define STM32_I2S_SPI1_IRQ_PRIORITY 2 #define STM32_I2S_SPI1_IRQ_PRIORITY 3
#define STM32_I2S_SPI2_IRQ_PRIORITY 2 #define STM32_I2S_SPI2_IRQ_PRIORITY 3
#define STM32_I2S_SPI1_DMA_PRIORITY 1 #define STM32_I2S_SPI1_DMA_PRIORITY 1
#define STM32_I2S_SPI2_DMA_PRIORITY 1 #define STM32_I2S_SPI2_DMA_PRIORITY 1
#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
@ -233,14 +234,14 @@
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 2 #define STM32_SPI_SPI1_IRQ_PRIORITY 3
#define STM32_SPI_SPI2_IRQ_PRIORITY 2 #define STM32_SPI_SPI2_IRQ_PRIORITY 3
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/* /*
* ST driver system settings. * ST driver system settings.
*/ */
#define STM32_ST_IRQ_PRIORITY 2 #define STM32_ST_IRQ_PRIORITY 3
#define STM32_ST_USE_TIMER 2 #define STM32_ST_USE_TIMER 2
/* /*

35
chconf.h
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@ -29,6 +29,9 @@
#define _CHCONF_H_ #define _CHCONF_H_
#define _CHIBIOS_RT_CONF_ #define _CHIBIOS_RT_CONF_
#define _CHIBIOS_RT_CONF_VER_7_0_
#define CH_CFG_SMP_MODE FALSE
/*===========================================================================*/ /*===========================================================================*/
/** /**
@ -49,6 +52,8 @@
* setting also defines the system tick time unit. * setting also defines the system tick time unit.
*/ */
#define CH_CFG_ST_FREQUENCY 10000 #define CH_CFG_ST_FREQUENCY 10000
#define CH_CFG_INTERVALS_SIZE 32
#define CH_CFG_TIME_TYPES_SIZE 32
/** /**
* @brief Time delta constant for the tick-less mode. * @brief Time delta constant for the tick-less mode.
@ -140,6 +145,7 @@
* @note The default is @p TRUE. * @note The default is @p TRUE.
*/ */
#define CH_CFG_USE_TM FALSE #define CH_CFG_USE_TM FALSE
#define CH_CFG_USE_TIMESTAMP FALSE
/** /**
* @brief Threads registry APIs. * @brief Threads registry APIs.
@ -305,6 +311,20 @@
*/ */
#define CH_CFG_USE_MEMPOOLS FALSE #define CH_CFG_USE_MEMPOOLS FALSE
#define CH_CFG_USE_OBJ_FIFOS FALSE
#define CH_CFG_USE_PIPES FALSE
#define CH_CFG_USE_OBJ_CACHES FALSE
#define CH_CFG_USE_DELEGATES FALSE
#define CH_CFG_USE_JOBS FALSE
#define CH_CFG_USE_FACTORY FALSE
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
#define CH_CFG_FACTORY_OBJECTS_REGISTRY FALSE
#define CH_CFG_FACTORY_GENERIC_BUFFERS FALSE
#define CH_CFG_FACTORY_SEMAPHORES FALSE
#define CH_CFG_FACTORY_MAILBOXES FALSE
#define CH_CFG_FACTORY_OBJ_FIFOS FALSE
#define CH_CFG_FACTORY_PIPES FALSE
/** /**
* @brief Dynamic Threads APIs. * @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included * @details If enabled then the dynamic threads creation APIs are included
@ -417,6 +437,18 @@
*/ */
/*===========================================================================*/ /*===========================================================================*/
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
/* No custom system fields.*/
#define CH_CFG_SYSTEM_INIT_HOOK() { \
}
#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \
/* No custom instance fields.*/
#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \
}
/** /**
* @brief Threads descriptor structure extension. * @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure. * @details User fields added to the end of the @p thread_t structure.
@ -522,6 +554,9 @@
/* Trace code here.*/ \ /* Trace code here.*/ \
} }
#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \
}
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/

8
chprintf.c
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@ -630,7 +630,13 @@ static msg_t put(void *ip, uint8_t b) {
return MSG_OK; return MSG_OK;
} }
static const struct printStreamVMT vmt = {NULL, NULL, put, NULL}; static const struct printStreamVMT vmt = {
.instance_offset = 0U,
.write = NULL,
.read = NULL,
.put = put,
.get = NULL
};
void printObjectInit(printStream *ps, int size, uint8_t *buffer){ void printObjectInit(printStream *ps, int size, uint8_t *buffer){
ps->vmt = &vmt; ps->vmt = &vmt;
ps->buffer = buffer; ps->buffer = buffer;

56
docs/CHIBIOS_21_11_5_PORT.md
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@ -0,0 +1,56 @@
# ChibiOS 21.11.5 port
This branch ports both firmware targets from the historical tinySA ChibiOS
fork to the official ChibiOS `ver21.11.5` release.
The draft currently pins the public integration commit
`db35f6df137058c612dc13e4488ac923219d881a` from
`PhysicistJohn/chibios`. It contains two focused commits on top of the release
tag:
1. restore the standalone STM32F0 TIM14 GPT interrupt service;
2. preserve active USBv1 endpoint-zero PMA buffers when configuration
endpoints are rebuilt.
Those fixes are also proposed independently to current ChibiOS in PRs #84 and
#85 and to `stable-21.11.x` in draft PRs #86 and #87. The temporary fork URL
will be replaced with the canonical ChibiOS URL and merged stable commit before
this port is marked ready.
## Port changes
- Adopt the RT7/HAL9 configuration markers, OS library settings, build rules,
Cortex-M port paths, and license include required by ChibiOS 21.11.5.
- Raise kernel-aware F303 interrupt priorities to respect the RT7
fast-interrupt reservation.
- Migrate board GPIO initialization, DMA allocation, ADC group definitions,
PAL line events, USB serial hooks, endpoint configuration, PWM configuration,
queue reset calls, time conversions, and thread diagnostics.
- Update the project-local F303 ADC LLD while retaining its tinySA-specific
behavior.
- Convert custom `BaseSequentialStream` VMTs to the current layout.
## Build
With an Arm GNU toolchain on `PATH`:
```sh
git submodule update --init --recursive
make TARGET=F303 -j8
make clean
make TARGET=F072 -j8
```
## Qualification boundary
The predecessor RC5 image using the same application port and equivalent
ChibiOS fixes was exercised on a tinySA Ultra+ ZS407. Its exact DFU write and
readback, USB runtime, warm reset retention, cold boot, and all fourteen
built-in self-tests passed. A fresh official-versus-candidate comparison had
one first-cold measured-level threshold failure in case 2; three repeats,
including a second cold run, passed. Physical forced-fault injection was not
performed.
The clean public branch has different commit identity and embedded version, so
it is a new binary. It must be rebuilt and receive a final physical smoke and
self-test run before this draft is promoted to ready.

67
hal_adc_lld.c
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@ -444,7 +444,7 @@ void adc_lld_init(void) {
#if STM32_ADC_DUAL_MODE #if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2; ADCD1.adcs = ADC2;
#endif #endif
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); ADCD1.dmastp = NULL;
ADCD1.dmamode = ADC_DMA_SIZE | ADCD1.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
@ -461,7 +461,7 @@ void adc_lld_init(void) {
ADCD2.adcc = ADC123_COMMON; ADCD2.adcc = ADC123_COMMON;
#endif #endif
ADCD2.adcm = ADC2; ADCD2.adcm = ADC2;
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); ADCD2.dmastp = NULL;
ADCD2.dmamode = ADC_DMA_SIZE | ADCD2.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
@ -483,7 +483,7 @@ void adc_lld_init(void) {
#if STM32_ADC_DUAL_MODE #if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4; ADCD3.adcs = ADC4;
#endif #endif
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); ADCD3.dmastp = NULL;
ADCD3.dmamode = ADC_DMA_SIZE | ADCD3.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
@ -496,7 +496,7 @@ void adc_lld_init(void) {
adcObjectInit(&ADCD4); adcObjectInit(&ADCD4);
ADCD4.adcc = ADC3_4_COMMON; ADCD4.adcc = ADC3_4_COMMON;
ADCD4.adcm = ADC4; ADCD4.adcm = ADC4;
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM); ADCD4.dmastp = NULL;
ADCD4.dmamode = ADC_DMA_SIZE | ADCD4.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) | STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_DIR_P2M |
@ -524,13 +524,13 @@ void adc_lld_init(void) {
rccEnableADC12(FALSE); rccEnableADC12(FALSE);
rccResetADC12(); rccResetADC12();
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12(FALSE); rccDisableADC12();
#endif #endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4 #if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
rccEnableADC34(FALSE); rccEnableADC34(FALSE);
rccResetADC34(); rccResetADC34();
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34(FALSE); rccDisableADC34();
#endif #endif
#endif #endif
@ -538,7 +538,7 @@ void adc_lld_init(void) {
rccEnableADC123(FALSE); rccEnableADC123(FALSE);
rccResetADC123(); rccResetADC123();
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC123(FALSE); rccDisableADC123();
#endif #endif
} }
@ -560,12 +560,11 @@ void adc_lld_start(ADCDriver *adcp) {
if (adcp->state == ADC_STOP) { if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1 #if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) { if (&ADCD1 == adcp) {
bool b; adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM,
b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp);
(void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
osalDbgAssert(!b, "stream already allocated");
clkmask |= (1 << 0); clkmask |= (1 << 0);
#if defined(STM32F3XX) #if defined(STM32F3XX)
@ -579,12 +578,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC2 #if STM32_ADC_USE_ADC2
if (&ADCD2 == adcp) { if (&ADCD2 == adcp) {
bool b; adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM,
b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
STM32_ADC_ADC2_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp);
(void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
osalDbgAssert(!b, "stream already allocated");
clkmask |= (1 << 1); clkmask |= (1 << 1);
#if defined(STM32F3XX) #if defined(STM32F3XX)
@ -598,12 +596,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC3 #if STM32_ADC_USE_ADC3
if (&ADCD3 == adcp) { if (&ADCD3 == adcp) {
bool b; adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM,
b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
STM32_ADC_ADC3_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp);
(void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
osalDbgAssert(!b, "stream already allocated");
clkmask |= (1 << 2); clkmask |= (1 << 2);
#if defined(STM32F3XX) #if defined(STM32F3XX)
@ -617,12 +614,11 @@ void adc_lld_start(ADCDriver *adcp) {
#if STM32_ADC_USE_ADC4 #if STM32_ADC_USE_ADC4
if (&ADCD4 == adcp) { if (&ADCD4 == adcp) {
bool b; adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC4_DMA_STREAM,
b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC4_DMA_IRQ_PRIORITY,
STM32_ADC_ADC4_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp);
(void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
osalDbgAssert(!b, "stream already allocated");
clkmask |= (1 << 3); clkmask |= (1 << 3);
#if defined(STM32F3XX) #if defined(STM32F3XX)
@ -671,7 +667,8 @@ void adc_lld_stop(ADCDriver *adcp) {
if (adcp->state == ADC_READY) { if (adcp->state == ADC_READY) {
/* Releasing the associated DMA channel.*/ /* Releasing the associated DMA channel.*/
dmaStreamRelease(adcp->dmastp); dmaStreamFreeI(adcp->dmastp);
adcp->dmastp = NULL;
/* Stopping the ongoing conversion, if any.*/ /* Stopping the ongoing conversion, if any.*/
adc_lld_stop_adc(adcp); adc_lld_stop_adc(adcp);
@ -727,16 +724,16 @@ void adc_lld_stop(ADCDriver *adcp) {
#if defined(STM32F3XX) #if defined(STM32F3XX)
if ((clkmask & 0x3) == 0) { if ((clkmask & 0x3) == 0) {
rccDisableADC12(FALSE); rccDisableADC12();
} }
if ((clkmask & 0xC) == 0) { if ((clkmask & 0xC) == 0) {
rccDisableADC34(FALSE); rccDisableADC34();
} }
#endif #endif
#if defined(STM32L4XX) #if defined(STM32L4XX)
if ((clkmask & 0x7) == 0) { if ((clkmask & 0x7) == 0) {
rccDisableADC123(FALSE); rccDisableADC123();
} }
#endif #endif
} }

3
halconf.h
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@ -28,6 +28,9 @@
#ifndef _HALCONF_H_ #ifndef _HALCONF_H_
#define _HALCONF_H_ #define _HALCONF_H_
#define _CHIBIOS_HAL_CONF_
#define _CHIBIOS_HAL_CONF_VER_9_1_
#include "mcuconf.h" #include "mcuconf.h"
/** /**

16
ili9341.c
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@ -881,7 +881,13 @@ int lcd_printf(int16_t x, int16_t y, const char *fmt, ...) {
// Init small lcd print stream // Init small lcd print stream
struct lcd_printStreamVMT { struct lcd_printStreamVMT {
_base_sequential_stream_methods _base_sequential_stream_methods
} lcd_vmt = {NULL, NULL, put_char, NULL}; } lcd_vmt = {
.instance_offset = 0U,
.write = NULL,
.read = NULL,
.put = put_char,
.get = NULL
};
lcdPrintStream ps = {&lcd_vmt, x, y, x, y}; lcdPrintStream ps = {&lcd_vmt, x, y, x, y};
// Performing the print operation using the common code. // Performing the print operation using the common code.
va_list ap; va_list ap;
@ -1357,7 +1363,7 @@ static uint8_t SD_WaitNotBusy(uint32_t wait_time) {
// Receive data block from SD // Receive data block from SD
static bool SD_RxDataBlock(uint8_t *buff, uint16_t len, uint8_t token) { static bool SD_RxDataBlock(uint8_t *buff, uint16_t len, uint8_t token) {
// loop until receive read response token or timeout ~50ms // loop until receive read response token or timeout ~50ms
if (!SD_WaitDataToken(token, MS2ST(50))) { if (!SD_WaitDataToken(token, TIME_MS2I(50))) {
DEBUG_PRINT(" rx SD_WaitDataToken err\r\n"); DEBUG_PRINT(" rx SD_WaitDataToken err\r\n");
return FALSE; return FALSE;
} }
@ -1408,7 +1414,7 @@ static bool SD_TxDataBlock(const uint8_t *buff, uint16_t len, uint8_t token) {
} }
#if 1 #if 1
// Wait busy (recommended timeout is 250ms (500ms for SDXC) set 250ms // Wait busy (recommended timeout is 250ms (500ms for SDXC) set 250ms
resp = SD_WaitNotBusy(MS2ST(250)); resp = SD_WaitNotBusy(TIME_MS2I(250));
if (resp == 0xFF) if (resp == 0xFF)
return TRUE; return TRUE;
#else #else
@ -1427,7 +1433,7 @@ static uint8_t SD_SendCmd(uint8_t cmd, uint32_t arg) {
uint8_t buf[6]; uint8_t buf[6];
volatile uint8_t r1; volatile uint8_t r1;
// wait SD ready after last Tx (recommended timeout is 250ms (500ms for SDXC) set 250ms // wait SD ready after last Tx (recommended timeout is 250ms (500ms for SDXC) set 250ms
if ((r1 = SD_WaitNotBusy(MS2ST(500))) != 0xFF) { if ((r1 = SD_WaitNotBusy(TIME_MS2I(500))) != 0xFF) {
DEBUG_PRINT(" SD_WaitNotBusy CMD%d err, %02x\r\n", cmd-0x40, (uint32_t)r1); DEBUG_PRINT(" SD_WaitNotBusy CMD%d err, %02x\r\n", cmd-0x40, (uint32_t)r1);
return 0xFF; return 0xFF;
} }
@ -1707,7 +1713,7 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void* buff) {
// Nothing to do for this command if each write operation to the media is completed // Nothing to do for this command if each write operation to the media is completed
// within the disk_write function. // within the disk_write function.
case CTRL_SYNC: case CTRL_SYNC:
if (SD_WaitNotBusy(MS2ST(200)) == 0xFF) res = RES_OK; if (SD_WaitNotBusy(TIME_MS2I(200)) == 0xFF) res = RES_OK;
break; break;
#if FF_USE_TRIM == 1 #if FF_USE_TRIM == 1
// Informs the device the data on the block of sectors is no longer needed and it can be erased. // Informs the device the data on the block of sectors is no longer needed and it can be erased.

20
main.c
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@ -209,7 +209,7 @@ static THD_FUNCTION(Thread1, arg)
{ {
completed = sweep(true); completed = sweep(true);
#ifdef __USE_SD_CARD__ #ifdef __USE_SD_CARD__
if (setting.trigger_auto_save && (last_auto_save == 0 || chVTGetSystemTimeX() - last_auto_save > S2ST(30)) ) { // once every 30 seconds max if (setting.trigger_auto_save && (last_auto_save == 0 || chVTGetSystemTimeX() - last_auto_save > TIME_S2I(30)) ) { // once every 30 seconds max
uint16_t old_mode = config._mode; uint16_t old_mode = config._mode;
config._mode |= _MODE_AUTO_FILENAME; config._mode |= _MODE_AUTO_FILENAME;
save_csv(1+(2<<0)); // frequencies + trace 1 save_csv(1+(2<<0)); // frequencies + trace 1
@ -455,7 +455,7 @@ VNA_SHELL_FUNCTION(cmd_restart)
(void)argc; (void)argc;
(void)argv; (void)argv;
if (argc == 1) { if (argc == 1) {
restart_interval = S2ST(my_atoi(argv[0])); restart_interval = TIME_S2I(my_atoi(argv[0]));
if (restart_interval) { if (restart_interval) {
restart_set_time = chVTGetSystemTimeX(); restart_set_time = chVTGetSystemTimeX();
if (restart_set_time == 0) if (restart_set_time == 0)
@ -2418,7 +2418,7 @@ VNA_SHELL_FUNCTION(cmd_threads)
#endif #endif
shell_printf("%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s"VNA_SHELL_NEWLINE_STR, shell_printf("%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s"VNA_SHELL_NEWLINE_STR,
stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp, stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp,
(uint32_t)tp->refs - 1, (uint32_t)tp->prio, states[tp->state], (uint32_t)tp->refs - 1, (uint32_t)tp->hdr.pqueue.prio, states[tp->state],
tp->name == NULL ? "" : tp->name); tp->name == NULL ? "" : tp->name);
tp = chRegNextThread(tp); tp = chRegNextThread(tp);
} while (tp != NULL); } while (tp != NULL);
@ -2697,18 +2697,21 @@ void shell_update_speed(void){
} }
void shell_reset_console(void){ void shell_reset_console(void){
osalSysLock();
// Reset I/O queue over USB (for USB need also connect/disconnect) // Reset I/O queue over USB (for USB need also connect/disconnect)
if (usb_IsActive()){ if (usb_IsActive()){
if (config._mode & _MODE_SERIAL) if (config._mode & _MODE_SERIAL)
sduDisconnectI(&SDU1); sduSuspendHookI(&SDU1);
else else
sduConfigureHookI(&SDU1); sduConfigureHookI(&SDU1);
} }
// Reset I/O queue over Serial // Reset I/O queue over Serial
// oqResetI(&SD1.oqueue); // oqResetI(&SD1.oqueue);
// iqResetI(&SD1.iqueue); // iqResetI(&SD1.iqueue);
qResetI(&SD1.oqueue); oqResetI(&SD1.oqueue);
qResetI(&SD1.iqueue); iqResetI(&SD1.iqueue);
osalOsRescheduleS();
osalSysUnlock();
} }
@ -2886,7 +2889,7 @@ static void VNAShell_executeLine(char *line)
int timeout_count = 0; int timeout_count = 0;
msg_t result; msg_t result;
do { do {
result = osalThreadEnqueueTimeoutS(&shell_thread, MS2ST(5000)); // 5 second timeout result = osalThreadEnqueueTimeoutS(&shell_thread, TIME_MS2I(5000)); // 5 second timeout
if (result == MSG_TIMEOUT) { if (result == MSG_TIMEOUT) {
timeout_count++; timeout_count++;
if (timeout_count > 3) { if (timeout_count > 3) {
@ -3004,6 +3007,7 @@ static PWMConfig pwmcfg = {
{PWM_OUTPUT_DISABLED, NULL} {PWM_OUTPUT_DISABLED, NULL}
}, },
0, 0,
0,
0 0
}; };
@ -3516,7 +3520,7 @@ void hard_fault_handler_c(uint32_t *sp)
#endif #endif
lcd_printf(x, y+=FONT_STR_HEIGHT, "%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s", lcd_printf(x, y+=FONT_STR_HEIGHT, "%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s",
stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp, stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp,
(uint32_t)tp->refs - 1, (uint32_t)tp->prio, states[tp->state], (uint32_t)tp->refs - 1, (uint32_t)tp->hdr.pqueue.prio, states[tp->state],
tp->name == NULL ? "" : tp->name); tp->name == NULL ? "" : tp->name);
tp = chRegNextThread(tp); tp = chRegNextThread(tp);
} while (tp != NULL); } while (tp != NULL);

8
plot.c
Unescape View File

@ -1509,7 +1509,13 @@ int cell_printf(int16_t x, int16_t y, const char *fmt, ...) {
// Init small cell print stream // Init small cell print stream
struct cellprintStreamVMT { struct cellprintStreamVMT {
_base_sequential_stream_methods _base_sequential_stream_methods
} cell_vmt = {NULL, NULL, NULL, NULL}; } cell_vmt = {
.instance_offset = 0U,
.write = NULL,
.read = NULL,
.put = NULL,
.get = NULL
};
screenPrintStream ps = {&cell_vmt, x, y}; screenPrintStream ps = {&cell_vmt, x, y};
// Select font and skip print if not on cell (at top/bottom) // Select font and skip print if not on cell (at top/bottom)
switch (*fmt++){ switch (*fmt++){

2
sa_core.c
Unescape View File

@ -5849,7 +5849,7 @@ static volatile int dummy;
} else if (actual_max_level > target_level && setting.attenuate_x2 < 60) { } else if (actual_max_level > target_level && setting.attenuate_x2 < 60) {
delta = actual_max_level - target_level; delta = actual_max_level - target_level;
} }
if (chVTGetSystemTimeX() - sweep_elapsed > MS2ST(1000)){ if (chVTGetSystemTimeX() - sweep_elapsed > TIME_MS2I(1000)){
if (( delta < -5 || delta > +5) || delta > 10 ) { if (( delta < -5 || delta > +5) || delta > 10 ) {
setting.attenuate_x2 += delta + delta; setting.attenuate_x2 += delta + delta;
if (setting.attenuate_x2 < 0) if (setting.attenuate_x2 < 0)

4
si5351.c
Unescape View File

@ -210,7 +210,7 @@ static bool si5351_wait_ready(void)
{ {
uint8_t status = 0xff; uint8_t status = 0xff;
systime_t start = chVTGetSystemTime(); systime_t start = chVTGetSystemTime();
systime_t end = start + MS2ST(1000); // 1000 ms timeout systime_t end = start + TIME_MS2I(1000); // 1000 ms timeout
while (chVTIsSystemTimeWithin(start, end)) while (chVTIsSystemTimeWithin(start, end))
{ {
if(!si5351_read(0, &status)) if(!si5351_read(0, &status))
@ -230,7 +230,7 @@ static void si5351_wait_pll_lock(void)
status = 0xff; // comm timeout status = 0xff; // comm timeout
if ((status & 0x60) == 0) if ((status & 0x60) == 0)
return; return;
systime_t end = start + MS2ST(100); // 100 ms timeout systime_t end = start + TIME_MS2I(100); // 100 ms timeout
while (chVTIsSystemTimeWithin(start, end)) while (chVTIsSystemTimeWithin(start, end))
{ {
if(!si5351_read(0, &status)) if(!si5351_read(0, &status))

75
ui.c
Unescape View File

@ -48,10 +48,10 @@ uistat_t uistat = {
#define EVT_DOWN 0x20 #define EVT_DOWN 0x20
#define EVT_REPEAT 0x40 #define EVT_REPEAT 0x40
#define BUTTON_DOWN_LONG_TICKS MS2ST(500) // 500ms #define BUTTON_DOWN_LONG_TICKS TIME_MS2I(500) // 500ms
#define BUTTON_DOUBLE_TICKS MS2ST(250) // 250ms #define BUTTON_DOUBLE_TICKS TIME_MS2I(250) // 250ms
#define BUTTON_REPEAT_TICKS MS2ST( 40) // 40ms #define BUTTON_REPEAT_TICKS TIME_MS2I(40) // 40ms
#define BUTTON_DEBOUNCE_TICKS MS2ST( 2) // 2ms #define BUTTON_DEBOUNCE_TICKS TIME_MS2I(2) // 2ms
/* lever switch assignment */ /* lever switch assignment */
#define BIT_UP1 3 #define BIT_UP1 3
@ -684,7 +684,7 @@ extern const char *states[];
#endif #endif
lcd_printf(x, y+=bFONT_STR_HEIGHT, "%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s", lcd_printf(x, y+=bFONT_STR_HEIGHT, "%08x|%08x|%08x|%08x|%4u|%4u|%9s|%12s",
stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp, stklimit, (uint32_t)tp->ctx.sp, max_stack_use, (uint32_t)tp,
(uint32_t)tp->refs - 1, (uint32_t)tp->prio, states[tp->state], (uint32_t)tp->refs - 1, (uint32_t)tp->hdr.pqueue.prio, states[tp->state],
tp->name == NULL ? "" : tp->name); tp->name == NULL ? "" : tp->name);
tp = chRegNextThread(tp); tp = chRegNextThread(tp);
} while (tp != NULL); } while (tp != NULL);
@ -1599,10 +1599,12 @@ static const menuitem_t menu_calibrate_normal[];
#endif #endif
static const menuitem_t menu_calibrate[]; static const menuitem_t menu_calibrate[];
static const menuitem_t menu_sweep[]; static const menuitem_t menu_sweep[];
#ifdef TINYSA4
static const menuitem_t menu_settings[]; static const menuitem_t menu_settings[];
static const menuitem_t menu_settings2[];
static const menuitem_t menu_lowoutput_settings[]; static const menuitem_t menu_lowoutput_settings[];
static const menuitem_t menu_lowoutput_settings_max[]; static const menuitem_t menu_lowoutput_settings_max[];
#endif
static const menuitem_t menu_settings2[];
extern bool dirty; extern bool dirty;
char range_text[20]; char range_text[20];
#ifdef TINYSA4 #ifdef TINYSA4
@ -8382,10 +8384,9 @@ ui_process(void)
} }
/* Triggered when the button is pressed or released. The LED4 is set to ON.*/ /* Triggered when the button is pressed or released. The LED4 is set to ON.*/
static void extcb1(EXTDriver *extp, expchannel_t channel) static void extcb1(void *arg)
{ {
(void)extp; uint32_t channel = (uint32_t)(uintptr_t)arg;
(void)channel;
#ifdef __USE_SD_CARD__ #ifdef __USE_SD_CARD__
if (channel == 12) if (channel == 12)
SD_PowerOff(); SD_PowerOff();
@ -8397,42 +8398,6 @@ static void extcb1(EXTDriver *extp, expchannel_t channel)
// cur_button = READ_PORT() & BUTTON_MASK; // cur_button = READ_PORT() & BUTTON_MASK;
} }
static const EXTConfig extcfg = {
{
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1},
{EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1},
{EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOA, extcb1},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
#ifdef __WAIT_CTS_WHILE_SLEEPING__
{EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOB, extcb1},
#else
{EXT_CH_MODE_DISABLED, NULL},
#endif
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
#ifdef __USE_SD_CARD__
{EXT_CH_MODE_RISING_EDGE | EXT_CH_MODE_AUTOSTART | EXT_MODE_GPIOB, extcb1},
#else
{EXT_CH_MODE_DISABLED, NULL},
#endif
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL},
{EXT_CH_MODE_DISABLED, NULL}
}
};
void void
handle_touch_interrupt(void) handle_touch_interrupt(void)
{ {
@ -8442,8 +8407,24 @@ handle_touch_interrupt(void)
void void
ui_init() ui_init()
{ {
// Activates the EXT driver 1. /* HAL 9.1 routes STM32 EXTI through PAL line events. */
extStart(&EXTD1, &extcfg); palSetLineCallback(PAL_LINE(GPIOA, GPIOA_LEVER1), extcb1,
(void *)(uintptr_t)GPIOA_LEVER1);
palEnableLineEvent(PAL_LINE(GPIOA, GPIOA_LEVER1), PAL_EVENT_MODE_RISING_EDGE);
palSetLineCallback(PAL_LINE(GPIOA, GPIOA_PUSH), extcb1,
(void *)(uintptr_t)GPIOA_PUSH);
palEnableLineEvent(PAL_LINE(GPIOA, GPIOA_PUSH), PAL_EVENT_MODE_RISING_EDGE);
palSetLineCallback(PAL_LINE(GPIOA, GPIOA_LEVER2), extcb1,
(void *)(uintptr_t)GPIOA_LEVER2);
palEnableLineEvent(PAL_LINE(GPIOA, GPIOA_LEVER2), PAL_EVENT_MODE_RISING_EDGE);
#ifdef __WAIT_CTS_WHILE_SLEEPING__
palSetLineCallback(LINE_RX_CTS, extcb1, (void *)(uintptr_t)9U);
palEnableLineEvent(LINE_RX_CTS, PAL_EVENT_MODE_RISING_EDGE);
#endif
#ifdef __USE_SD_CARD__
palSetLineCallback(LINE_SD_CD, extcb1, (void *)(uintptr_t)12U);
palEnableLineEvent(LINE_SD_CD, PAL_EVENT_MODE_RISING_EDGE);
#endif
// Init touch subsystem // Init touch subsystem
touch_init(); touch_init();
} }

31
usbcfg.c
Unescape View File

@ -297,8 +297,10 @@ static const USBEndpointConfig ep1config = {
sduDataReceived, sduDataReceived,
0x0040, 0x0040,
0x0040, 0x0040,
&ep1instate, &ep1instate,
&ep1outstate, &ep1outstate,
1,
NULL
}; };
/** /**
@ -316,8 +318,10 @@ static const USBEndpointConfig ep2config = {
NULL, NULL,
0x0010, 0x0010,
0x0000, 0x0000,
&ep2instate, &ep2instate,
NULL, NULL,
1,
NULL
}; };
/* /*
@ -327,10 +331,8 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
extern SerialUSBDriver SDU1; extern SerialUSBDriver SDU1;
switch (event) { switch (event) {
case USB_EVENT_RESET: case USB_EVENT_ADDRESS:
return; return;
case USB_EVENT_ADDRESS:
return;
case USB_EVENT_CONFIGURED: case USB_EVENT_CONFIGURED:
chSysLockFromISR(); chSysLockFromISR();
@ -345,16 +347,21 @@ static void usb_event(USBDriver *usbp, usbevent_t event) {
chSysUnlockFromISR(); chSysUnlockFromISR();
return; return;
case USB_EVENT_SUSPEND: case USB_EVENT_RESET:
case USB_EVENT_UNCONFIGURED:
case USB_EVENT_SUSPEND:
chSysLockFromISR(); chSysLockFromISR();
/* Disconnection event on suspend.*/ /* Disconnection event on suspend.*/
sduDisconnectI(&SDU1); sduSuspendHookI(&SDU1);
chSysUnlockFromISR(); chSysUnlockFromISR();
return; return;
case USB_EVENT_WAKEUP: case USB_EVENT_WAKEUP:
return; chSysLockFromISR();
sduWakeupHookI(&SDU1);
chSysUnlockFromISR();
return;
case USB_EVENT_STALLED: case USB_EVENT_STALLED:
return; return;
} }

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