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@ -28,80 +28,79 @@
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#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
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#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
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#define ADC_CFGR1_RES_12BIT (0U << 3U)
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#define ADC_CFGR1_RES_12BIT (0U << 3U)
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#define VNA_ADC ADC1
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void adc_init(void)
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void adc_init(void)
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{
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{
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rccEnableADC1(FALSE);
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rccEnableADC1(FALSE);
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/* Ensure flag states */
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/* Ensure flag states */
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ADC1->IER = 0;
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VNA_ADC->IER = 0;
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/* Calibration procedure.*/
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/* Calibration procedure.*/
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ADC->CCR = 0;
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ADC->CCR = 0;
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if (ADC1->CR & ADC_CR_ADEN) {
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if (VNA_ADC->CR & ADC_CR_ADEN) {
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ADC1->CR |= ~ADC_CR_ADDIS; /* Disable ADC */
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VNA_ADC->CR |= ~ADC_CR_ADDIS; /* Disable ADC */
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}
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}
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while (ADC1->CR & ADC_CR_ADEN)
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while (VNA_ADC->CR & ADC_CR_ADEN)
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;
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;
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ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN;
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VNA_ADC->CFGR1 &= ~ADC_CFGR1_DMAEN;
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ADC1->CR |= ADC_CR_ADCAL;
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VNA_ADC->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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while (VNA_ADC->CR & ADC_CR_ADCAL)
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;
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;
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if (ADC1->ISR & ADC_ISR_ADRDY) {
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if (VNA_ADC->ISR & ADC_ISR_ADRDY) {
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ADC1->ISR |= ADC_ISR_ADRDY; /* clear ADRDY */
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VNA_ADC->ISR |= ADC_ISR_ADRDY; /* clear ADRDY */
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}
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}
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/* Enable ADC */
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/* Enable ADC */
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ADC1->CR |= ADC_CR_ADEN;
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VNA_ADC->CR |= ADC_CR_ADEN;
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while (!(ADC1->ISR & ADC_ISR_ADRDY))
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while (!(VNA_ADC->ISR & ADC_ISR_ADRDY))
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;
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;
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}
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}
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uint16_t adc_single_read(ADC_TypeDef *adc, uint32_t chsel)
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uint16_t adc_single_read(uint32_t chsel)
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{
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{
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/* ADC setup */
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/* ADC setup */
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adc->ISR = adc->ISR;
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VNA_ADC->ISR = VNA_ADC->ISR;
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adc->IER = 0;
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VNA_ADC->IER = 0;
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adc->TR = ADC_TR(0, 0);
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VNA_ADC->TR = ADC_TR(0, 0);
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adc->SMPR = ADC_SMPR_SMP_239P5;
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VNA_ADC->SMPR = ADC_SMPR_SMP_239P5;
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adc->CFGR1 = ADC_CFGR1_RES_12BIT;
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VNA_ADC->CFGR1 = ADC_CFGR1_RES_12BIT;
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adc->CHSELR = chsel;
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VNA_ADC->CHSELR = chsel;
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/* ADC conversion start.*/
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/* ADC conversion start.*/
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adc->CR |= ADC_CR_ADSTART;
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VNA_ADC->CR |= ADC_CR_ADSTART;
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while (adc->CR & ADC_CR_ADSTART)
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while (VNA_ADC->CR & ADC_CR_ADSTART)
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;
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;
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return adc->DR;
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return VNA_ADC->DR;
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}
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}
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int16_t adc_vbat_read(ADC_TypeDef *adc)
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int16_t adc_vbat_read(void)
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{
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{
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#define ADC_FULL_SCALE 3300
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#define ADC_FULL_SCALE 3300
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#define VBAT_DIODE_VF 500
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#define VREFINT_CAL (*((uint16_t*)0x1FFFF7BA))
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#define VREFINT_CAL (*((uint16_t*)0x1FFFF7BA))
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float vbat = 0;
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adc_stop();
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float vrefint = 0;
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float vbat = 0;
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float vrefint = 0;
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ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_VBATEN;
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ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_VBATEN;
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// VREFINT == ADC_IN17
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// VREFINT == ADC_IN17
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vrefint = adc_single_read(adc, ADC_CHSELR_CHSEL17);
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vrefint = adc_single_read(ADC_CHSELR_CHSEL17);
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// VBAT == ADC_IN18
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// VBAT == ADC_IN18
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// VBATEN enables resiter devider circuit. It consume vbat power.
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// VBATEN enables resiter devider circuit. It consume vbat power.
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vbat = adc_single_read(adc, ADC_CHSELR_CHSEL18);
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vbat = adc_single_read(ADC_CHSELR_CHSEL18);
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ADC->CCR &= ~(ADC_CCR_VREFEN | ADC_CCR_VBATEN);
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ADC->CCR &= ~(ADC_CCR_VREFEN | ADC_CCR_VBATEN);
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touch_start_watchdog();
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uint16_t vbat_raw = (ADC_FULL_SCALE * VREFINT_CAL * vbat * 2 / (vrefint * ((1<<12)-1)));
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uint16_t vbat_raw = (ADC_FULL_SCALE * VREFINT_CAL * vbat * 2 / (vrefint * ((1<<12)-1)));
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if (vbat_raw < 100) {
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if (vbat_raw < 100) {
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// maybe D2 is not installed
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// maybe D2 is not installed
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return -1;
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return -1;
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}
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}
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return vbat_raw + config.vbat_offset;
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return vbat_raw + VBAT_DIODE_VF;
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}
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}
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void adc_start_analog_watchdogd(ADC_TypeDef *adc, uint32_t chsel)
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void adc_start_analog_watchdogd(uint32_t chsel)
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{
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{
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uint32_t cfgr1;
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uint32_t cfgr1;
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@ -111,38 +110,38 @@ void adc_start_analog_watchdogd(ADC_TypeDef *adc, uint32_t chsel)
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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is enabled.*/
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adc->ISR = adc->ISR;
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VNA_ADC->ISR = VNA_ADC->ISR;
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adc->IER = ADC_IER_AWDIE;
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VNA_ADC->IER = ADC_IER_AWDIE;
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adc->TR = ADC_TR(0, TOUCH_THRESHOLD);
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VNA_ADC->TR = ADC_TR(0, TOUCH_THRESHOLD);
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adc->SMPR = ADC_SMPR_SMP_1P5;
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VNA_ADC->SMPR = ADC_SMPR_SMP_1P5;
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adc->CHSELR = chsel;
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VNA_ADC->CHSELR = chsel;
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/* ADC configuration and start.*/
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/* ADC configuration and start.*/
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adc->CFGR1 = cfgr1;
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VNA_ADC->CFGR1 = cfgr1;
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/* ADC conversion start.*/
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/* ADC conversion start.*/
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adc->CR |= ADC_CR_ADSTART;
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VNA_ADC->CR |= ADC_CR_ADSTART;
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}
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}
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void adc_stop(ADC_TypeDef *adc)
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void adc_stop(void)
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{
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{
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if (adc->CR & ADC_CR_ADEN) {
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if (VNA_ADC->CR & ADC_CR_ADEN) {
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if (adc->CR & ADC_CR_ADSTART) {
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if (VNA_ADC->CR & ADC_CR_ADSTART) {
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adc->CR |= ADC_CR_ADSTP;
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VNA_ADC->CR |= ADC_CR_ADSTP;
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while (adc->CR & ADC_CR_ADSTP)
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while (VNA_ADC->CR & ADC_CR_ADSTP)
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;
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;
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}
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}
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/* adc->CR |= ADC_CR_ADDIS;
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/* VNA_ADC->CR |= ADC_CR_ADDIS;
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while (adc->CR & ADC_CR_ADDIS)
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while (VNA_ADC->CR & ADC_CR_ADDIS)
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;*/
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;*/
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}
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}
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}
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}
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void adc_interrupt(ADC_TypeDef *adc)
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void adc_interrupt(void)
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{
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{
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uint32_t isr = adc->ISR;
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uint32_t isr = VNA_ADC->ISR;
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adc->ISR = isr;
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VNA_ADC->ISR = isr;
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if (isr & ADC_ISR_OVR) {
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if (isr & ADC_ISR_OVR) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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/* ADC overflow condition, this could happen only if the DMA is unable
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@ -159,7 +158,7 @@ OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER)
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{
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{
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OSAL_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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adc_interrupt(ADC1);
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adc_interrupt();
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OSAL_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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}
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