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@ -53,10 +53,13 @@ si5351_init(void)
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void si5351_disable_output(void)
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{
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uint8_t reg[4];
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff);
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si5351_write(SI5351_REG_16_CLK0_CONTROL, 0x80);
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si5351_write(SI5351_REG_17_CLK1_CONTROL, 0x80);
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si5351_write(SI5351_REG_18_CLK2_CONTROL, 0x80);
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reg[0] = SI5351_REG_16_CLK0_CONTROL;
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reg[1] = SI5351_CLK_POWERDOWN;
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reg[2] = SI5351_CLK_POWERDOWN;
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reg[3] = SI5351_CLK_POWERDOWN;
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si5351_bulk_write(reg, 4);
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}
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void si5351_enable_output(void)
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@ -80,8 +83,6 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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SI5351_REG_26_PLL_A,
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SI5351_REG_34_PLL_B
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};
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uint8_t baseaddr = pllreg_base[pll];
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uint32_t P1;
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uint32_t P2;
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uint32_t P3;
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@ -115,14 +116,17 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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}
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/* The datasheet is a nightmare of typos and inconsistencies here! */
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si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+1, (P3 & 0x000000FF));
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si5351_write(baseaddr+2, (P1 & 0x00030000) >> 16);
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si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+4, (P1 & 0x000000FF));
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si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) );
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si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+7, (P2 & 0x000000FF));
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uint8_t reg[9];
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reg[0] = pllreg_base[pll];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = (P1 & 0x00030000) >> 16;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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}
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void
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@ -139,7 +143,6 @@ si5351_setupMultisynth(uint8_t output,
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SI5351_REG_50_MULTISYNTH1,
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SI5351_REG_58_MULTISYNTH2,
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};
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uint8_t baseaddr = msreg_base[output];
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const uint8_t clkctrl[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_REG_17_CLK1_CONTROL,
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@ -179,14 +182,17 @@ si5351_setupMultisynth(uint8_t output,
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}
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/* Set the MSx config registers */
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si5351_write(baseaddr, (P3 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+1, (P3 & 0x000000FF));
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si5351_write(baseaddr+2, ((P1 & 0x00030000) >> 16) | div4);
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si5351_write(baseaddr+3, (P1 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+4, (P1 & 0x000000FF));
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si5351_write(baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16));
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si5351_write(baseaddr+6, (P2 & 0x0000FF00) >> 8);
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si5351_write(baseaddr+7, (P2 & 0x000000FF));
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uint8_t reg[9];
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reg[0] = msreg_base[output];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = ((P1 & 0x00030000) >> 16) | div4;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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/* Configure the clk control and enable the output */
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dat = drive_strength | SI5351_CLK_INPUT_MULTISYNTH_N;
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