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Update the ADF7021 parameters for M17.

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pull/130/head
Jonathan Naylor 5 years ago
parent 3f83f671a3
commit dc2171bef7
3 changed files with 18 additions and 17 deletions
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4
ADF7021.cpp
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@ -424,7 +424,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
break;
case STATE_YSF:
// Dev: +1 symb 900 Hz, symb rate = 4800
// Dev: +1 symb 2700/900 Hz, symb rate = 4800
ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
ADF7021_REG10 = ADF7021_REG10_YSF;
@ -685,7 +685,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
break;
case STATE_YSF:
// Dev: +1 symb 900 Hz, symb rate = 4800
// Dev: +1 symb 2700/900 Hz, symb rate = 4800
ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
ADF7021_REG10 = ADF7021_REG10_YSF;

29
ADF7021.h
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@ -1,4 +1,5 @@
/*
* Copyright (C) 2020 by Jonathan Naylor G4KLX
* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
* Copyright (C) 2017 by Danilo DB4PLE
@ -52,7 +53,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// Support for ADF7021-N version:
// #define ADF7021_N_VER
// Enable AFC support for DMR, YSF and P25 (experimental):
// Enable AFC support for DMR, YSF, P25, and M17 (experimental):
// (AFC is already enabled by default in D-Star)
// #define ADF7021_ENABLE_4FSK_AFC
@ -65,7 +66,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// R = 4
// DEMOD_CLK = 2.4576 MHz (DSTAR)
// DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25)
// DEMOD_CLK = 7.3728 MHz (YSF_H)
// DEMOD_CLK = 7.3728 MHz (YSF_H, M17)
// DEMOD CLK = 3.6864 MHz (NXDN)
// DEMOD_CLK = 7.3728 MHz (POCSAG)
#define ADF7021_PFD 3686400.0
@ -87,7 +88,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DEV_P25 22U
#endif
#define ADF7021_DEV_NXDN 13U
#define ADF7021_DEV_M17 28U // XXX FIXME
#define ADF7021_DEV_M17 28U
#define ADF7021_DEV_POCSAG 160U
// TX/RX CLOCK register (REG 03)
@ -98,7 +99,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_YSF_H 0x2A4C0493
#define ADF7021_REG3_P25 0x2A4C04D3
#define ADF7021_REG3_NXDN 0x2A4C04D3
#define ADF7021_REG3_M17 0x2A4C04D3 // XXX FIXME
#define ADF7021_REG3_M17 0x2A4C04D3
#else
#define ADF7021_REG3_DMR 0x2A4C80D3
#define ADF7021_REG3_YSF_L 0x2A4C80D3
@ -117,7 +118,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DISC_BW_YSF_H 516U // K=28
#define ADF7021_DISC_BW_P25 394U // K=32
#define ADF7021_DISC_BW_NXDN 295U // K=32
#define ADF7021_DISC_BW_M17 459U // XXX FIXME
#define ADF7021_DISC_BW_M17 393U // K=32 XXX FIXME
#define ADF7021_DISC_BW_POCSAG 406U // K=22
// Post demodulator bandwith (REG 04)
@ -144,7 +145,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_YSF 0x01FE473A
#define ADF7021_REG10_P25 0x01FE473A
#define ADF7021_REG10_NXDN 0x01FE473A
#define ADF7021_REG10_M17 0x01FE473A // XXX FIXME
#define ADF7021_REG10_M17 0x01FE473A
#if defined(ADF7021_AFC_POS)
#define AFC_OFFSET_DMR -250
#define AFC_OFFSET_YSF -250
@ -163,7 +164,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_YSF 0x049E472A
#define ADF7021_REG10_P25 0x049E472A
#define ADF7021_REG10_NXDN 0x049E472A
#define ADF7021_REG10_M17 0x049E472A // XXX FIXME
#define ADF7021_REG10_M17 0x049E472A
#define AFC_OFFSET_DMR 0
#define AFC_OFFSET_YSF 0
#define AFC_OFFSET_P25 0
@ -176,7 +177,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// R = 2
// DEMOD_CLK = 2.4576 MHz (DSTAR)
// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25)
// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25, M17)
// DEMOD_CLK = 3.0720 MHz (NXDN)
// DEMOD_CLK = 6.1440 MHz (POCSAG)
#define ADF7021_PFD 6144000.0
@ -198,7 +199,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DEV_P25 13U
#endif
#define ADF7021_DEV_NXDN 8U
#define ADF7021_DEV_M17 17U // XXX FIXME
#define ADF7021_DEV_M17 17U
#define ADF7021_DEV_POCSAG 96U
// TX/RX CLOCK register (REG 03)
@ -209,14 +210,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_YSF_H 0x29EC0493
#define ADF7021_REG3_P25 0x29EC0493
#define ADF7021_REG3_NXDN 0x29EC0493
#define ADF7021_REG3_M17 0x29EC0493 // XXX FIXME
#define ADF7021_REG3_M17 0x29EC0493
#else
#define ADF7021_REG3_DMR 0x29ECA093
#define ADF7021_REG3_YSF_L 0x29ECA093
#define ADF7021_REG3_YSF_H 0x29ECA093
#define ADF7021_REG3_P25 0x29ECA093
#define ADF7021_REG3_NXDN 0x29ECA113
#define ADF7021_REG3_M17 0x29ECA093 // XXX FIXME
#define ADF7021_REG3_M17 0x29ECA093
#endif
#define ADF7021_REG3_POCSAG 0x29EE8093
@ -228,7 +229,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DISC_BW_YSF_H 430U // K=28
#define ADF7021_DISC_BW_P25 493U // K=32
#define ADF7021_DISC_BW_NXDN 246U // K=32
#define ADF7021_DISC_BW_M17 393U // XXX FIXME
#define ADF7021_DISC_BW_M17 491U // K=32 XXX FIXME
#define ADF7021_DISC_BW_POCSAG 338U // K=22
// Post demodulator bandwith (REG 04)
@ -255,7 +256,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_YSF 0x01FE557A
#define ADF7021_REG10_P25 0x01FE557A
#define ADF7021_REG10_NXDN 0x01FE557A
#define ADF7021_REG10_M17 0x01FE557A // XXX FIXME
#define ADF7021_REG10_M17 0x01FE557A
#if defined(ADF7021_AFC_POS)
#define AFC_OFFSET_DMR -250
#define AFC_OFFSET_YSF -250
@ -274,7 +275,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_YSF 0x049E556A
#define ADF7021_REG10_P25 0x049E556A
#define ADF7021_REG10_NXDN 0x049E556A
#define ADF7021_REG10_M17 0x049E556A // XXX FIXME
#define ADF7021_REG10_M17 0x049E556A
#define AFC_OFFSET_DMR 0
#define AFC_OFFSET_YSF 0
#define AFC_OFFSET_P25 0

2
version.h
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@ -25,7 +25,7 @@
#define VER_MAJOR "1"
#define VER_MINOR "5"
#define VER_REV "1b"
#define VERSION_DATE "20201023"
#define VERSION_DATE "20201025"
#if defined(ZUMSPOT_ADF7021)
#define BOARD_INFO "ZUMspot"

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