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MMDVM_HS
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Add dummy register values for ADF7021

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pull/32/head
Andy CA6JAU 8 years ago
parent f1fe279408
commit ae4431c884
5 changed files with 34 additions and 3 deletions
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6
ADF7021.cpp
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@ -865,6 +865,11 @@ uint16_t CIO::devP25()
return (uint16_t)((ADF7021_PFD * ADF7021_DEV_P25) / (f_div * 65536));
}
uint16_t CIO::devNXDN()
{
return (uint16_t)((ADF7021_PFD * ADF7021_DEV_NXDN) / (f_div * 65536));
}
void CIO::printConf()
{
DEBUG1("MMDVM_HS FW configuration:");
@ -876,6 +881,7 @@ void CIO::printConf()
DEBUG2("YSF_H +1 sym dev (Hz):", devYSF_H());
DEBUG2("YSF_L +1 sym dev (Hz):", devYSF_L());
DEBUG2("P25 +1 sym dev (Hz):", devP25());
DEBUG2("NXDN +1 sym dev (Hz):", devNXDN());
}
#endif

24
ADF7021.h
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@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 by Jim McLaughlin KI6ZUM
* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
* Copyright (C) 2017 by Danilo DB4PLE
*
* Some of the code is based on work of Guus Van Dooren PE1PLM:
@ -84,6 +84,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#else
#define ADF7021_DEV_P25 22U
#endif
#define ADF7021_DEV_NXDN 22U
// TX/RX CLOCK register (REG 03)
#define ADF7021_REG3_DSTAR 0x2A4C4193
@ -92,11 +93,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_YSF_L 0x2A4C04D3
#define ADF7021_REG3_YSF_H 0x2A4C0493
#define ADF7021_REG3_P25 0x2A4C04D3
#define ADF7021_REG3_NXDN 0x2A4C04D3
#else
#define ADF7021_REG3_DMR 0x2A4C80D3
#define ADF7021_REG3_YSF_L 0x2A4C80D3
#define ADF7021_REG3_YSF_H 0x2A4CC093
#define ADF7021_REG3_P25 0x2A4C80D3
#define ADF7021_REG3_NXDN 0x2A4C80D3
#endif
// Discriminator bandwith, demodulator (REG 04)
@ -106,12 +109,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DISC_BW_YSF_L 393U // K=32
#define ADF7021_DISC_BW_YSF_H 516U // K=28
#define ADF7021_DISC_BW_P25 394U // K=32
#define ADF7021_DISC_BW_NXDN 394U // K=32
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 10U
#define ADF7021_POST_BW_DMR 150U
#define ADF7021_POST_BW_YSF 20U
#define ADF7021_POST_BW_P25 6U
#define ADF7021_POST_BW_NXDN 6U
// IF filter (REG 05)
#define ADF7021_REG5 0x000024F5
@ -126,22 +131,27 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_DMR 0x01FE473A
#define ADF7021_REG10_YSF 0x01FE473A
#define ADF7021_REG10_P25 0x01FE473A
#define ADF7021_REG10_NXDN 0x01FE473A
#if defined(ADF7021_AFC_POS)
#define AFC_OFFSET_DMR -250
#define AFC_OFFSET_YSF -250
#define AFC_OFFSET_P25 -250
#define AFC_OFFSET_NXDN -250
#else
#define AFC_OFFSET_DMR 250
#define AFC_OFFSET_YSF 250
#define AFC_OFFSET_P25 250
#define AFC_OFFSET_NXDN 250
#endif
#else
#define ADF7021_REG10_DMR 0x049E472A
#define ADF7021_REG10_YSF 0x049E472A
#define ADF7021_REG10_P25 0x049E472A
#define ADF7021_REG10_NXDN 0x049E472A
#define AFC_OFFSET_DMR 0
#define AFC_OFFSET_YSF 0
#define AFC_OFFSET_P25 0
#define AFC_OFFSET_NXDN 0
#endif
/****** Support for 12.2880 MHz TCXO ******/
@ -168,6 +178,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#else
#define ADF7021_DEV_P25 13U
#endif
#define ADF7021_DEV_NXDN 13U
// TX/RX CLOCK register (REG 03)
#define ADF7021_REG3_DSTAR 0x29EC4153
@ -176,11 +187,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_YSF_L 0x29EC0493
#define ADF7021_REG3_YSF_H 0x29EC0493
#define ADF7021_REG3_P25 0x29EC0493
#define ADF7021_REG3_NXDN 0x29EC0493
#else
#define ADF7021_REG3_DMR 0x29ECA093
#define ADF7021_REG3_YSF_L 0x29ECA093
#define ADF7021_REG3_YSF_H 0x29ECA093
#define ADF7021_REG3_P25 0x29ECA093
#define ADF7021_REG3_NXDN 0x29ECA093
#endif
// Discriminator bandwith, demodulator (REG 04)
@ -190,12 +203,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_DISC_BW_YSF_L 491U // K=32
#define ADF7021_DISC_BW_YSF_H 430U // K=28
#define ADF7021_DISC_BW_P25 493U // K=32
#define ADF7021_DISC_BW_NXDN 493U // K=32
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 10U
#define ADF7021_POST_BW_DMR 150U
#define ADF7021_POST_BW_YSF 20U
#define ADF7021_POST_BW_P25 6U
#define ADF7021_POST_BW_NXDN 6U
// IF filter (REG 05)
#define ADF7021_REG5 0x00001ED5
@ -210,22 +225,27 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG10_DMR 0x01FE557A
#define ADF7021_REG10_YSF 0x01FE557A
#define ADF7021_REG10_P25 0x01FE557A
#define ADF7021_REG10_NXDN 0x01FE557A
#if defined(ADF7021_AFC_POS)
#define AFC_OFFSET_DMR -250
#define AFC_OFFSET_YSF -250
#define AFC_OFFSET_P25 -250
#define AFC_OFFSET_NXDN -250
#else
#define AFC_OFFSET_DMR 250
#define AFC_OFFSET_YSF 250
#define AFC_OFFSET_P25 250
#define AFC_OFFSET_NXDN 250
#endif
#else
#define ADF7021_REG10_DMR 0x049E556A
#define ADF7021_REG10_YSF 0x049E556A
#define ADF7021_REG10_P25 0x049E556A
#define ADF7021_REG10_NXDN 0x049E556A
#define AFC_OFFSET_DMR 0
#define AFC_OFFSET_YSF 0
#define AFC_OFFSET_P25 0
#define AFC_OFFSET_NXDN 0
#endif
#endif
@ -238,6 +258,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_SLICER_TH_YSF_L 35U
#define ADF7021_SLICER_TH_YSF_H 69U
#define ADF7021_SLICER_TH_P25 43U
#define ADF7021_SLICER_TH_NXDN 43U
#else
@ -246,6 +267,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_SLICER_TH_YSF_L 38U
#define ADF7021_SLICER_TH_YSF_H 75U
#define ADF7021_SLICER_TH_P25 47U
#define ADF7021_SLICER_TH_NXDN 47U
#endif

5
IO.h
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@ -1,6 +1,6 @@
/*
* Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
* Copyright (C) 2016,2017 by Andy Uribe CA6JAU
* Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
* Copyright (C) 2017 by Danilo DB4PLE
* This program is free software; you can redistribute it and/or modify
@ -127,6 +127,7 @@ public:
uint16_t devYSF_H(void);
uint16_t devYSF_L(void);
uint16_t devP25(void);
uint16_t devNXDN(void);
void printConf();
private:
@ -144,7 +145,7 @@ private:
uint32_t m_scanPauseCnt;
uint8_t m_scanPos;
uint8_t m_TotalModes;
MMDVM_STATE m_Modes[4];
MMDVM_STATE m_Modes[5];
bool m_ledValue;
volatile uint32_t m_watchdog;

1
Utils.cpp
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 by Jonathan Naylor G4KLX
* Copyright (C) 2017 by Andy Uribe CA6JAU
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

1
Utils.h
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
* Copyright (C) 2017 by Andy Uribe CA6JAU
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

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