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@ -44,10 +44,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_PFD 3686400.0
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 42U
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#define ADF7021_DEV_DMR 24U
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#define ADF7021_DEV_DSTAR 43U
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#define ADF7021_DEV_DMR 23U
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#define ADF7021_DEV_YSF 32U
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#define ADF7021_DEV_P25 22U
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#define ADF7021_DEV_P25 21U
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x2A4C4193
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@ -129,6 +129,52 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_SLICER_TH_YSF 59U
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#define ADF7021_SLICER_TH_P25 45U
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/****** Support for 12.2880 MHz TCXO ******/
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#elif defined(ADF7021_12_2880)
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// R = 4
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#define ADF7021_PFD 3072000.0
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 51U
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#define ADF7021_DEV_DMR 28U
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#define ADF7021_DEV_YSF 38U
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#define ADF7021_DEV_P25 26U
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x29EC4153
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#define ADF7021_REG3_DMR 0x29ECA093
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#define ADF7021_REG3_YSF 0x29ECA093
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#define ADF7021_REG3_P25 0x29ECA093
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// Discriminator bandwith, demodulator (REG 04)
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 522U // K=85
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#define ADF7021_DISC_BW_DMR 492U // K=32
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#define ADF7021_DISC_BW_YSF 430U // K=28
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#define ADF7021_DISC_BW_P25 492U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 65U
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#define ADF7021_POST_BW_YSF 65U
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#define ADF7021_POST_BW_P25 65U
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// IF filter (REG 05)
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#define ADF7021_REG5 0x00001ED5
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// IF CAL (fine cal, defaults) (REG 06)
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#define ADF7021_REG6 0x0505EBB6
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// AFC (off, defaults) (REG 10)
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#define ADF7021_REG10 0x3296556A
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// Slicer threshold for 4FSK demodulator (REG 13)
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 51U
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#define ADF7021_SLICER_TH_YSF 59U
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#define ADF7021_SLICER_TH_P25 45U
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#endif
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#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
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