implement opcode for controlling DMR CACH Access Type flag;

usb-support 2022-10-02
Bryan Biedenkapp 3 years ago
parent 99ef4965be
commit db39b8fe31

@ -343,6 +343,24 @@ void SerialPort::process()
#endif
break;
case CMD_DMR_CACH_AT_CTRL:
#if defined(DUPLEX)
if (m_dmrEnable) {
err = RSN_INVALID_REQUEST;
if (m_len == 4U) {
dmrTX.setIgnoreCACH_AT(m_buffer[3U]);
err = RSN_OK;
}
}
if (err != RSN_OK) {
DEBUG2("SerialPort: process(): received invalid DMR CACH AT Control", err);
sendNAK(err);
}
#else
sendNAK(RSN_INVALID_REQUEST);
#endif
break;
/** Project 25 */
case CMD_P25_DATA:
if (m_p25Enable) {

@ -90,6 +90,7 @@ enum DVM_COMMANDS {
CMD_DMR_SHORTLC = 0x1CU,
CMD_DMR_START = 0x1DU,
CMD_DMR_ABORT = 0x1EU,
CMD_DMR_CACH_AT_CTRL = 0x1FU,
CMD_P25_DATA = 0x31U,
CMD_P25_LOST = 0x32U,

@ -14,7 +14,7 @@
* Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
* Copyright (C) 2016 by Colin Durbridge G4EML
* Copyright (C) 2017 by Andy Uribe CA6JAU
* Copyright (C) 2021 by Bryan Biedenkapp N2PLL
* Copyright (C) 2021-2022 by Bryan Biedenkapp N2PLL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -81,6 +81,7 @@ DMRTX::DMRTX() :
m_frameCount(0U),
m_abortCount(),
m_abort(),
m_cachATControl(0U),
m_controlPrev(MARK_NONE)
{
::memcpy(m_newShortLC, EMPTY_SHORT_LC, 12U);
@ -306,6 +307,18 @@ uint8_t DMRTX::getSpace2() const
return m_fifo[1U].getSpace() / (DMR_FRAME_LENGTH_BYTES + 2U);
}
/// <summary>
/// Sets the ignore flags for setting the CACH Access Type bit.
/// </summary>
/// <param name="slot"></param>
void DMRTX::setIgnoreCACH_AT(uint8_t slot)
{
m_cachATControl = slot;
if (m_cachATControl > 3U) {
m_cachATControl = 0U;
}
}
/// <summary>
/// Sets the DMR color code.
/// </summary>
@ -441,8 +454,16 @@ void DMRTX::createCACH(uint8_t txSlotIndex, uint8_t rxSlotIndex)
m_markBuffer[2U] = rxSlotIndex == 1U ? MARK_SLOT1 : MARK_SLOT2;
bool at = false;
if (m_frameCount >= STARTUP_COUNT)
if (m_frameCount >= STARTUP_COUNT) {
if (m_cachATControl == 0U) {
at = m_fifo[rxSlotIndex].getData() > 0U;
} else {
if (m_cachATControl != 3U && m_cachATControl != (rxSlotIndex + 1U)) {
at = m_fifo[rxSlotIndex].getData() > 0U;
}
}
}
bool tc = txSlotIndex == 1U;
bool ls0 = true; // For 1 and 2
bool ls1 = true;

@ -14,7 +14,7 @@
* Copyright (C) 2015,2016,2017 by Jonathan Naylor G4KLX
* Copyright (C) 2016 by Colin Durbridge G4EML
* Copyright (C) 2017 by Andy Uribe CA6JAU
* Copyright (C) 2021 by Bryan Biedenkapp N2PLL
* Copyright (C) 2021-2022 by Bryan Biedenkapp N2PLL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -85,6 +85,8 @@ namespace dmr
/// <summary>Helper to get how much space the slot 2 ring buffer has for samples.</summary>
uint8_t getSpace2() const;
/// <summary>Sets the ignore flags for setting the CACH Access Type bit.</summary>
void setIgnoreCACH_AT(uint8_t slot);
/// <summary>Sets the DMR color code.</summary>
void setColorCode(uint8_t colorCode);
@ -117,6 +119,8 @@ namespace dmr
uint32_t m_abortCount[2U];
bool m_abort[2U];
uint8_t m_cachATControl;
uint8_t m_controlPrev;
/// <summary></summary>

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