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@ -14,7 +14,7 @@
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* Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
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* Copyright (C) 2016 by Colin Durbridge G4EML
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* Copyright (C) 2017 by Andy Uribe CA6JAU
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* Copyright (C) 2021 by Bryan Biedenkapp N2PLL
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* Copyright (C) 2021-2022 by Bryan Biedenkapp N2PLL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -81,6 +81,7 @@ DMRTX::DMRTX() :
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m_frameCount(0U),
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m_abortCount(),
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m_abort(),
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m_cachATControl(0U),
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m_controlPrev(MARK_NONE)
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{
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::memcpy(m_newShortLC, EMPTY_SHORT_LC, 12U);
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@ -306,6 +307,18 @@ uint8_t DMRTX::getSpace2() const
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return m_fifo[1U].getSpace() / (DMR_FRAME_LENGTH_BYTES + 2U);
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}
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/// <summary>
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/// Sets the ignore flags for setting the CACH Access Type bit.
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/// </summary>
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/// <param name="slot"></param>
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void DMRTX::setIgnoreCACH_AT(uint8_t slot)
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{
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m_cachATControl = slot;
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if (m_cachATControl > 3U) {
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m_cachATControl = 0U;
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}
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}
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/// <summary>
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/// Sets the DMR color code.
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/// </summary>
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@ -441,8 +454,16 @@ void DMRTX::createCACH(uint8_t txSlotIndex, uint8_t rxSlotIndex)
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m_markBuffer[2U] = rxSlotIndex == 1U ? MARK_SLOT1 : MARK_SLOT2;
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bool at = false;
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if (m_frameCount >= STARTUP_COUNT)
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if (m_frameCount >= STARTUP_COUNT) {
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if (m_cachATControl == 0U) {
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at = m_fifo[rxSlotIndex].getData() > 0U;
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} else {
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if (m_cachATControl != 3U && m_cachATControl != (rxSlotIndex + 1U)) {
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at = m_fifo[rxSlotIndex].getData() > 0U;
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}
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}
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}
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bool tc = txSlotIndex == 1U;
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bool ls0 = true; // For 1 and 2
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bool ls1 = true;
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