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refactor ADF debug trace logging; correct some ADF IF filter configuration; correct some ADF data inversion configuration; correct some issues with DMR slot RX; remove m_endPtr from NXDNRX;

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pull/4/head
Bryan Biedenkapp 2 years ago
parent c491e9344d
commit c75ff52d0c
6 changed files with 65 additions and 47 deletions
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50
ADF7021.cpp
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@ -299,7 +299,7 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
{ {
uint32_t txFrequencyTmp, rxFrequencyTmp; uint32_t txFrequencyTmp, rxFrequencyTmp;
DEBUG4("IO::rf1Conf(): configuring ADF for Tx/Rx; modemState/reset/rxGain", modemState, reset, m_gainMode); DEBUG4("IO::rf1Conf(): ADF1 (Tx/Rx); modemState/reset/rxGain", modemState, reset, m_gainMode);
#if defined (ZUMSPOT_ADF7021) || defined(SKYBRIDGE_HS) #if defined (ZUMSPOT_ADF7021) || defined(SKYBRIDGE_HS)
io.checkBand(m_rxFrequency, m_txFrequency); io.checkBand(m_rxFrequency, m_txFrequency);
@ -378,12 +378,16 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
AD7021_CONTROL = ADF7021_REG3; AD7021_CONTROL = ADF7021_REG3;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG3("IO::rf1Conf(): ADF1 REG3 =", (ADF7021_REG3 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
/* /*
** Demodulator Setup (Register 4) ** Demodulator Setup (Register 4)
*/ */
AD7021_CONTROL = ADF7021_REG4; AD7021_CONTROL = ADF7021_REG4;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG3("IO::rf1Conf(): ADF1 REG4 =", (ADF7021_REG4 >> 16 & 0xFFFFU), (ADF7021_REG4 & 0xFFFFU));
/* /*
** IF Fine Cal Setup (Register 6) ** IF Fine Cal Setup (Register 6)
*/ */
@ -410,6 +414,8 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
AD7021_CONTROL = ADF7021_REG2; AD7021_CONTROL = ADF7021_REG2;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG3("IO::rf1Conf(): ADF1 REG2 =", (ADF7021_REG2 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
/* /*
** Test DAC (Register 14) ** Test DAC (Register 14)
*/ */
@ -446,6 +452,8 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
AD7021_CONTROL = ADF7021_REG10; AD7021_CONTROL = ADF7021_REG10;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG3("IO::rf1Conf(): ADF1 REG10 =", (ADF7021_REG10 >> 16 & 0xFFFFU), (ADF7021_REG10 & 0xFFFFU));
/* /*
** Sync Word Detect (Register 11) ** Sync Word Detect (Register 11)
*/ */
@ -464,6 +472,8 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
AD7021_CONTROL = ADF7021_REG13; AD7021_CONTROL = ADF7021_REG13;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG3("IO::rf1Conf(): ADF1 REG13 =", (ADF7021_REG13 >> 16 & 0xFFFFU), (ADF7021_REG13 & 0xFFFFU));
/* /*
** Test Mode (Register 15) ** Test Mode (Register 15)
*/ */
@ -493,7 +503,7 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
/// <param name="reset"></param> /// <param name="reset"></param>
void IO::rf2Conf(DVM_STATE modemState) void IO::rf2Conf(DVM_STATE modemState)
{ {
DEBUG3("IO::rf2Conf(): configuring 2nd ADF for Rx; modemState/rxGain", modemState, m_gainMode); DEBUG3("IO::rf2Conf(): ADF2 (Rx); modemState/rxGain", modemState, m_gainMode);
// configure ADF Tx/RX // configure ADF Tx/RX
configureTxRx(modemState); configureTxRx(modemState);
@ -511,12 +521,16 @@ void IO::rf2Conf(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG3; AD7021_CONTROL = ADF7021_REG3;
AD7021_2_IOCTL(); AD7021_2_IOCTL();
DEBUG3("IO::rf2Conf(): ADF2 REG3 =", (ADF7021_REG3 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
/* /*
** Demodulator Setup (Register 4) ** Demodulator Setup (Register 4)
*/ */
AD7021_CONTROL = ADF7021_REG4; AD7021_CONTROL = ADF7021_REG4;
AD7021_2_IOCTL(); AD7021_2_IOCTL();
DEBUG3("IO::rf2Conf(): ADF2 REG4 =", (ADF7021_REG4 >> 16 & 0xFFFFU), (ADF7021_REG4 & 0xFFFFU));
/* /*
** IF Fine Cal Setup (Register 6) ** IF Fine Cal Setup (Register 6)
*/ */
@ -545,6 +559,8 @@ void IO::rf2Conf(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG2; AD7021_CONTROL = ADF7021_REG2;
AD7021_2_IOCTL(); AD7021_2_IOCTL();
DEBUG3("IO::rf2Conf(): ADF2 REG2 =", (ADF7021_REG2 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
/* /*
** Test DAC (Register 14) ** Test DAC (Register 14)
*/ */
@ -577,6 +593,8 @@ void IO::rf2Conf(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG10; AD7021_CONTROL = ADF7021_REG10;
AD7021_2_IOCTL(); AD7021_2_IOCTL();
DEBUG3("IO::rf2Conf(): ADF2 REG10 =", (ADF7021_REG10 >> 16 & 0xFFFFU), (ADF7021_REG10 & 0xFFFFU));
/* /*
** Sync Word Detect (Register 11) ** Sync Word Detect (Register 11)
*/ */
@ -595,6 +613,8 @@ void IO::rf2Conf(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG13; AD7021_CONTROL = ADF7021_REG13;
AD7021_2_IOCTL(); AD7021_2_IOCTL();
DEBUG3("IO::rf2Conf(): ADF2 REG13 =", (ADF7021_REG13 >> 16 & 0xFFFFU), (ADF7021_REG13 & 0xFFFFU));
/* /*
** Test Mode (Register 15) ** Test Mode (Register 15)
*/ */
@ -636,8 +656,8 @@ void IO::setRFAdjust(int8_t dmrDiscBWAdj, int8_t p25DiscBWAdj, int8_t nxdnDiscBW
m_p25PostBWAdj = p25PostBWAdj; m_p25PostBWAdj = p25PostBWAdj;
m_nxdnPostBWAdj = nxdnPostBWADJ; m_nxdnPostBWAdj = nxdnPostBWADJ;
DEBUG4("IO::setRFAdjust(): setting RF adjustment, discBW", dmrDiscBWAdj, p25DiscBWAdj, nxdnDiscBWAdj); DEBUG4("IO::setRFAdjust(): RF adjustment, discBW", dmrDiscBWAdj, p25DiscBWAdj, nxdnDiscBWAdj);
DEBUG4("IO::setRFAdjust(): setting RF adjustment, postBW", dmrPostBWAdj, p25PostBWAdj, nxdnPostBWADJ); DEBUG4("IO::setRFAdjust(): RF adjustment, postBW", dmrPostBWAdj, p25PostBWAdj, nxdnPostBWADJ);
} }
/// <summary> /// <summary>
@ -654,7 +674,7 @@ void IO::setAFCParams(bool afcEnable, uint8_t afcKI, uint8_t afcKP, uint8_t afcR
m_afcKP = afcKP; m_afcKP = afcKP;
m_afcRange = afcRange; m_afcRange = afcRange;
DEBUG5("IO::setAFCParams(): setting AFC params", afcEnable, afcKI, afcKP, afcRange); DEBUG5("IO::setAFCParams(): AFC params", afcEnable, afcKI, afcKP, afcRange);
} }
/// <summary> /// <summary>
@ -673,7 +693,7 @@ void IO::updateCal(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG1; AD7021_CONTROL = ADF7021_REG1;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
// configure ADF Tx/RX // configure ADF Tx/Rx
configureTxRx(modemState); configureTxRx(modemState);
/* /*
@ -712,7 +732,7 @@ void IO::updateCal(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG2; AD7021_CONTROL = ADF7021_REG2;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG2("IO::updateCal(): updating ADF calibration; modemState", modemState); DEBUG2("IO::updateCal(): ADF calibration; modemState", modemState);
if (m_tx) if (m_tx)
setTX(); setTX();
@ -881,7 +901,7 @@ void IO::configureBand()
else else
f_div = 1U; f_div = 1U;
DEBUG3("IO::configureBand(): configuring ADF freq band; reg1/f_div", ADF7021_REG1, f_div); DEBUG3("IO::configureBand(): ADF freq band; reg1/f_div", ADF7021_REG1, f_div);
} }
/// <summary> /// <summary>
@ -1093,7 +1113,7 @@ void IO::configureTxRx(DVM_STATE modemState)
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion
ADF7021_REG4 |= (uint32_t)(dmrDiscBW & 0x3FFU) << 10; // Discriminator BW ADF7021_REG4 |= (uint32_t)(dmrDiscBW & 0x3FFU) << 10; // Discriminator BW
ADF7021_REG4 |= (uint32_t)(dmrPostBW & 0xFFFU) << 20; // Post Demod BW ADF7021_REG4 |= (uint32_t)(dmrPostBW & 0xFFFU) << 20; // Post Demod BW
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_125K << 30; // IF Filter ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_25K << 30; // IF Filter
/* /*
** 3FSK/4FSK Demod (Register 13) ** 3FSK/4FSK Demod (Register 13)
@ -1109,7 +1129,7 @@ void IO::configureTxRx(DVM_STATE modemState)
ADF7021_REG2 |= (uint32_t)ADF7021_REG2_PA_DEF << 7; // PA Enable & PA Bias ADF7021_REG2 |= (uint32_t)ADF7021_REG2_PA_DEF << 7; // PA Enable & PA Bias
ADF7021_REG2 |= (uint32_t)(m_rfPower & 0x3FU) << 13; // PA Level (0 - Off, 63 - 13 dBm) ADF7021_REG2 |= (uint32_t)(m_rfPower & 0x3FU) << 13; // PA Level (0 - Off, 63 - 13 dBm)
ADF7021_REG2 |= (uint32_t)(dmrDev / div2) << 19; // Freq. Deviation ADF7021_REG2 |= (uint32_t)(dmrDev / div2) << 19; // Freq. Deviation
ADF7021_REG2 |= (uint32_t)ADF7021_REG2_INV_CLKDAT << 28; // Clock/Data Inversion ADF7021_REG2 |= (uint32_t)ADF7021_REG2_INV_DATA << 28; // Data Inversion
ADF7021_REG2 |= (uint32_t)ADF7021_REG2_RC_5 << 30; // R-Cosine Alpha ADF7021_REG2 |= (uint32_t)ADF7021_REG2_RC_5 << 30; // R-Cosine Alpha
} }
break; break;
@ -1172,7 +1192,7 @@ void IO::configureTxRx(DVM_STATE modemState)
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion
ADF7021_REG4 |= (uint32_t)(p25DiscBW & 0x3FFU) << 10; // Discriminator BW ADF7021_REG4 |= (uint32_t)(p25DiscBW & 0x3FFU) << 10; // Discriminator BW
ADF7021_REG4 |= (uint32_t)(p25PostBW & 0xFFFU) << 20; // Post Demod BW ADF7021_REG4 |= (uint32_t)(p25PostBW & 0xFFFU) << 20; // Post Demod BW
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_125K << 30; // IF Filter ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_25K << 30; // IF Filter
/* /*
** 3FSK/4FSK Demod (Register 13) ** 3FSK/4FSK Demod (Register 13)
@ -1263,7 +1283,7 @@ void IO::configureTxRx(DVM_STATE modemState)
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion ADF7021_REG4 |= (uint32_t)ADF7021_REG4_INV_CLKDAT << 8; // Clock/Data Inversion
ADF7021_REG4 |= (uint32_t)(nxdnDiscBW & 0x3FFU) << 10; // Discriminator BW ADF7021_REG4 |= (uint32_t)(nxdnDiscBW & 0x3FFU) << 10; // Discriminator BW
ADF7021_REG4 |= (uint32_t)(nxdnPostBW & 0xFFFU) << 20; // Post Demod BW ADF7021_REG4 |= (uint32_t)(nxdnPostBW & 0xFFFU) << 20; // Post Demod BW
ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_125K << 30; // IF Filter ADF7021_REG4 |= (uint32_t)ADF7021_REG4_IF_1875K << 30; // IF Filter
/* /*
** 3FSK/4FSK Demod (Register 13) ** 3FSK/4FSK Demod (Register 13)
@ -1363,12 +1383,6 @@ void IO::configureTxRx(DVM_STATE modemState)
break; break;
} }
DEBUG3("IO::configureTxRx(): ADF7021_REG3 =", (ADF7021_REG3 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
DEBUG3("IO::configureTxRx(): ADF7021_REG10 =", (ADF7021_REG10 >> 16 & 0xFFFFU), (ADF7021_REG10 & 0xFFFFU));
DEBUG3("IO::configureTxRx(): ADF7021_REG4 =", (ADF7021_REG4 >> 16 & 0xFFFFU), (ADF7021_REG4 & 0xFFFFU));
DEBUG3("IO::configureTxRx(): ADF7021_REG13 =", (ADF7021_REG13 >> 16 & 0xFFFFU), (ADF7021_REG13 & 0xFFFFU));
DEBUG3("IO::configureTxRx(): ADF7021_REG2 =", (ADF7021_REG2 >> 16 & 0xFFFFU), (ADF7021_REG3 & 0xFFFFU));
DEBUG5("IO::configureTxRx(): ADF Tx/Rx values; dmrDiscBW/dmrPostBW/p25DiscBW/p25PostBW", dmrDiscBW, dmrPostBW, p25DiscBW, p25PostBW); DEBUG5("IO::configureTxRx(): ADF Tx/Rx values; dmrDiscBW/dmrPostBW/p25DiscBW/p25PostBW", dmrDiscBW, dmrPostBW, p25DiscBW, p25PostBW);
DEBUG3("IO::configureTxRx(): ADF Tx/Rx values; nxdnDiscBW/nxdnPostBW", nxdnDiscBW, nxdnPostBW); DEBUG3("IO::configureTxRx(): ADF Tx/Rx values; nxdnDiscBW/nxdnPostBW", nxdnDiscBW, nxdnPostBW);
DEBUG5("IO::configureTxRx(): ADF Tx/Rx values; dmrSymDev/p25SymDev/nxdnSymDev/rfPower", (uint16_t)((ADF7021_PFD * dmrDev) / (f_div * 65536)), DEBUG5("IO::configureTxRx(): ADF Tx/Rx values; dmrSymDev/p25SymDev/nxdnSymDev/rfPower", (uint16_t)((ADF7021_PFD * dmrDev) / (f_div * 65536)),

2
IO.cpp
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@ -110,8 +110,6 @@ void IO::process()
if (m_modemState == STATE_DMR && m_tx) if (m_modemState == STATE_DMR && m_tx)
dmrTX.setStart(false); dmrTX.setStart(false);
#endif #endif
m_modemState = STATE_IDLE;
setMode(m_modemState);
} }
m_watchdog = 0U; m_watchdog = 0U;

29
dmr/DMRSlotRX.cpp
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@ -94,17 +94,12 @@ void DMRSlotRX::start()
/// </summary> /// </summary>
void DMRSlotRX::reset() void DMRSlotRX::reset()
{ {
m_syncPtr = 0U;
m_dataPtr = 0U; m_dataPtr = 0U;
m_delayPtr = 0U; m_delayPtr = 0U;
m_bitBuffer = 0U; m_bitBuffer = 0U;
m_control = CONTROL_NONE; resetSlot();
m_syncCount = 0U;
m_state = DMRRXS_NONE;
m_startPtr = 0U;
m_endPtr = NOENDPTR;
} }
/// <summary> /// <summary>
@ -228,8 +223,7 @@ bool DMRSlotRX::databit(bool bit)
if (m_syncCount >= MAX_SYNC_LOST_FRAMES) { if (m_syncCount >= MAX_SYNC_LOST_FRAMES) {
DEBUG1("DMRSlotRX: databit(): sync timeout, lost lock"); DEBUG1("DMRSlotRX: databit(): sync timeout, lost lock");
serial.writeDMRLost(m_slot); serial.writeDMRLost(m_slot);
m_state = DMRRXS_NONE; resetSlot();
m_endPtr = NOENDPTR;
} }
} }
@ -251,6 +245,9 @@ bool DMRSlotRX::databit(bool bit)
} }
} }
} }
// end of this slot, reset some items for the next slot
m_control = CONTROL_NONE;
} }
m_dataPtr++; m_dataPtr++;
@ -347,6 +344,22 @@ void DMRSlotRX::correlateSync()
} }
} }
/// <summary>
///
/// </summary>
void DMRSlotRX::resetSlot()
{
m_syncPtr = 0U;
m_control = CONTROL_NONE;
m_syncCount = 0U;
m_state = DMRRXS_NONE;
m_startPtr = 0U;
m_endPtr = NOENDPTR;
m_type = 0U;
m_n = 0U;
}
/// <summary> /// <summary>
/// ///
/// </summary> /// </summary>

2
dmr/DMRSlotRX.h
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@ -102,6 +102,8 @@ namespace dmr
/// <summary>Frame synchronization correlator.</summary> /// <summary>Frame synchronization correlator.</summary>
void correlateSync(); void correlateSync();
/// <summary></summary>
void resetSlot();
/// <summary></summary> /// <summary></summary>
void bitsToBytes(uint16_t start, uint8_t count, uint8_t* buffer); void bitsToBytes(uint16_t start, uint8_t count, uint8_t* buffer);

27
nxdn/NXDNRX.cpp
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@ -57,7 +57,6 @@ NXDNRX::NXDNRX() :
m_outBuffer(), m_outBuffer(),
m_buffer(NULL), m_buffer(NULL),
m_dataPtr(0U), m_dataPtr(0U),
m_endPtr(NOENDPTR),
m_lostCount(0U), m_lostCount(0U),
m_state(NXDNRXS_NONE) m_state(NXDNRXS_NONE)
{ {
@ -73,8 +72,6 @@ void NXDNRX::reset()
m_bitBuffer = 0x00U; m_bitBuffer = 0x00U;
m_dataPtr = 0U; m_dataPtr = 0U;
m_endPtr = NOENDPTR;
m_lostCount = 0U; m_lostCount = 0U;
m_state = NXDNRXS_NONE; m_state = NXDNRXS_NONE;
@ -90,23 +87,13 @@ void NXDNRX::databit(bool bit)
if (bit) if (bit)
m_bitBuffer |= 0x01U; m_bitBuffer |= 0x01U;
if (m_state != NXDNRXS_NONE) {
_WRITE_BIT(m_buffer, m_dataPtr, bit);
m_dataPtr++;
if (m_dataPtr > NXDN_FRAME_LENGTH_BITS) {
reset();
}
}
if (m_state == NXDNRXS_DATA) { if (m_state == NXDNRXS_DATA) {
processData(bit); processData(bit);
} }
else { else {
bool ret = correlateSync(true); bool ret = correlateSync(true);
if (ret) { if (ret) {
DEBUG3("NXDNRX: databit(): dataPtr/endPtr", m_dataPtr, m_endPtr); DEBUG2("NXDNRX: databit(): dataPtr", m_dataPtr);
m_state = NXDNRXS_DATA; m_state = NXDNRXS_DATA;
} }
@ -124,13 +111,20 @@ void NXDNRX::databit(bool bit)
/// <param name="bit"></param> /// <param name="bit"></param>
void NXDNRX::processData(bool bit) void NXDNRX::processData(bool bit)
{ {
_WRITE_BIT(m_buffer, m_dataPtr, bit);
m_dataPtr++;
if (m_dataPtr > NXDN_FRAME_LENGTH_BITS) {
reset();
}
// only search for a sync in the right place +-2 bits // only search for a sync in the right place +-2 bits
if (m_dataPtr >= (NXDN_FSW_LENGTH_BITS - 2U) && m_dataPtr <= (NXDN_FSW_LENGTH_BITS + 2U)) { if (m_dataPtr >= (NXDN_FSW_LENGTH_BITS - 2U) && m_dataPtr <= (NXDN_FSW_LENGTH_BITS + 2U)) {
correlateSync(); correlateSync();
} }
// process frame // process frame
if (m_dataPtr == m_endPtr) { if (m_dataPtr == NXDN_FRAME_LENGTH_BITS) {
m_lostCount--; m_lostCount--;
// we've not seen a data sync for too long, signal sync lost and change to NXDNRXS_NONE // we've not seen a data sync for too long, signal sync lost and change to NXDNRXS_NONE
@ -187,9 +181,8 @@ bool NXDNRX::correlateSync(bool first)
m_lostCount = MAX_FSW_FRAMES; m_lostCount = MAX_FSW_FRAMES;
m_dataPtr = NXDN_FSW_LENGTH_BITS; m_dataPtr = NXDN_FSW_LENGTH_BITS;
m_endPtr = NXDN_FRAME_LENGTH_BITS;
DEBUG3("NXDNRX: correlateSync(): dataPtr/endPtr", m_dataPtr, m_endPtr); DEBUG2("NXDNRX: correlateSync(): dataPtr", m_dataPtr);
return true; return true;
} }

2
nxdn/NXDNRX.h
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@ -68,8 +68,6 @@ namespace nxdn
uint16_t m_dataPtr; uint16_t m_dataPtr;
uint16_t m_endPtr;
uint16_t m_lostCount; uint16_t m_lostCount;
NXDNRX_STATE m_state; NXDNRX_STATE m_state;

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