Digital_Voice_Modem_Project
/
dvmfirmware-hs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

reorganize DMR sync detection; make DMR receive IF bandwidth 12.5khz; implement fix for setting discriminator and post BW settings; fix debug messages;

Browse Source
pull/2/head
Bryan Biedenkapp 4 years ago
parent 03f4e59918
commit 4db35fc673
5 changed files with 173 additions and 114 deletions
Show Stats Download Patch File Download Diff File

107
ADF7021.cpp
Unescape View File

@ -292,7 +292,7 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
uint32_t txFrequencyTmp, rxFrequencyTmp; uint32_t txFrequencyTmp, rxFrequencyTmp;
DEBUG3("IO: rf1Conf(): configuring ADF for Tx/Rx; modemState/reset", modemState, reset); DEBUG3("IO::rf1Conf(): configuring ADF for Tx/Rx; modemState/reset", modemState, reset);
#if defined (ZUMSPOT_ADF7021) || defined(SKYBRIDGE_HS) #if defined (ZUMSPOT_ADF7021) || defined(SKYBRIDGE_HS)
io.checkBand(m_rxFrequency, m_txFrequency); io.checkBand(m_rxFrequency, m_txFrequency);
@ -492,7 +492,7 @@ void IO::rf1Conf(DVM_STATE modemState, bool reset)
/// <param name="reset"></param> /// <param name="reset"></param>
void IO::rf2Conf(DVM_STATE modemState) void IO::rf2Conf(DVM_STATE modemState)
{ {
DEBUG2("IO: rf2Conf(): configuring 2nd ADF for Rx; modemState", modemState); DEBUG2("IO::rf2Conf(): configuring 2nd ADF for Rx; modemState", modemState);
// configure ADF Tx/RX // configure ADF Tx/RX
configureTxRx(modemState); configureTxRx(modemState);
@ -679,7 +679,7 @@ void IO::updateCal(DVM_STATE modemState)
AD7021_CONTROL = ADF7021_REG2; AD7021_CONTROL = ADF7021_REG2;
AD7021_1_IOCTL(); AD7021_1_IOCTL();
DEBUG2("IO: updateCal(): updating ADF calibration; modemState", modemState); DEBUG2("IO::updateCal(): updating ADF calibration; modemState", modemState);
if (m_tx) if (m_tx)
setTX(); setTX();
@ -847,7 +847,7 @@ void IO::configureBand()
else else
f_div = 1U; f_div = 1U;
DEBUG3("IO: configureBand(): configuring ADF freq band; reg1/f_div", ADF7021_REG1, f_div); DEBUG3("IO::configureBand(): configuring ADF freq band; reg1/f_div", ADF7021_REG1, f_div);
} }
/// <summary> /// <summary>
@ -856,6 +856,39 @@ void IO::configureBand()
/// <param name="modemState"></param> /// <param name="modemState"></param>
void IO::configureTxRx(DVM_STATE modemState) void IO::configureTxRx(DVM_STATE modemState)
{ {
uint16_t dmrDiscBW = ADF7021_DISC_BW_DMR, dmrPostBW = ADF7021_POST_BW_DMR;
uint16_t p25DiscBW = ADF7021_DISC_BW_P25, p25PostBW = ADF7021_POST_BW_P25;
// configure DMR discriminator and post demodulator BW
if (dmrDiscBW + m_dmrDiscBWAdj < 0U)
dmrDiscBW = 0U;
else
dmrDiscBW = ADF7021_DISC_BW_DMR + m_dmrDiscBWAdj;
if (dmrDiscBW > ADF7021_DISC_BW_MAX)
dmrDiscBW = ADF7021_DISC_BW_MAX;
if (dmrPostBW + m_dmrPostBWAdj < 0)
dmrPostBW = 0U;
else
dmrPostBW = ADF7021_POST_BW_DMR + m_dmrPostBWAdj;
if (dmrPostBW > ADF7021_POST_BW_MAX)
dmrPostBW = ADF7021_POST_BW_MAX;
// configure P25 discriminator and post demodulator BW
if (p25DiscBW + m_p25DiscBWAdj < 0U)
p25DiscBW = 0U;
else
p25DiscBW = ADF7021_DISC_BW_P25 + m_p25DiscBWAdj;
if (p25DiscBW > ADF7021_DISC_BW_MAX)
p25DiscBW = ADF7021_DISC_BW_MAX;
if (p25PostBW + m_p25PostBWAdj < 0)
p25PostBW = 0U;
else
p25PostBW = ADF7021_POST_BW_P25 + m_p25PostBWAdj;
if (p25PostBW > ADF7021_POST_BW_MAX)
p25PostBW = ADF7021_POST_BW_MAX;
/* /*
** Configure the remaining registers based on modem state. ** Configure the remaining registers based on modem state.
*/ */
@ -874,29 +907,13 @@ void IO::configureTxRx(DVM_STATE modemState)
/* /*
** Demodulator Setup (Register 4) ** Demodulator Setup (Register 4)
*/ */
uint16_t discBW = ADF7021_DISC_BW_DMR;
if (discBW + m_dmrDiscBWAdj < 0U)
discBW = 0U;
else
discBW = ADF7021_DISC_BW_DMR + m_dmrDiscBWAdj;
if (discBW > ADF7021_DISC_BW_MAX)
discBW = ADF7021_DISC_BW_MAX;
uint16_t postBW = ADF7021_POST_BW_DMR;
if (postBW + m_dmrPostBWAdj < 0)
postBW = 0U;
else
postBW = ADF7021_POST_BW_DMR + m_dmrPostBWAdj;
if (postBW > ADF7021_POST_BW_MAX)
postBW = ADF7021_POST_BW_MAX;
// K=32 // K=32
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4 ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product
ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data
ADF7021_REG4 |= (uint32_t)(discBW & 0x3FFU) << 10; // discriminator BW ADF7021_REG4 |= (uint32_t)(dmrDiscBW & 0x3FFU) << 10; // discriminator BW
ADF7021_REG4 |= (uint32_t)(postBW & 0xFFFU) << 20; // post demod BW ADF7021_REG4 |= (uint32_t)(dmrPostBW & 0xFFFU) << 20; // post demod BW
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter (25 kHz) ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter (25 kHz)
/* /*
@ -930,30 +947,15 @@ void IO::configureTxRx(DVM_STATE modemState)
/* /*
** Demodulator Setup (Register 4) ** Demodulator Setup (Register 4)
*/ */
uint16_t discBW = ADF7021_DISC_BW_DMR;
if (discBW + m_dmrDiscBWAdj < 0U)
discBW = 0U;
else
discBW = ADF7021_DISC_BW_DMR + m_dmrDiscBWAdj;
if (discBW > ADF7021_DISC_BW_MAX)
discBW = ADF7021_DISC_BW_MAX;
uint16_t postBW = ADF7021_POST_BW_DMR;
if (postBW + m_dmrPostBWAdj < 0)
postBW = 0U;
else
postBW = ADF7021_POST_BW_DMR + m_dmrPostBWAdj;
if (postBW > ADF7021_POST_BW_MAX)
postBW = ADF7021_POST_BW_MAX;
// K=32 // K=32
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4 ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product
ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data
ADF7021_REG4 |= (uint32_t)(discBW & 0x3FFU) << 10; // discriminator BW ADF7021_REG4 |= (uint32_t)(dmrDiscBW & 0x3FFU) << 10; // discriminator BW
ADF7021_REG4 |= (uint32_t)(postBW & 0xFFFU) << 20; // post demod BW ADF7021_REG4 |= (uint32_t)(dmrPostBW & 0xFFFU) << 20; // post demod BW
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter (25 kHz) ADF7021_REG4 |= (uint32_t)0b00 << 30; // IF filter (12.5 kHz)
//ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter (25 kHz)
/* /*
** 3FSK/4FSK Demod (Register 13) ** 3FSK/4FSK Demod (Register 13)
@ -990,29 +992,13 @@ void IO::configureTxRx(DVM_STATE modemState)
/* /*
** Demodulator Setup (Register 4) ** Demodulator Setup (Register 4)
*/ */
uint16_t discBW = ADF7021_DISC_BW_P25;
if (discBW + m_dmrDiscBWAdj < 0U)
discBW = 0U;
else
discBW = ADF7021_DISC_BW_P25 + m_dmrDiscBWAdj;
if (discBW > ADF7021_DISC_BW_MAX)
discBW = ADF7021_DISC_BW_MAX;
uint16_t postBW = ADF7021_POST_BW_P25;
if (postBW + m_dmrPostBWAdj < 0)
postBW = 0U;
else
postBW = ADF7021_POST_BW_P25 + m_dmrPostBWAdj;
if (postBW > ADF7021_POST_BW_MAX)
postBW = ADF7021_POST_BW_MAX;
// K=32 // K=32
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4 ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product ADF7021_REG4 |= (uint32_t)0b0 << 7; // cross product
ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data ADF7021_REG4 |= (uint32_t)0b11 << 8; // invert clk/data
ADF7021_REG4 |= (uint32_t)(discBW & 0x3FFU) << 10; // discriminator BW ADF7021_REG4 |= (uint32_t)(p25DiscBW & 0x3FFU) << 10; // discriminator BW
ADF7021_REG4 |= (uint32_t)(postBW & 0xFFFU) << 20; // post demod BW ADF7021_REG4 |= (uint32_t)(p25PostBW & 0xFFFU) << 20; // post demod BW
ADF7021_REG4 |= (uint32_t)0b00 << 30; // IF filter (12.5 kHz) ADF7021_REG4 |= (uint32_t)0b00 << 30; // IF filter (12.5 kHz)
/* /*
@ -1077,7 +1063,8 @@ void IO::configureTxRx(DVM_STATE modemState)
break; break;
} }
DEBUG4("IO: configureTxRx(): configuring ADF Tx/Rx states; dmrSymDev/p25SymDev/rfPower", (uint16_t)((ADF7021_PFD * dmrDev) / (f_div * 65536)), DEBUG5("IO::configureTxRx(): configuring ADF Tx/Rx values; dmrDiscBW/dmrPostBW/p25DiscBW/p25PostBW", dmrDiscBW, dmrPostBW, p25DiscBW, p25PostBW);
DEBUG4("IO::configureTxRx(): configuring ADF Tx/Rx values; dmrSymDev/p25SymDev/rfPower", (uint16_t)((ADF7021_PFD * dmrDev) / (f_div * 65536)),
(uint16_t)((ADF7021_PFD * p25Dev) / (f_div * 65536)), m_rfPower); (uint16_t)((ADF7021_PFD * p25Dev) / (f_div * 65536)), m_rfPower);
} }

2
IO.cpp
Unescape View File

@ -226,7 +226,7 @@ void IO::setMode(DVM_STATE modemState)
relativeState = serial.calRelativeState(modemState); relativeState = serial.calRelativeState(modemState);
} }
DEBUG3("IO: setMode(): setting RF hardware", modemState, relativeState); DEBUG3("IO::setMode(): setting RF hardware", modemState, relativeState);
rf1Conf(relativeState, true); rf1Conf(relativeState, true);

48
dmr/DMRDMORX.cpp
Unescape View File

@ -39,7 +39,7 @@ using namespace dmr;
// Constants // Constants
// --------------------------------------------------------------------------- // ---------------------------------------------------------------------------
const uint8_t MAX_SYNC_BYTES_ERRS = 3U; const uint8_t MAX_SYNC_BYTES_ERRS = 2U;
const uint8_t MAX_SYNC_LOST_FRAMES = 13U; const uint8_t MAX_SYNC_LOST_FRAMES = 13U;
@ -246,8 +246,34 @@ void DMRDMORX::setColorCode(uint8_t colorCode)
/// </summary> /// </summary>
void DMRDMORX::correlateSync() void DMRDMORX::correlateSync()
{ {
if ((countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_DATA_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) || \ uint8_t errs = countBits32((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_DATA_SYNC_BITS);
(countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_S2_DATA_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS)) {
// The voice sync is the complement of the data sync
bool data = (errs <= MAX_SYNC_BYTES_ERRS);
bool voice = (errs >= (DMR_SYNC_LENGTH_SYMBOLS - MAX_SYNC_BYTES_ERRS));
// unpack sync bytes
uint8_t sync[DMR_SYNC_BYTES_LENGTH];
sync[0U] = (uint8_t)((m_bitBuffer >> 48) & 0xFFU);
sync[1U] = (uint8_t)((m_bitBuffer >> 40) & 0xFFU);
sync[2U] = (uint8_t)((m_bitBuffer >> 32) & 0xFFU);
sync[3U] = (uint8_t)((m_bitBuffer >> 24) & 0xFFU);
sync[4U] = (uint8_t)((m_bitBuffer >> 16) & 0xFFU);
sync[5U] = (uint8_t)((m_bitBuffer >> 8) & 0xFFU);
sync[6U] = (uint8_t)((m_bitBuffer >> 0) & 0xFFU);
if (data) {
uint8_t errs = 0U;
for (uint8_t i = 0U; i < DMR_SYNC_BYTES_LENGTH; i++)
errs += countBits8((sync[i] & DMR_SYNC_BYTES_MASK[i]) ^ DMR_MS_DATA_SYNC_BYTES[i]);
if (errs <= MAX_SYNC_BYTES_ERRS) {
DEBUG2("DMRDMORX: correlateSync(): correlateSync errs", errs);
DEBUG4("DMRDMORX: correlateSync(): sync [b0 - b2]", sync[0], sync[1], sync[2]);
DEBUG4("DMRDMORX: correlateSync(): sync [b3 - b5]", sync[3], sync[4], sync[5]);
DEBUG2("DMRDMORX: correlateSync(): sync [b6]", sync[6]);
m_control = CONTROL_DATA; m_control = CONTROL_DATA;
m_syncPtr = m_dataPtr; m_syncPtr = m_dataPtr;
@ -261,8 +287,19 @@ void DMRDMORX::correlateSync()
DEBUG4("DMRDMORX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr); DEBUG4("DMRDMORX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr);
} }
else if ((countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_VOICE_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) || \ }
(countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_S2_VOICE_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS)) { else {
uint8_t errs = 0U;
for (uint8_t i = 0U; i < DMR_SYNC_BYTES_LENGTH; i++)
errs += countBits8((sync[i] & DMR_SYNC_BYTES_MASK[i]) ^ DMR_MS_VOICE_SYNC_BYTES[i]);
if (errs <= MAX_SYNC_BYTES_ERRS) {
DEBUG2("DMRDMORX: correlateSync(): correlateSync errs", errs);
DEBUG4("DMRDMORX: correlateSync(): sync [b0 - b2]", sync[0], sync[1], sync[2]);
DEBUG4("DMRDMORX: correlateSync(): sync [b3 - b5]", sync[3], sync[4], sync[5]);
DEBUG2("DMRDMORX: correlateSync(): sync [b6]", sync[6]);
m_control = CONTROL_VOICE; m_control = CONTROL_VOICE;
m_syncPtr = m_dataPtr; m_syncPtr = m_dataPtr;
@ -276,6 +313,7 @@ void DMRDMORX::correlateSync()
DEBUG4("DMRDMORX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr); DEBUG4("DMRDMORX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr);
} }
}
} }
/// <summary> /// <summary>

10
dmr/DMRDefines.h
Unescape View File

@ -80,10 +80,12 @@ namespace dmr
const uint8_t DMR_MS_VOICE_SYNC_BYTES[] = { 0x07U, 0xF7U, 0xD5U, 0xDDU, 0x57U, 0xDFU, 0xD0U }; const uint8_t DMR_MS_VOICE_SYNC_BYTES[] = { 0x07U, 0xF7U, 0xD5U, 0xDDU, 0x57U, 0xDFU, 0xD0U };
const uint8_t DMR_BS_DATA_SYNC_BYTES[] = { 0x0DU, 0xFFU, 0x57U, 0xD7U, 0x5DU, 0xF5U, 0xD0U }; const uint8_t DMR_BS_DATA_SYNC_BYTES[] = { 0x0DU, 0xFFU, 0x57U, 0xD7U, 0x5DU, 0xF5U, 0xD0U };
const uint8_t DMR_BS_VOICE_SYNC_BYTES[] = { 0x07U, 0x55U, 0xFDU, 0x7DU, 0xF7U, 0x5FU, 0x70U }; const uint8_t DMR_BS_VOICE_SYNC_BYTES[] = { 0x07U, 0x55U, 0xFDU, 0x7DU, 0xF7U, 0x5FU, 0x70U };
/*
const uint8_t DMR_S1_DATA_SYNC_BYTES[] = { 0x0FU, 0x7FU, 0xDDU, 0x5DU, 0xDFU, 0xD5U, 0x50U }; const uint8_t DMR_S1_DATA_SYNC_BYTES[] = { 0x0FU, 0x7FU, 0xDDU, 0x5DU, 0xDFU, 0xD5U, 0x50U };
const uint8_t DMR_S1_VOICE_SYNC_BYTES[] = { 0x05U, 0xD5U, 0x77U, 0xF7U, 0x75U, 0x7FU, 0xF0U }; const uint8_t DMR_S1_VOICE_SYNC_BYTES[] = { 0x05U, 0xD5U, 0x77U, 0xF7U, 0x75U, 0x7FU, 0xF0U };
const uint8_t DMR_S2_DATA_SYNC_BYTES[] = { 0x0DU, 0x75U, 0x57U, 0xF5U, 0xFFU, 0x7FU, 0x50U }; const uint8_t DMR_S2_DATA_SYNC_BYTES[] = { 0x0DU, 0x75U, 0x57U, 0xF5U, 0xFFU, 0x7FU, 0x50U };
const uint8_t DMR_S2_VOICE_SYNC_BYTES[] = { 0x07U, 0xDFU, 0xFDU, 0x5FU, 0x55U, 0xD5U, 0xF0U }; const uint8_t DMR_S2_VOICE_SYNC_BYTES[] = { 0x07U, 0xDFU, 0xFDU, 0x5FU, 0x55U, 0xD5U, 0xF0U };
*/
const uint8_t DMR_SYNC_BYTES_MASK[] = { 0x0FU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xF0U }; const uint8_t DMR_SYNC_BYTES_MASK[] = { 0x0FU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xF0U };
const uint8_t DMR_START_SYNC = 0x5FU; const uint8_t DMR_START_SYNC = 0x5FU;
@ -92,20 +94,12 @@ namespace dmr
const uint64_t DMR_MS_VOICE_SYNC_BITS = 0x00007F7D5DD57DFDU; const uint64_t DMR_MS_VOICE_SYNC_BITS = 0x00007F7D5DD57DFDU;
const uint64_t DMR_BS_DATA_SYNC_BITS = 0x0000DFF57D75DF5DU; const uint64_t DMR_BS_DATA_SYNC_BITS = 0x0000DFF57D75DF5DU;
const uint64_t DMR_BS_VOICE_SYNC_BITS = 0x0000755FD7DF75F7U; const uint64_t DMR_BS_VOICE_SYNC_BITS = 0x0000755FD7DF75F7U;
const uint64_t DMR_S1_DATA_SYNC_BITS = 0x0000F7FDD5DDFD55U;
const uint64_t DMR_S1_VOICE_SYNC_BITS = 0x00005D577F7757FFU;
const uint64_t DMR_S2_DATA_SYNC_BITS = 0x0000D7557F5FF7F5U;
const uint64_t DMR_S2_VOICE_SYNC_BITS = 0x00007DFFD5F55D5FU;
const uint64_t DMR_SYNC_BITS_MASK = 0x0000FFFFFFFFFFFFU; const uint64_t DMR_SYNC_BITS_MASK = 0x0000FFFFFFFFFFFFU;
const uint32_t DMR_MS_DATA_SYNC_SYMBOLS = 0x0076286EU; const uint32_t DMR_MS_DATA_SYNC_SYMBOLS = 0x0076286EU;
const uint32_t DMR_MS_VOICE_SYNC_SYMBOLS = 0x0089D791U; const uint32_t DMR_MS_VOICE_SYNC_SYMBOLS = 0x0089D791U;
const uint32_t DMR_BS_DATA_SYNC_SYMBOLS = 0x00439B4DU; const uint32_t DMR_BS_DATA_SYNC_SYMBOLS = 0x00439B4DU;
const uint32_t DMR_BS_VOICE_SYNC_SYMBOLS = 0x00BC64B2U; const uint32_t DMR_BS_VOICE_SYNC_SYMBOLS = 0x00BC64B2U;
const uint32_t DMR_S1_DATA_SYNC_SYMBOLS = 0x0021751FU;
const uint32_t DMR_S1_VOICE_SYNC_SYMBOLS = 0x00DE8AE0U;
const uint32_t DMR_S2_DATA_SYNC_SYMBOLS = 0x006F8C23U;
const uint32_t DMR_S2_VOICE_SYNC_SYMBOLS = 0x009073DCU;
const uint32_t DMR_SYNC_SYMBOLS_MASK = 0x00FFFFFFU; const uint32_t DMR_SYNC_SYMBOLS_MASK = 0x00FFFFFFU;
// D 5 D 7 F 7 7 F D 7 5 7 // D 5 D 7 F 7 7 F D 7 5 7

44
dmr/DMRSlotRX.cpp
Unescape View File

@ -286,7 +286,34 @@ void DMRSlotRX::setRxDelay(uint8_t delay)
/// <param name="first"></param> /// <param name="first"></param>
void DMRSlotRX::correlateSync() void DMRSlotRX::correlateSync()
{ {
if (countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_DATA_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) { uint8_t errs = countBits32((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_DATA_SYNC_BITS);
// The voice sync is the complement of the data sync
bool data = (errs <= MAX_SYNC_BYTES_ERRS);
bool voice = (errs >= (DMR_SYNC_LENGTH_SYMBOLS - MAX_SYNC_BYTES_ERRS));
// unpack sync bytes
uint8_t sync[DMR_SYNC_BYTES_LENGTH];
sync[0U] = (uint8_t)((m_bitBuffer >> 48) & 0xFFU);
sync[1U] = (uint8_t)((m_bitBuffer >> 40) & 0xFFU);
sync[2U] = (uint8_t)((m_bitBuffer >> 32) & 0xFFU);
sync[3U] = (uint8_t)((m_bitBuffer >> 24) & 0xFFU);
sync[4U] = (uint8_t)((m_bitBuffer >> 16) & 0xFFU);
sync[5U] = (uint8_t)((m_bitBuffer >> 8) & 0xFFU);
sync[6U] = (uint8_t)((m_bitBuffer >> 0) & 0xFFU);
if (data) {
uint8_t errs = 0U;
for (uint8_t i = 0U; i < DMR_SYNC_BYTES_LENGTH; i++)
errs += countBits8((sync[i] & DMR_SYNC_BYTES_MASK[i]) ^ DMR_MS_DATA_SYNC_BYTES[i]);
if (errs <= MAX_SYNC_BYTES_ERRS) {
DEBUG3("DMRSlotRX: correlateSync(): correlateSync slot/errs", m_slot ? 2U : 1U, errs);
DEBUG4("DMRSlotRX: correlateSync(): sync [b0 - b2]", sync[0], sync[1], sync[2]);
DEBUG4("DMRSlotRX: correlateSync(): sync [b3 - b5]", sync[3], sync[4], sync[5]);
DEBUG2("DMRSlotRX: correlateSync(): sync [b6]", sync[6]);
m_control = CONTROL_DATA; m_control = CONTROL_DATA;
m_syncPtr = m_dataPtr; m_syncPtr = m_dataPtr;
@ -300,7 +327,19 @@ void DMRSlotRX::correlateSync()
DEBUG4("DMRSlotRX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr); DEBUG4("DMRSlotRX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr);
} }
else if (countBits64((m_bitBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_VOICE_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) { }
else {
uint8_t errs = 0U;
for (uint8_t i = 0U; i < DMR_SYNC_BYTES_LENGTH; i++)
errs += countBits8((sync[i] & DMR_SYNC_BYTES_MASK[i]) ^ DMR_MS_VOICE_SYNC_BYTES[i]);
if (errs <= MAX_SYNC_BYTES_ERRS) {
DEBUG3("DMRSlotRX: correlateSync(): correlateSync slot/errs", m_slot ? 2U : 1U, errs);
DEBUG4("DMRSlotRX: correlateSync(): sync [b0 - b2]", sync[0], sync[1], sync[2]);
DEBUG4("DMRSlotRX: correlateSync(): sync [b3 - b5]", sync[3], sync[4], sync[5]);
DEBUG2("DMRSlotRX: correlateSync(): sync [b6]", sync[6]);
m_control = CONTROL_VOICE; m_control = CONTROL_VOICE;
m_syncPtr = m_dataPtr; m_syncPtr = m_dataPtr;
@ -314,6 +353,7 @@ void DMRSlotRX::correlateSync()
DEBUG4("DMRSlotRX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr); DEBUG4("DMRSlotRX: correlateSync(): dataPtr/startPtr/endPtr", m_dataPtr, m_startPtr, m_endPtr);
} }
}
} }
/// <summary> /// <summary>

Write Preview
Loading…
Cancel
Save

Powered by TurnKey Linux.