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251 lines
6.7 KiB
251 lines
6.7 KiB
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "ch.h"
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#include "hal.h"
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#include "nanovna.h"
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#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \
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(uint32_t)(low))
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#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */
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#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
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#define ADC_CFGR1_RES_12BIT (0U << 3U)
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#define VNA_ADC ADC1
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void adc_init(void)
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{
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rccEnableADC1(FALSE);
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/* Ensure flag states */
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VNA_ADC->IER = 0;
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/* Calibration procedure.*/
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ADC->CCR = 0;
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if (VNA_ADC->CR & ADC_CR_ADEN) {
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VNA_ADC->CR |= ~ADC_CR_ADDIS; /* Disable ADC */
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}
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while (VNA_ADC->CR & ADC_CR_ADEN)
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;
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VNA_ADC->CFGR1 &= ~ADC_CFGR1_DMAEN;
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VNA_ADC->CR |= ADC_CR_ADCAL;
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while (VNA_ADC->CR & ADC_CR_ADCAL)
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;
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if (VNA_ADC->ISR & ADC_ISR_ADRDY) {
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VNA_ADC->ISR |= ADC_ISR_ADRDY; /* clear ADRDY */
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}
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/* Enable ADC */
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VNA_ADC->CR |= ADC_CR_ADEN;
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while (!(VNA_ADC->ISR & ADC_ISR_ADRDY))
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;
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}
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uint16_t adc_single_read(uint32_t chsel)
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{
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/* ADC setup */
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VNA_ADC->ISR = VNA_ADC->ISR;
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VNA_ADC->IER = 0;
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VNA_ADC->TR = ADC_TR(0, 0);
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VNA_ADC->SMPR = ADC_SMPR_SMP_239P5;
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VNA_ADC->CFGR1 = ADC_CFGR1_RES_12BIT;
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VNA_ADC->CHSELR = chsel;
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VNA_ADC->CR |= ADC_CR_ADSTART; // ADC conversion start
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while (VNA_ADC->CR & ADC_CR_ADSTART)
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;
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return VNA_ADC->DR;
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}
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int16_t adc_vbat_read(void)
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{
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// Vbat measure averange count = 2^VBAT_AVERAGE
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#define VBAT_AVERAGE 4
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// Measure vbat every 5 second
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#define VBAT_MEASURE_INTERVAL 50000
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static int16_t vbat_raw = 0;
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static systime_t vbat_time = -VBAT_MEASURE_INTERVAL-1;
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systime_t _time = chVTGetSystemTimeX();
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if (_time - vbat_time < VBAT_MEASURE_INTERVAL)
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goto return_cached;
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vbat_time = _time;
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// 13.9 Temperature sensor and internal reference voltage
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// VREFINT_CAL calibrated on 3.3V, need get value in mV
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#define ADC_FULL_SCALE 3300
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#define VREFINT_CAL (*((uint16_t*)0x1FFFF7BA))
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uint32_t vrefint = 0;
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uint32_t vbat = 0;
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uint8_t restart_touch = 0;
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if (VNA_ADC->CR & ADC_CR_ADSTART){
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adc_stop_analog_watchdog();
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restart_touch = 1;
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}
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ADC->CCR |= ADC_CCR_VREFEN | ADC_CCR_VBATEN;
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for (uint16_t i = 0; i < 1<<VBAT_AVERAGE; i++){
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// VREFINT == ADC_IN17
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vrefint+= adc_single_read(ADC_CHSELR_CHSEL17);
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// VBAT == ADC_IN18
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// VBATEN enables resiter devider circuit. It consume vbat power.
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vbat+= adc_single_read(ADC_CHSELR_CHSEL18);
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}
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vbat>>=VBAT_AVERAGE;
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vrefint>>=VBAT_AVERAGE;
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ADC->CCR &= ~(ADC_CCR_VREFEN | ADC_CCR_VBATEN);
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if (restart_touch)
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adc_start_analog_watchdog();
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// vbat_raw = (3300 * 2 * vbat / 4095) * (VREFINT_CAL / vrefint)
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// uint16_t vbat_raw = (ADC_FULL_SCALE * VREFINT_CAL * (float)vbat * 2 / (vrefint * ((1<<12)-1)));
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// For speed divide not on 4095, divide on 4096, get little error, but no matter
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vbat_raw = ((ADC_FULL_SCALE * 2 * vbat)>>12) * VREFINT_CAL / vrefint;
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return_cached:
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if (vbat_raw < 100) {
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// maybe D2 is not installed
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return -1;
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}
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return vbat_raw + config.vbat_offset;
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}
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void adc_start_analog_watchdog(void)
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{
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uint32_t cfgr1;
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cfgr1 = ADC_CFGR1_RES_12BIT | ADC_CFGR1_AWDEN
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| ADC_CFGR1_EXTEN_0 // rising edge of external trigger
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| ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1; // TRG3 , /* CFGR1 */
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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VNA_ADC->ISR = VNA_ADC->ISR;
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VNA_ADC->IER = ADC_IER_AWDIE;
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VNA_ADC->TR = ADC_TR(0, TOUCH_THRESHOLD);
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VNA_ADC->SMPR = ADC_SMPR_SMP_1P5;
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VNA_ADC->CHSELR = ADC_TOUCH_Y;
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/* ADC configuration and start.*/
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VNA_ADC->CFGR1 = cfgr1;
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/* ADC conversion start.*/
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VNA_ADC->CR |= ADC_CR_ADSTART;
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}
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void adc_stop_analog_watchdog(void)
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{
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if (VNA_ADC->CR & ADC_CR_ADEN) {
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if (VNA_ADC->CR & ADC_CR_ADSTART) {
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VNA_ADC->CR |= ADC_CR_ADSTP;
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while (VNA_ADC->CR & ADC_CR_ADSTP)
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;
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}
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/* VNA_ADC->CR |= ADC_CR_ADDIS;
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while (VNA_ADC->CR & ADC_CR_ADDIS)
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;*/
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}
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}
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void adc_interrupt(void)
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{
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uint32_t isr = VNA_ADC->ISR;
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VNA_ADC->ISR = isr;
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if (isr & ADC_ISR_OVR) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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handle_touch_interrupt();
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}
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}
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OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER)
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{
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OSAL_IRQ_PROLOGUE();
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adc_interrupt();
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OSAL_IRQ_EPILOGUE();
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}
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#if 1
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uint16_t adc_multi_read(uint32_t chsel, uint16_t *result, uint32_t count)
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{
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/* ADC setup */
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VNA_ADC->ISR = VNA_ADC->ISR;
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VNA_ADC->IER = 0;
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VNA_ADC->TR = ADC_TR(0, 0);
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VNA_ADC->SMPR = ADC_SMPR_SMP_1P5;
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VNA_ADC->CFGR1 = ADC_CFGR1_RES_12BIT;
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VNA_ADC->CHSELR = chsel;
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// palSetPadMode(GPIOA, 10, PAL_MODE_OUTPUT_PUSHPULL);
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do{
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#if 0
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if (count < 145)
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palSetPad(GPIOA, 10);
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else
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palClearPad(GPIOA, 10);
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#endif
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VNA_ADC->CR |= ADC_CR_ADSTART; // ADC conversion start.
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// while (VNA_ADC->CR & ADC_CR_ADSTART)
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while(!(VNA_ADC->ISR & ADC_ISR_EOC));
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;
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*(result++) =VNA_ADC->DR;
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}while(--count);
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return count;
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}
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int16_t adc_buf_read(uint32_t chsel, uint16_t *result, uint32_t count)
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{
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uint8_t restart_touch = 0;
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if (VNA_ADC->CR & ADC_CR_ADSTART){
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adc_stop_analog_watchdog();
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restart_touch = 1;
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}
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#if 0
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// drive high to low on Y line (coordinates from left to right)
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palSetPad(GPIOB, GPIOB_YN);
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palClearPad(GPIOA, GPIOA_YP);
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// Set Y line as output
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palSetPadMode(GPIOB, GPIOB_YN, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPadMode(GPIOA, GPIOA_YP, PAL_MODE_OUTPUT_PUSHPULL);
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// Set X line as input
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palSetPadMode(GPIOB, GPIOB_XN, PAL_MODE_INPUT); // Hi-z mode
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palSetPadMode(GPIOA, GPIOA_XP, PAL_MODE_INPUT_ANALOG); // <- ADC_TOUCH_X channel
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uint16_t res = adc_multi_read(ADC_TOUCH_X, result, count);
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#else
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// palSetPadMode(GPIOA, 9, PAL_MODE_INPUT_ANALOG);
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uint16_t res = adc_multi_read(chsel, result, count); // ADC_CHSELR_CHSEL9
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#endif
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if (restart_touch)
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adc_start_analog_watchdog();;
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return res;
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}
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#endif
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