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/* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "ch.h"
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#include "hal.h"
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#include "nanovna.h"
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#include "si4432.h"
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#define CS_SI0_HIGH palSetPad(GPIOC, GPIO_RX_SEL)
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#define CS_SI1_HIGH palSetPad(GPIOC, GPIO_LO_SEL)
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#define CS_PE_HIGH palSetPad(GPIOC, GPIO_PE_SEL)
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#define RF_POWER_HIGH palSetPad(GPIOC, GPIO_RF_PWR)
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#define CS_SI0_LOW palClearPad(GPIOC, GPIO_RX_SEL)
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#define CS_SI1_LOW palClearPad(GPIOC, GPIO_LO_SEL)
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#define CS_PE_LOW palClearPad(GPIOC, GPIO_PE_SEL)
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#define SPI2_CLK_HIGH palSetPad(GPIOB, GPIO_SPI2_CLK)
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#define SPI2_CLK_LOW palClearPad(GPIOB, GPIO_SPI2_CLK)
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#define SPI2_SDI_HIGH palSetPad(GPIOB, GPIO_SPI2_SDI)
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#define SPI2_SDI_LOW palClearPad(GPIOB, GPIO_SPI2_SDI)
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#define SPI2_SDO ((palReadPort(GPIOB) & (1<<GPIO_SPI2_SDO))?1:0)
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//#define MAXLOG 1024
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//unsigned char SI4432_logging[MAXLOG];
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//volatile int log_index = 0;
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//#define SI4432_log(X) { if (log_index < MAXLOG) SI4432_logging[log_index++] = X; }
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#define SI4432_log(X)
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void shiftOut(uint8_t val)
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{
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uint8_t i;
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SI4432_log(SI4432_Sel);
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SI4432_log(val);
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for (i = 0; i < 8; i++) {
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if (val & (1 << (7 - i)))
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SPI2_SDI_HIGH;
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else
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SPI2_SDI_LOW;
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SPI2_CLK_HIGH;
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SPI2_CLK_LOW;
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}
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}
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uint8_t shiftIn(void) {
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uint8_t value = 0;
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uint8_t i;
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for (i = 0; i < 8; ++i) {
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SPI2_CLK_HIGH;
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value |= SPI2_SDO << (7 - i);
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SPI2_CLK_LOW;
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}
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return value;
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}
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const int SI_nSEL[3] = { GPIO_RX_SEL, GPIO_LO_SEL, 0}; // #3 is dummy!!!!!!
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volatile int SI4432_Sel = 0; // currently selected SI4432
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// volatile int SI4432_guard = 0;
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#ifdef __SI4432_H__
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#define SELECT_DELAY 10
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void SI4432_Write_Byte(byte ADR, byte DATA )
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{
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// if (SI4432_guard)
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// while(1) ;
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// SI4432_guard = 1;
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SPI2_CLK_LOW;
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palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
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// chThdSleepMicroseconds(SELECT_DELAY);
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ADR |= 0x80 ; // RW = 1
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shiftOut( ADR );
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shiftOut( DATA );
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palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
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// SI4432_guard = 0;
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}
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void SI4432_Write_3_Byte(byte ADR, byte DATA1, byte DATA2, byte DATA3 )
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{
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// if (SI4432_guard)
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// while(1) ;
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// SI4432_guard = 1;
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SPI2_CLK_LOW;
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palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
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// chThdSleepMicroseconds(SELECT_DELAY);
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ADR |= 0x80 ; // RW = 1
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shiftOut( ADR );
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shiftOut( DATA1 );
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shiftOut( DATA2 );
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shiftOut( DATA3 );
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palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
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// SI4432_guard = 0;
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}
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byte SI4432_Read_Byte( byte ADR )
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{
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byte DATA ;
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// if (SI4432_guard)
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// while(1) ;
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// SI4432_guard = 1;
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SPI2_CLK_LOW;
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palClearPad(GPIOC, SI_nSEL[SI4432_Sel]);
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shiftOut( ADR );
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DATA = shiftIn();
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palSetPad(GPIOC, SI_nSEL[SI4432_Sel]);
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// SI4432_guard = 0;
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return DATA ;
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}
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void SI4432_Reset(void)
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{
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int count = 0;
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// always perform a system reset (don't send 0x87)
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SI4432_Write_Byte( 0x07, 0x80);
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chThdSleepMilliseconds(50);
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// wait for chiprdy bit
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while (count++ < 100 && ( SI4432_Read_Byte ( 0x04 ) & 0x02 ) == 0) {
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chThdSleepMilliseconds(10);
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}
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}
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void SI4432_Transmit(int d)
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{
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int count = 0;
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SI4432_Write_Byte(0x6D, (byte) (0x1C+d));
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if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 2)
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return; // Already in transmit mode
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chThdSleepMilliseconds(10);
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SI4432_Write_Byte( 0x07, 0x0b);
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chThdSleepMilliseconds(20);
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while (count++ < 100 && ( SI4432_Read_Byte ( 0x02 ) & 0x03 ) != 2) {
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chThdSleepMilliseconds(10);
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}
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}
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void SI4432_Receive(void)
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{
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int count = 0;
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if (( SI4432_Read_Byte ( 0x02 ) & 0x03 ) == 1)
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return; // Already in receive mode
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chThdSleepMilliseconds(10);
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SI4432_Write_Byte( 0x07, 0x07);
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chThdSleepMilliseconds(20);
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while (count++ < 100 && ( SI4432_Read_Byte ( 0x02 ) & 0x03 ) != 1) {
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chThdSleepMilliseconds(5);
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}
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}
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// First entry of each triple is RBW in khz times 10, so 377 = 37.7khz
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// User asks for an RBW of WISH, go through table finding the last triple
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// for which WISH is greater than the first entry, use those values,
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// Return the first entry of the following triple for the RBW actually achieved
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static const short RBW_choices[] = { // Each triple is: ndec, fils, WISH*10
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0, 5,1,26, 5,2,28, 5,3,31, 5,4,32, 5,5,37, 5,6,42, 5,7,
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45,4,1, 49,4,2, 54,4,3, 59,4,4, 61,4,5, 72,4,6, 82,4,7,
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88,3,1, 95,3,2, 106,3,3, 115,3,4, 121,3,5, 142,3,6, 162,3,7,
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175,2,1, 189,2,2, 210,2,3, 227,2,4, 240,2,5, 282,2,6, 322,2,7,
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347,1,1, 377,1,2, 417,1,3, 452,1,4, 479,1,5, 562,1,6, 641,1,7,
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692,0,1, 752,0,2, 832,0,3, 900,0,4, 953,0,5, 1121,0,6, 1279,0,7,
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1379,1,4, 1428,1,5, 1678,1,9, 1811,0,15, 1915,0,1, 2251,0,2, 2488,0,3,
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2693,0,4, 2849,0,8, 3355,0,9, 3618,0,10, 4202,0,11, 4684,0,12, 5188,0,13,
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5770,0,14, 6207
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};
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float SI4432_SET_RBW(float w) {
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uint8_t dwn3=0;
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int32_t WISH = (uint32_t)(w * 10.0);
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uint8_t ndec, fils, i;
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if (WISH > 6207) WISH=6207; // Final value in RBW_choices[]
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if (WISH > 1379) dwn3 = 1 ;
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for (i=3; i<sizeof(RBW_choices)/sizeof(RBW_choices[0]); i+=3)
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if (WISH <= RBW_choices[i]) break;
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ndec = RBW_choices[i-2];
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fils = RBW_choices[i-1];
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WISH = RBW_choices[i]; // RBW achieved by Si4432 in Hz
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uint8_t BW = (dwn3 << 7) | (ndec << 4) | fils ;
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SI4432_Write_Byte(0x1C , BW ) ;
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return ((float)WISH / 10.0) ;
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}
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void SI4432_Set_Frequency ( long Freq ) {
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int hbsel;
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long Carrier;
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if (Freq >= 480000000) {
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hbsel = 1;
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Freq = Freq / 2;
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} else {
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hbsel = 0;
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}
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int sbsel = 1;
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int N = Freq / 10000000;
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Carrier = ( 4 * ( Freq - N * 10000000 )) / 625;
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int Freq_Band = ( N - 24 ) | ( hbsel << 5 ) | ( sbsel << 6 );
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#if 0
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SI4432_Write_Byte ( 0x75, Freq_Band );
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SI4432_Write_Byte ( 0x76, (Carrier>>8) & 0xFF );
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SI4432_Write_Byte ( 0x77, Carrier & 0xFF );
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#else
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SI4432_Write_3_Byte ( 0x75, Freq_Band, (Carrier>>8) & 0xFF, Carrier & 0xFF );
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#endif
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}
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int actualStepDelay = 1500;
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float SI4432_RSSI(uint32_t i, int s)
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{
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(void) i;
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int RSSI_RAW;
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(void) i;
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// SEE DATASHEET PAGE 61
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#ifdef USE_SI4463
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if (SI4432_Sel == 2) {
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RSSI_RAW = Si446x_getRSSI();
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} else
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#endif
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//START_PROFILE
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SI4432_Sel = s;
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chThdSleepMicroseconds(actualStepDelay);
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RSSI_RAW = (unsigned char)SI4432_Read_Byte( 0x26 ) ;
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// if (MODE_INPUT(setting_mode) && RSSI_RAW == 0)
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// SI4432_Init();
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float dBm = (RSSI_RAW-240)/2.0;
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#ifdef __SIMULATION__
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dBm = Simulated_SI4432_RSSI(i,s);
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#endif
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//STOP_PROFILE
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// Serial.println(dBm,2);
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return dBm ;
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}
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void SI4432_Sub_Init(void)
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{
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SI4432_Reset();
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SI4432_Write_Byte(0x05, 0x0);
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SI4432_Write_Byte(0x06, 0x0);
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// Enable receiver chain
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// SI4432_Write_Byte(0x07, 0x05);
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// Clock Recovery Gearshift Value
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SI4432_Write_Byte(0x1F, 0x00);
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// IF Filter Bandwidth
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SI4432_SET_RBW(10) ;
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// // Register 0x75 Frequency Band Select
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// byte sbsel = 1 ; // recommended setting
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// byte hbsel = 0 ; // low bands
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// byte fb = 19 ; // 430<33>439.9 MHz
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// byte FBS = (sbsel << 6 ) | (hbsel << 5 ) | fb ;
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// SI4432_Write_Byte(0x75, FBS) ;
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SI4432_Write_Byte(0x75, 0x46) ;
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// Register 0x76 Nominal Carrier Frequency
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// WE USE 433.92 MHz
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// Si443x-Register-Settings_RevB1.xls
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// SI4432_Write_Byte(0x76, 0x62) ;
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SI4432_Write_Byte(0x76, 0x00) ;
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// Register 0x77 Nominal Carrier Frequency
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SI4432_Write_Byte(0x77, 0x00) ;
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// RX MODEM SETTINGS
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SI4432_Write_Byte(0x1C, 0x81) ;
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SI4432_Write_Byte(0x1D, 0x3C) ;
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SI4432_Write_Byte(0x1E, 0x02) ;
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SI4432_Write_Byte(0x1F, 0x03) ;
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// SI4432_Write_Byte(0x20, 0x78) ;
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SI4432_Write_Byte(0x21, 0x01) ;
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SI4432_Write_Byte(0x22, 0x11) ;
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SI4432_Write_Byte(0x23, 0x11) ;
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SI4432_Write_Byte(0x24, 0x01) ;
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SI4432_Write_Byte(0x25, 0x13) ;
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SI4432_Write_Byte(0x2A, 0xFF) ;
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SI4432_Write_Byte(0x2C, 0x28) ;
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SI4432_Write_Byte(0x2D, 0x0C) ;
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SI4432_Write_Byte(0x2E, 0x28) ;
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SI4432_Write_Byte(0x69, 0x60); // AGC, no LNA, fast gain increment
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// GPIO automatic antenna switching
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SI4432_Write_Byte(0x0B, 0x12) ; // Normal
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SI4432_Write_Byte(0x0C, 0x15) ;
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}
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#define V0_XTAL_CAPACITANCE 0x64
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#define V1_XTAL_CAPACITANCE 0x64
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void SI4432_Init()
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{
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RF_POWER_HIGH; // Power the RF part
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chThdSleepMilliseconds(25);
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//DebugLine("IO set");
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SI4432_Sel = 0;
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SI4432_Sub_Init();
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SI4432_Sel = 1;
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SI4432_Sub_Init();
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//DebugLine("1 init done");
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SI4432_Sel = 0;
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SI4432_Receive();// Enable receiver chain
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// SI4432_Write_Byte(0x09, V0_XTAL_CAPACITANCE);// Tune the crystal
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SI4432_Set_Frequency(433700000);
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SI4432_Write_Byte(0x0D, 0x1F) ; // Set GPIO2 output to ground
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SI4432_Sel = 1;
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// SI4432_Write_Byte(0x09, V1_XTAL_CAPACITANCE);// Tune the crystal
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SI4432_Set_Frequency(443700000);
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SI4432_Write_Byte(0x6D, 0x1C);//Set low power
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SI4432_Transmit(0);
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SI4432_Write_Byte(0x0D, 0xC0) ; // Set GPIO2 maximumdrive and clock output
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SI4432_Write_Byte(0x0A, 0x02) ; // Set 10MHz output
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}
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void SI4432_SetReference(int freq)
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{
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SI4432_Sel = 1; //Select Lo module
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if (freq < 0 || freq > 7 ) {
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SI4432_Write_Byte(0x0D, 0x1F) ; // Set GPIO2 to GND
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} else {
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SI4432_Write_Byte(0x0D, 0xC0) ; // Set GPIO2 maximumdrive and clock output
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SI4432_Write_Byte(0x0A, freq & 0x07) ; // Set GPIO2 frequency
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}
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}
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//------------PE4302 -----------------------------------------------
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// Comment out this define to use parallel mode PE4302
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#define PE4302_en 10
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void PE4302_init(void) {
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CS_PE_LOW;
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}
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#define PE4302_DELAY 100
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void PE4302_shiftOut(uint8_t val)
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{
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uint8_t i;
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SI4432_log(SI4432_Sel);
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SI4432_log(val);
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for (i = 0; i < 8; i++) {
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if (val & (1 << (7 - i)))
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SPI2_SDI_HIGH;
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else
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SPI2_SDI_LOW;
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chThdSleepMicroseconds(PE4302_DELAY);
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SPI2_CLK_HIGH;
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chThdSleepMicroseconds(PE4302_DELAY);
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SPI2_CLK_LOW;
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chThdSleepMicroseconds(PE4302_DELAY);
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}
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}
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void PE4302_Write_Byte(unsigned char DATA )
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{
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chThdSleepMicroseconds(PE4302_DELAY);
|
|
|
SPI2_CLK_LOW;
|
|
|
chThdSleepMicroseconds(PE4302_DELAY);
|
|
|
PE4302_shiftOut(DATA);
|
|
|
chThdSleepMicroseconds(PE4302_DELAY);
|
|
|
CS_PE_HIGH;
|
|
|
chThdSleepMicroseconds(PE4302_DELAY);
|
|
|
CS_PE_LOW;
|
|
|
chThdSleepMicroseconds(PE4302_DELAY);
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
//-----------------SI4432 dummy------------------
|
|
|
void SI4432_Write_Byte(unsigned char ADR, unsigned char DATA ) {}
|
|
|
unsigned char SI4432_Read_Byte(unsigned char ADR) {return ADR;}
|
|
|
float SI4432_SET_RBW(float WISH) {return (WISH > 600.0?600: (WISH<3.0?3:WISH));}
|
|
|
void SI4432_SetReference(int p) {}
|
|
|
void SI4432_Set_Frequency(long f) {}
|
|
|
void PE4302_Write_Byte(unsigned char DATA ) {}
|
|
|
void PE4302_init(void) {}
|
|
|
#endif
|
|
|
|
|
|
#ifdef __SIMULATION__
|
|
|
unsigned long seed = 123456789;
|
|
|
extern float actual_rbw;
|
|
|
float myfrand(void)
|
|
|
{
|
|
|
seed = (unsigned int) (1103515245 * seed + 12345) ;
|
|
|
return ((float) seed) / 1000000000.0;
|
|
|
}
|
|
|
#define NOISE ((myfrand()-2) * 2) // +/- 4 dBm noise
|
|
|
extern int settingAttenuate;
|
|
|
|
|
|
//#define LEVEL(i, f, v) (v * (1-(fabs(f - frequencies[i])/actual_rbw/1000)))
|
|
|
|
|
|
float LEVEL(uint32_t i, uint32_t f, int v)
|
|
|
{
|
|
|
float dv;
|
|
|
float df = fabs((float)f - (float)i);
|
|
|
if (df < actual_rbw*1000)
|
|
|
dv = df/(actual_rbw*1000);
|
|
|
else
|
|
|
dv = 1 + 50*(df - actual_rbw*1000)/(actual_rbw*1000);
|
|
|
return (v - dv - settingAttenuate);
|
|
|
}
|
|
|
|
|
|
float Simulated_SI4432_RSSI(uint32_t i, int s)
|
|
|
{
|
|
|
SI4432_Sel = s;
|
|
|
float v = -100 + log10(actual_rbw)*10 + NOISE;
|
|
|
if(s == 0) {
|
|
|
v = fmax(LEVEL(i,10000000,-20),v);
|
|
|
v = fmax(LEVEL(i,20000000,-40),v);
|
|
|
v = fmax(LEVEL(i,30000000,-30),v);
|
|
|
v = fmax(LEVEL(i,40000000,-90),v);
|
|
|
} else {
|
|
|
v = fmax(LEVEL(i,320000000,-20),v);
|
|
|
v = fmax(LEVEL(i,340000000,-40),v);
|
|
|
v = fmax(LEVEL(i,360000000,-30),v);
|
|
|
v = fmax(LEVEL(i,380000000,-90),v);
|
|
|
}
|
|
|
return(v);
|
|
|
}
|
|
|
|
|
|
#endif
|
