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174 lines
6.2 KiB
174 lines
6.2 KiB
/* Copyright (c) 2020, Erik Kaashoek erik@kaashoek.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __SI4432_H__
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#define __SI4432_H__
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extern int SI4432_step_delay;
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extern int SI4432_offset_delay;
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#ifdef __SI4432__
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//
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#define MAX_SI4432 2
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#define SI4432_RX 0
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#define SI4432_LO 1
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// #define SI4432_DUMMY 2 // never used
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#define SI4432_DEV_TYPE 0x00
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#define SI4432_DEV_VERSION 0x01
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#define SI4432_DEV_STATUS 0x02
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#define SI4432_INT_STATUS1 0x03
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#define SI4432_INT_STATUS2 0x04
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#define SI4432_INT_ENABLE1 0x05
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#define SI4432_INT_ENABLE2 0x06
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#define SI4432_STATE 0x07
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#define SI4432_OPERATION_CONTROL 0x08
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#define Si4432_CRYSTAL_OSC_LOAD_CAP 0x09
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#define Si4432_UC_OUTPUT_CLOCK 0x0A
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#define SI4432_GPIO0_CONF 0x0B
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#define SI4432_GPIO1_CONF 0x0C
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#define SI4432_GPIO2_CONF 0x0D
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#define SI4432_IOPORT_CONF 0x0E
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#define SI4432_IF_FILTER_BW 0x1C
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#define SI4432_AFC_LOOP_GEARSHIFT_OVERRIDE 0x1D
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#define SI4432_AFC_TIMING_CONTROL 0x1E
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#define SI4432_CLOCK_RECOVERY_GEARSHIFT 0x1F
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#define SI4432_CLOCK_RECOVERY_OVERSAMPLING 0x20
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#define SI4432_CLOCK_RECOVERY_OFFSET2 0x21
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#define SI4432_CLOCK_RECOVERY_OFFSET1 0x22
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#define SI4432_CLOCK_RECOVERY_OFFSET0 0x23
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#define SI4432_CLOCK_RECOVERY_TIMING_GAIN1 0x24
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#define SI4432_CLOCK_RECOVERY_TIMING_GAIN0 0x25
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#define SI4432_REG_RSSI 0x26
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#define SI4432_RSSI_THRESHOLD 0x27
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#define SI4432_AFC_LIMITER 0x2A
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#define SI4432_AFC_CORRECTION_READ 0x2B
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#define Si4432_OOK_COUNTER_VALUE_1 0x2C
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#define Si4432_OOK_COUNTER_VALUE_2 0x2D
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#define Si4432_SLICER_PEAK_HOLD 0x2E
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#define SI4432_DATAACCESS_CONTROL 0x30
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#define SI4432_EZMAC_STATUS 0x31
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#define SI4432_HEADER_CONTROL1 0x32
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#define SI4432_HEADER_CONTROL2 0x33
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#define SI4432_PREAMBLE_LENGTH 0x34
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#define SI4432_PREAMBLE_DETECTION 0x35
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#define SI4432_SYNC_WORD3 0x36
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#define SI4432_SYNC_WORD2 0x37
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#define SI4432_SYNC_WORD1 0x38
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#define SI4432_SYNC_WORD0 0x39
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#define SI4432_TRANSMIT_HEADER3 0x3A
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#define SI4432_TRANSMIT_HEADER2 0x3B
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#define SI4432_TRANSMIT_HEADER1 0x3C
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#define SI4432_TRANSMIT_HEADER0 0x3D
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#define SI4432_PKG_LEN 0x3E
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#define SI4432_CHECK_HEADER3 0x3F
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#define SI4432_CHECK_HEADER2 0x40
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#define SI4432_CHECK_HEADER1 0x41
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#define SI4432_CHECK_HEADER0 0x42
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#define SI4432_RECEIVED_HEADER3 0x47
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#define SI4432_RECEIVED_HEADER2 0x48
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#define SI4432_RECEIVED_HEADER1 0x49
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#define SI4432_RECEIVED_HEADER0 0x4A
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#define SI4432_RECEIVED_LENGTH 0x4B
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#define SI4432_CHARGEPUMP_OVERRIDE 0x58
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#define SI4432_DIVIDER_CURRENT_TRIM 0x59
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#define SI4432_VCO_CURRENT_TRIM 0x5A
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#define SI4432_AGC_OVERRIDE 0x69
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#define SI4432_TX_POWER 0x6D
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#define SI4432_TX_DATARATE1 0x6E
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#define SI4432_TX_DATARATE0 0x6F
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#define SI4432_MODULATION_MODE1 0x70
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#define SI4432_MODULATION_MODE2 0x71
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#define SI4432_FREQ_DEVIATION 0x72
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#define SI4432_FREQ_OFFSET1 0x73
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#define SI4432_FREQ_OFFSET2 0x74
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#define SI4432_FREQBAND 0x75
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#define SI4432_FREQCARRIER_H 0x76
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#define SI4432_FREQCARRIER_L 0x77
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#define SI4432_FREQCHANNEL 0x79
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#define SI4432_CHANNEL_STEPSIZE 0x7A
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#define SI4432_FIFO 0x7F
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extern volatile int SI4432_Sel; // currently selected SI4432
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extern int SI4432_frequency_changed;
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extern int SI4432_offset_changed;
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void SI4432_Write_Byte(uint8_t ADR, uint8_t DATA );
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void SI4432_Write_2_Byte(uint8_t ADR, uint8_t DATA1, uint8_t DATA2);
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uint8_t SI4432_Read_Byte( uint8_t ADR );
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void SI4432_Transmit(int d);
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void SI4432_Receive(void);
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void SI4432_Reset(void);
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void SI4432_Init(void);
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void SI4432_Drive(int);
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pureRSSI_t getSI4432_RSSI_correction(void);
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pureRSSI_t SI4432_RSSI(uint32_t i, int s);
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#ifdef __SIMULATION__
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float Simulated_SI4432_RSSI(uint32_t i, int s);
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#endif
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void SI4432_Set_Frequency ( uint32_t Freq );
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uint16_t force_rbw(int i);
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uint16_t set_rbw(uint16_t WISH);
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extern const int SI4432_RBW_count;
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void set_calibration_freq(int freq);
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#ifdef __FAST_SWEEP__
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void SI4432_Fill(int s, int start);
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#if 0
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int SI4432_is_fast_mode(void);
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#endif
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#endif
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#endif
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bool PE4302_Write_Byte(unsigned char DATA );
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void PE4302_init(void);
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#ifdef __ADF4351__
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extern int ADF4351_LE[];
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extern int debug;
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void ADF4351_Setup(void);
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void ADF4351_WriteRegister32(int channel, const uint32_t value);
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uint32_t ADF4351_set_frequency(int channel, uint32_t freq, int drive_strength);
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uint32_t ADF4351_prep_frequency(int channel, uint32_t freq, int drive_strength);
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//int ADF4351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_strength);
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void ADF4351_Set(int channel);
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void ADF4351_enable_output(void);
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void ADF4351_disable_output(void);
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void ADF4351_spur_mode(int S);
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void ADF4351_R_counter(int R);
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void ADF4351_channel_spacing(int spacing);
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void ADF4351_CP(int p);
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void ADF4351_level(int p);
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int ADF4351_locked(void);
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#endif
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#endif //__SI4432_H__
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