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108 lines
5.0 KiB
108 lines
5.0 KiB
/*
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* Copyright (c) 2019-2020, Dmitry Slepynin (DiSlord) dislordlive@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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//*****************************************************************************
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//********************************** SPI1 bus *********************************
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//*****************************************************************************
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// STM32 SPI transfer mode:
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// in 8 bit mode:
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// if you write *(uint8_t*)(&SPI1->DR) = (uint8_t) data, then data send as << data
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// if you write *(uint16_t*)(&SPI1->DR) =(uint16_t) data, then data send as << dataLoByte, after send dataHiByte
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// in 16 bit mode
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// if you write *(uint16_t*)(&SPI1->DR) =(uint16_t) data, then data send as << data
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// SPI init in 8 bit mode
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#define SPI_CR2_8BIT 0x0700
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#define SPI_CR2_16BIT 0x0F00
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//*****************************************************
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// SPI bus baud rate (PPL/BR_DIV)
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//*****************************************************
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#define SPI_BR_DIV2 (0x00000000U)
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#define SPI_BR_DIV4 (SPI_CR1_BR_0)
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#define SPI_BR_DIV8 (SPI_CR1_BR_1)
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#define SPI_BR_DIV16 (SPI_CR1_BR_1|SPI_CR1_BR_0)
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#define SPI_BR_DIV32 (SPI_CR1_BR_2)
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#define SPI_BR_DIV64 (SPI_CR1_BR_2|SPI_CR1_BR_0)
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#define SPI_BR_DIV128 (SPI_CR1_BR_2|SPI_CR1_BR_1)
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#define SPI_BR_DIV256 (SPI_CR1_BR_2|SPI_CR1_BR_1|SPI_CR1_BR_0)
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#define SPI_BR_SET(spi, br) (spi->CR1 = (spi->CR1& ~(SPI_CR1_BR))|br)
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//*****************************************************
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// SPI bus activity macros
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//*****************************************************
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// The RXNE flag is set depending on the FRXTH bit value in the SPIx_CR2 register:
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// • If FRXTH is set, RXNE goes high and stays high until the RXFIFO level is greater or equal to 1/4 (8-bit).
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#define SPI_RX_IS_NOT_EMPTY(spi) (spi->SR&SPI_SR_RXNE)
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#define SPI_RX_IS_EMPTY(spi) (((spi->SR&SPI_SR_RXNE) == 0))
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// The TXE flag is set when transmission TXFIFO has enough space to store data to send.
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// 0: Tx buffer not empty, bit is cleared automatically when the TXFIFO level becomes greater than 1/2
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// 1: Tx buffer empty, flag goes high and stays high until the TXFIFO level is lower or equal to 1/2 of the FIFO depth
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#define SPI_TX_IS_NOT_EMPTY(spi) (((spi->SR&(SPI_SR_TXE)) == 0))
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#define SPI_TX_IS_EMPTY(spi) (spi->SR&SPI_SR_TXE)
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// When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is busy).
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#define SPI_IS_BUSY(spi) (spi->SR & SPI_SR_BSY)
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// Tx or Rx in process
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#define SPI_IN_TX_RX(spi) ((spi->SR & (SPI_SR_TXE | SPI_SR_RXNE)) == 0 || SPI_IS_BUSY(spi))
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//*****************************************************
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// SPI send data macros
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//*****************************************************
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#define SPI_WRITE_8BIT(spi, data) *(__IO uint8_t*)(&spi->DR) = (uint8_t) data
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#define SPI_WRITE_16BIT(spi, data) *(__IO uint16_t*)(&spi->DR) = (uint16_t) data
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//*****************************************************
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// SPI read data macros
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//*****************************************************
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#define SPI_READ_8BIT(spi) *(__IO uint8_t*)(&spi->DR)
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#define SPI_READ_16BIT(spi) *(__IO uint16_t*)(&spi->DR)
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//*****************************************************
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// DMA channels macros
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//*****************************************************
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#define dmaChannelSetMemory(ch, addr) {(ch)->CMAR = (uint32_t)(addr);}
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#define dmaChannelSetPeripheral(ch, addr) {(ch)->CPAR = (uint32_t)(addr);}
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#define dmaChannelSetTransactionSize(ch, size) {(ch)->CNDTR= (uint32_t)(size);}
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#define dmaChannelGetTransactionSize(ch) ((ch)->CNDTR)
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#define dmaChannelSetMode(ch, mode) {(ch)->CCR = (uint32_t)(mode);}
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#define dmaChannelEnable(ch) {(ch)->CCR |= STM32_DMA_CR_EN;}
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#define dmaChannelDisable(ch) {(ch)->CCR &=~STM32_DMA_CR_EN;}
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#define dmaChannelWaitCompletion(ch) {while ((ch)->CNDTR > 0); (ch)->CCR = 0;}
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#define STM32_DMA_CR_BYTE (STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE)
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#define STM32_DMA_CR_HWORD (STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD)
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#ifdef TINYSA4
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#define SPI_MODE_LCD 0x00
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#define SPI_MODE_SD_CARD 0x01
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#define SPI_MODE_SD_CARD_LOW 0x02
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#define SPI_MODE_SI 0x03
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#define SPI_MODE_PE 0x04
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void set_SPI_mode(uint16_t mode);
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void start_SI4432_SPI_mode(void);
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void stop_SI4432_SPI_mode(void);
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void start_PE4312_SPI_mode(void);
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void stop_PE4312_SPI_mode(void);
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#endif
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