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609 lines
16 KiB
609 lines
16 KiB
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hal.h"
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#include "nanovna.h"
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#ifdef __SI5351__
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#include "si5351.h"
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//inline int palReadLine(uint32_t line) {
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// return ( palReadPort(PAL_PORT(line)) & (1<<PAL_PAD(line)) )
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//}
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char pll_lock_failed = 0;
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int si5351_available = false;
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/*
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* Software i2c bus
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*/
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#define I2C_DELAY my_microsecond_delay(20);
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static inline void scl_low(void) {
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palClearLine(LINE_SCL);
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I2C_DELAY;
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}
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static inline void scl_high(void) {
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palSetLine(LINE_SCL);
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I2C_DELAY;
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}
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static inline void sda_low(void) {
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palClearLine(LINE_SDA);
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I2C_DELAY;
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}
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static inline void sda_high(void) {
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palSetLine(LINE_SDA);
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I2C_DELAY;
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}
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static void i2c_begin(void) {
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sda_low();
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scl_low();
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}
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static void i2c_end(void) {
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sda_low();
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scl_high();
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sda_high();
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}
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uint32_t i2c_recv(int bits) {
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uint32_t ret = 0;
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// soft_i2c_sda.set_mode(GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, HIGH); // Input pullup
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while(bits--) {
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scl_high();
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ret<<= 1;
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if (palReadLine(LINE_SDA)) ret|=1;
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scl_low();
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}
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// soft_i2c_sda.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, LOW); // Output low
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return ret;
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}
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#define CLOCK_TICK {scl_high(); scl_low();}
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#define DATA_OUT(bit) {if (bit) sda_high(); else sda_low();}
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static bool i2c_send(uint8_t data) {
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// put data on bus
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for (uint16_t mask = 0x80; mask; mask>>=1){
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DATA_OUT(data&mask);
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CLOCK_TICK; // clock tick
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}
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// Read answer bit
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bool ret = i2c_recv(1);
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// Stop transfer at error (no answer)
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if (ret)
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i2c_end();
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return ret;
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}
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void i2c_init(void) {
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// soft_i2c_clk.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL);
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// soft_i2c_sda.set_mode(GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL);
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i2c_begin();
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i2c_end();
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}
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#define I2C_WRITE 0
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#define I2C_READ 1
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bool i2c_probe(uint8_t devAddr) {
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i2c_begin();
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// device address
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if(i2c_send((devAddr<<1) | I2C_WRITE))
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return false;
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i2c_end();
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return true;
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}
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// return value: 0: success; -1: no device ack; -2: no register addr ack; -3: no data ack
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int i2c_write(uint8_t devAddr, uint8_t addr, uint8_t data) {
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i2c_begin();
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// device address
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if(i2c_send((devAddr<<1) | I2C_WRITE))
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return -1;
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// register address
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if(i2c_send(addr))
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return -2;
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// data
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if(i2c_send(data))
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return -3;
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i2c_end();
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return 0;
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}
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// return value: 0: success; -1: no device ack; -2: no register addr ack or data ack
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int i2c_write_buf(uint8_t devAddr, uint8_t* data, int len) {
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i2c_begin();
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// device address
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if(i2c_send((devAddr<<1) | I2C_WRITE))
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return -1;
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// data
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for(int i=0; i<len; i++)
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if(i2c_send(data[i]))
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return -2;
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i2c_end();
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return 0;
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}
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// return value: >= 0: the read data; -1: no device ack; -2: no register addr ack
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int i2c_read(uint8_t devAddr, uint8_t addr) {
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i2c_begin();
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// device address
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if(i2c_send((devAddr<<1) | I2C_READ))
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return -1;
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// register address
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if(i2c_send(addr))
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return -2;
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// data
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int res = i2c_recv(8);
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i2c_end();
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return res;
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}
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#define SI5351_I2C_ADDR (0x60<<1)
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static bool si5351_read(uint8_t reg, uint8_t* buf)
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{
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int addr = SI5351_I2C_ADDR>>1;
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int v = i2c_read(addr, reg);
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if (v < 0)
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return false;
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*buf = (uint8_t) v;
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return true;
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}
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static bool si5351_write(uint8_t reg, uint8_t dat)
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{
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int addr = SI5351_I2C_ADDR>>1;
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int s = i2c_write(addr, reg, dat);
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return s >= 0;
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}
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static bool si5351_bulk_write(const uint8_t *buf, int len)
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{
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int addr = SI5351_I2C_ADDR>>1;
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int s = i2c_write_buf(addr, (uint8_t* )buf, len);
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return s >= 0;
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}
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// register addr, length, data, ...
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static const uint8_t si5351_configs[] = {
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff,
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4, SI5351_REG_16_CLK0_CONTROL, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN,
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// 2, SI5351_REG_183_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_8PF,
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// setup PLL (30MHz * 30 = 900MHz, 30/2-2=13)
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9, SI5351_REG_26_PLL_A, /*P3*/0, 1, /*P1*/0, 13, 0, /*P3/P2*/0, 0, 0,
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// RESET PLL
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2, SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B,
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// setup multisynth (900MHz / 30 = 30MHz, 30/2-2=13)
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9, SI5351_REG_42_MULTISYNTH0, /*P3*/0, 1, /*P1*/0, 13, 0, /*P2|P3*/0, 0, 0,
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#ifdef __ENABLE_CLK2__
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2, SI5351_REG_18_CLK2_CONTROL, SI5351_CLK_DRIVE_STRENGTH_2MA | SI5351_CLK_INPUT_MULTISYNTH_N | SI5351_CLK_INTEGER_MODE,
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0,
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#else
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2, SI5351_REG_18_CLK2_CONTROL,SI5351_CLK_POWERDOWN,
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2, SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0x04,
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#endif
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0 // sentinel
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};
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static bool si5351_wait_ready(void)
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{
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uint8_t status = 0xff;
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systime_t start = chVTGetSystemTime();
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systime_t end = start + MS2ST(1000); // 1000 ms timeout
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while (chVTIsSystemTimeWithin(start, end))
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{
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if(!si5351_read(0, &status))
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status = 0xff; // comm timeout
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if ((status & 0x80) == 0)
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return true;
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}
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return false;
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}
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#if 1
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static void si5351_wait_pll_lock(void)
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{
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systime_t start = chVTGetSystemTime();
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uint8_t status = 0xff;
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if(!si5351_read(0, &status))
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status = 0xff; // comm timeout
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if ((status & 0x60) == 0)
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return;
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systime_t end = start + MS2ST(100); // 100 ms timeout
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while (chVTIsSystemTimeWithin(start, end))
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{
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if(!si5351_read(0, &status))
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status = 0xff; // comm timeout
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if ((status & 0x60) == 0)
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return;
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}
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pll_lock_failed = true;
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}
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#endif
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bool si5351_init(void)
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{
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if (!si5351_wait_ready())
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return false;
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// my_microsecond_delay(200);
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const uint8_t *p = si5351_configs;
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while (*p) {
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uint8_t len = *p++;
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if (!si5351_bulk_write(p, len))
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return false;
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p += len;
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}
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si5351_wait_pll_lock();
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if (pll_lock_failed)
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return false;
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return true;
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}
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static void si5351_disable_output(void)
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{
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uint8_t reg[4];
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff);
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reg[0] = SI5351_REG_16_CLK0_CONTROL;
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reg[1] = SI5351_CLK_POWERDOWN;
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reg[2] = SI5351_CLK_POWERDOWN;
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reg[3] = SI5351_CLK_POWERDOWN;
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si5351_bulk_write(reg, 4);
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}
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static void si5351_enable_output(void)
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{
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#ifdef __ENABLE_CLK2__
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0x00);
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#else
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0x04);
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#endif
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}
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static void si5351_reset_pll(void)
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{
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//si5351_write(SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
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si5351_write(SI5351_REG_177_PLL_RESET, 0xAC);
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}
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static void si5351_setupPLL(
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uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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uint8_t mult,
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uint32_t num,
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uint32_t denom)
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{
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/* Get the appropriate starting point for the PLL registers */
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const uint8_t pllreg_base[] = {
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SI5351_REG_26_PLL_A,
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SI5351_REG_34_PLL_B
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};
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uint32_t P1;
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uint32_t P2;
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uint32_t P3;
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/* Feedback Multisynth Divider Equation
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* where: a = mult, b = num and c = denom
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* P1 register is an 18-bit value using following formula:
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* P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512
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* P2 register is a 20-bit value using the following formula:
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* P2[19:0] = 128 * num - denom * floor(128*(num/denom))
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* P3 register is a 20-bit value using the following formula:
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* P3[19:0] = denom
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*/
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/* Set the main PLL config registers */
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if (num == 0)
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{
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/* Integer mode */
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P1 = 128 * mult - 512;
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P2 = 0;
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P3 = 1;
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}
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else
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{
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/* Fractional mode */
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//P1 = (uint32_t)(128 * mult + floor(128 * ((float)num/(float)denom)) - 512);
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P1 = 128 * mult + ((128 * num) / denom) - 512;
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//P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom)));
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P2 = 128 * num - denom * ((128 * num) / denom);
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P3 = denom;
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}
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/* The datasheet is a nightmare of typos and inconsistencies here! */
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uint8_t reg[9];
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reg[0] = pllreg_base[pll];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = (P1 & 0x00030000) >> 16;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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}
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static void si5351_setupMultisynth(
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uint8_t output,
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uint8_t pllSource,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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uint32_t rdiv, // SI5351_R_DIV_1~128
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uint8_t drive_strength)
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{
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/* Get the appropriate starting point for the PLL registers */
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const uint8_t msreg_base[] = {
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SI5351_REG_42_MULTISYNTH0,
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SI5351_REG_50_MULTISYNTH1,
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SI5351_REG_58_MULTISYNTH2,
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};
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const uint8_t clkctrl[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_REG_17_CLK1_CONTROL,
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SI5351_REG_18_CLK2_CONTROL
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};
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uint8_t dat;
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uint32_t P1;
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uint32_t P2;
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uint32_t P3;
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uint32_t div4 = 0;
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/* Output Multisynth Divider Equations
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* where: a = div, b = num and c = denom
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* P1 register is an 18-bit value using following formula:
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* P1[17:0] = 128 * a + floor(128*(b/c)) - 512
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* P2 register is a 20-bit value using the following formula:
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* P2[19:0] = 128 * b - c * floor(128*(b/c))
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* P3 register is a 20-bit value using the following formula:
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* P3[19:0] = c
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*/
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/* Set the main PLL config registers */
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if (div == 4) {
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div4 = SI5351_DIVBY4;
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P1 = P2 = 0;
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P3 = 1;
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} else if (num == 0) {
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/* Integer mode */
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P1 = 128 * div - 512;
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P2 = 0;
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P3 = 1;
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} else {
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/* Fractional mode */
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P1 = 128 * div + ((128 * num) / denom) - 512;
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P2 = 128 * num - denom * ((128 * num) / denom);
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P3 = denom;
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}
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/* Set the MSx config registers */
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uint8_t reg[9];
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reg[0] = msreg_base[output];
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reg[1] = (P3 & 0x0000FF00) >> 8;
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reg[2] = (P3 & 0x000000FF);
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reg[3] = ((P1 & 0x00030000) >> 16) | div4 | rdiv;
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reg[4] = (P1 & 0x0000FF00) >> 8;
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reg[5] = (P1 & 0x000000FF);
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reg[6] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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reg[7] = (P2 & 0x0000FF00) >> 8;
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reg[8] = (P2 & 0x000000FF);
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si5351_bulk_write(reg, 9);
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/* Configure the clk control and enable the output */
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dat = drive_strength | SI5351_CLK_INPUT_MULTISYNTH_N;
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if (pllSource == SI5351_PLL_B)
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dat |= SI5351_CLK_PLL_SELECT_B;
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if (num == 0)
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dat |= SI5351_CLK_INTEGER_MODE;
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si5351_write(clkctrl[output], dat);
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}
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static uint32_t gcd(uint32_t x, uint32_t y)
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{
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uint32_t z;
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while (y != 0) {
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z = x % y;
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x = y;
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y = z;
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}
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return x;
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}
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#define XTALFREQ 30000000L
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#define PLL_N 30
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#define PLLFREQ (XTALFREQ * PLL_N)
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static void si5351_set_frequency_fixedpll(
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int channel, int pll, int pllfreq, int freq,
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uint32_t rdiv, uint8_t drive_strength)
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{
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int32_t div = pllfreq / freq; // range: 8 ~ 1800
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int32_t num = pllfreq - freq * div;
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int32_t denom = freq;
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//int32_t k = freq / (1<<20) + 1;
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int32_t k = gcd(num, denom);
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num /= k;
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denom /= k;
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while (denom >= (1<<20)) {
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num >>= 1;
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denom >>= 1;
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}
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si5351_setupMultisynth(channel, pll, div, num, denom, rdiv, drive_strength);
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}
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static void si5351_set_frequency_fixeddiv(
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int channel, int pll, int freq, int div,
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uint8_t drive_strength)
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{
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int32_t pllfreq = freq * div;
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int32_t multi = pllfreq / XTALFREQ;
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int32_t num = pllfreq - multi * XTALFREQ;
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int32_t denom = XTALFREQ;
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int32_t k = gcd(num, denom);
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num /= k;
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denom /= k;
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while (denom >= (1<<20)) {
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num >>= 1;
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denom >>= 1;
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}
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si5351_setupPLL(pll, multi, num, denom);
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si5351_setupMultisynth(channel, pll, div, 0, 1, SI5351_R_DIV_1, drive_strength);
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}
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/*
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* 1~100MHz fixed PLL 900MHz, fractional divider
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* 100~150MHz fractional PLL 600-900MHz, fixed divider 6
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* 150~200MHz fractional PLL 600-900MHz, fixed divider 4
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*/
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void si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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{
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if (freq <= 100000000) {
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si5351_setupPLL(SI5351_PLL_A, 30, 0, 1);
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si5351_set_frequency_fixedpll(channel, SI5351_PLL_A, PLLFREQ, freq, SI5351_R_DIV_1, drive_strength);
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} else if (freq < 150000000) {
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_A, freq, 6, drive_strength);
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} else {
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_A, freq, 4, drive_strength);
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}
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}
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void si5351_set_int_mul_div(int channel, int multi, int div, uint8_t drive_strength)
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{
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si5351_setupPLL(SI5351_PLL_A, multi, 0, 1);
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si5351_setupMultisynth(channel, SI5351_PLL_A, div, 0, 1, SI5351_R_DIV_1, drive_strength);
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}
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static int current_band = -1;
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/*
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* configure output as follows:
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* CLK0: frequency + offset
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* CLK1: frequency
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* CLK2: fixed 8MHz
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*/
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#define CLK2_FREQUENCY 8000000L
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int si5351_set_frequency_with_offset(uint32_t freq, int offset, uint8_t drive_strength)
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{
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int band;
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int delay = 3;
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uint32_t ofreq = freq + offset;
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uint32_t rdiv = SI5351_R_DIV_1;
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#ifdef __VNA__
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/* if (freq > config.harmonic_freq_threshold * 5 ) {
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freq /= 7;
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ofreq /= 9;
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}else */
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if (freq > config.harmonic_freq_threshold * 3) {
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freq /= 5;
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ofreq /= 7;
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} else if (freq > config.harmonic_freq_threshold) {
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freq /= 3;
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ofreq /= 5;
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}
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#endif
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if (freq <= 100000000) {
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band = 0;
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} else if (freq < 160000000) {
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band = 1;
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} else {
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band = 2;
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}
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if (freq <= 500000) {
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rdiv = SI5351_R_DIV_64;
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} else if (freq <= 4000000) {
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rdiv = SI5351_R_DIV_8;
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}
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#if 1
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if (current_band != band)
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si5351_disable_output();
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#endif
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switch (band) {
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case 0:
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// fractional divider mode. only PLL A is used.
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if (current_band == 1 || current_band == 2){
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si5351_reset_pll();
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si5351_setupPLL(SI5351_PLL_A, PLL_N, 0, 1);
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}
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if (rdiv == SI5351_R_DIV_8) {
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freq *= 8;
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ofreq *= 8;
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} else if (rdiv == SI5351_R_DIV_64) {
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freq *= 64;
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ofreq *= 64;
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}
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|
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si5351_set_frequency_fixedpll(0, SI5351_PLL_A, PLLFREQ, ofreq,
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rdiv, drive_strength);
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si5351_set_frequency_fixedpll(1, SI5351_PLL_A, PLLFREQ, freq,
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rdiv, drive_strength);
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//if (current_band != 0)
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#ifdef __ENABLE_CLK2__
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si5351_set_frequency_fixedpll(2, SI5351_PLL_A, PLLFREQ, CLK2_FREQUENCY,
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SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
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#endif
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break;
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|
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case 1:
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// Set PLL twice on changing from band 2
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if (current_band == 2) {
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si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6, drive_strength);
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si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
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}
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|
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// div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
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si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6, drive_strength);
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si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
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#ifdef __ENABLE_CLK2__
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si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
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SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
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#endif
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break;
|
|
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case 2:
|
|
// div by 4 mode. both PLL A and B are dedicated for CLK0, CLK1
|
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si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4, drive_strength);
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|
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
|
|
#ifdef __ENABLE_CLK2__
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|
si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
|
|
SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
if (current_band != band) {
|
|
si5351_reset_pll();
|
|
si5351_wait_pll_lock();
|
|
#if 1
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|
si5351_enable_output();
|
|
#endif
|
|
delay += 10;
|
|
}
|
|
|
|
current_band = band;
|
|
return delay;
|
|
}
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|
#endif
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