From 42a2bec08205bbf2123edda268134f29caf987a2 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Sun, 2 May 2021 14:11:51 +0300 Subject: [PATCH 1/8] Use hardware sqrtf --- plot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plot.c b/plot.c index 60b6a4d..87ce2f7 100644 --- a/plot.c +++ b/plot.c @@ -323,7 +323,8 @@ float sa_sqrtf(const float x) return u.x; } #else -#define sa_sqrtf(x) sqrtf(x) +//#define sa_sqrtf(x) sqrtf(x) +__attribute__((always_inline)) __STATIC_INLINE float sa_sqrtf(float x){__asm__ ("vsqrt.f32 %0, %1" : "=t"(x) : "t"(x)); return x;} #endif // Function for convert to different type of values from dBm From 328366777f041adaeae65c5a4b128397066825b9 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Sun, 2 May 2021 15:03:39 +0300 Subject: [PATCH 2/8] Auto set SI SPI clock divider from MCU SPI clock --- si4468.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/si4468.c b/si4468.c index 886a0f1..f51dc42 100644 --- a/si4468.c +++ b/si4468.c @@ -55,8 +55,14 @@ #ifdef USE_HARDWARE_SPI_MODE #define SI4432_SPI SPI1 -//#define SI4432_SPI_SPEED SPI_BR_DIV4 // for 72M MCU -#define SI4432_SPI_SPEED SPI_BR_DIV2 // for 48M MCU +// Check device SPI clock speed +#if STM32_PCLK2 > 48000000 // 48 or 72M MCU +// On 72M MCU STM32_PCLK2 = 72M, SPI = 72M/4 = 18M +#define SI4432_SPI_SPEED SPI_BR_DIV4 +#else +// On 48M MCU STM32_PCLK2 = 48M, SPI = 48M/2 = 24M +#define SI4432_SPI_SPEED SPI_BR_DIV2 +#endif //#define ADF_SPI_SPEED SPI_BR_DIV64 //#define ADF_SPI_SPEED SPI_BR_DIV32 From 0ffd8ba6c8c371643f4457333e406c2cb2e50256 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Sun, 2 May 2021 21:37:24 +0300 Subject: [PATCH 3/8] Cleanup --- si4468.c | 71 +++++++++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 40 deletions(-) diff --git a/si4468.c b/si4468.c index f51dc42..c07b3d4 100644 --- a/si4468.c +++ b/si4468.c @@ -68,7 +68,7 @@ //#define ADF_SPI_SPEED SPI_BR_DIV32 #define ADF_SPI_SPEED SPI_BR_DIV2 -#define PE_SPI_SPEED SPI_BR_DIV32 +#define PE_SPI_SPEED SPI_BR_DIV2 static uint32_t old_spi_settings; #else @@ -148,7 +148,7 @@ static uint8_t shiftIn(void) #ifdef USE_HARDWARE_SPI_MODE // while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI)); SPI_WRITE_8BIT(SI4432_SPI, 0xFF); - while (SPI_IS_BUSY(SI4432_SPI) || SPI_RX_IS_EMPTY(SI4432_SPI)) ; // drop rx and wait tx + while (SPI_RX_IS_EMPTY(SI4432_SPI)) ; // drop rx and wait tx return SPI_READ_8BIT(SI4432_SPI); #else uint32_t value = 0; @@ -170,17 +170,10 @@ uint32_t SI4432_offset_delay = 1500; //------------PE4302 ----------------------------------------------- #ifdef __PE4302__ - -// Comment out this define to use parallel mode PE4302 - -#define PE4302_en 10 - void PE4302_init(void) { CS_PE_LOW; } -#define PE4302_DELAY 100 - static unsigned char old_attenuation = 255; bool PE4302_Write_Byte(unsigned char DATA ) { @@ -191,15 +184,18 @@ bool PE4302_Write_Byte(unsigned char DATA ) set_SPI_mode(SPI_MODE_SI); if (SI4432_SPI_SPEED != PE_SPI_SPEED) SPI_BR_SET(SI4432_SPI, PE_SPI_SPEED); - +#if 1 + SPI_WRITE_8BIT(SI4432_SPI, DATA); + while (SPI_IS_BUSY(SI4432_SPI)); +#else shiftOut(DATA); +#endif CS_PE_HIGH; CS_PE_LOW; if (SI4432_SPI_SPEED != PE_SPI_SPEED) SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED); return true; } - #endif //------------------------------- ADF4351 ------------------------------------- @@ -281,10 +277,18 @@ void ADF4351_WriteRegister32(int channel, const uint32_t value) // Select chip CS_ADF_LOW(ADF4351_LE[channel]); // Send 32 bit register +#if 1 + SPI_WRITE_8BIT(SI4432_SPI, (value >> 24)); + SPI_WRITE_8BIT(SI4432_SPI, (value >> 16)); + SPI_WRITE_8BIT(SI4432_SPI, (value >> 8)); + SPI_WRITE_8BIT(SI4432_SPI, (value >> 0)); + while (SPI_IS_BUSY(SI4432_SPI)); // drop rx and wait tx +#else shiftOut((value >> 24) & 0xFF); shiftOut((value >> 16) & 0xFF); shiftOut((value >> 8) & 0xFF); shiftOut((value >> 0) & 0xFF); +#endif // unselect CS_ADF_HIGH(ADF4351_LE[channel]); old_registers[value & 0x07] = registers[value & 0x07]; @@ -568,15 +572,7 @@ static si446x_state_t SI4463_get_state(void); static void SI4463_set_state(si446x_state_t); #define SI4463_READ_CTS (palReadLine(LINE_RX_CTS)) - -static int SI4463_wait_for_cts(void) -{ - while (!SI4463_READ_CTS) { //CTS is read through GPIO -// chThdSleepMicroseconds(100); - my_microsecond_delay(1); - } - return 1; -} +#define SI4463_WAIT_CTS while (!SI4463_READ_CTS); #if 0 // not used static void SI4463_write_byte(uint8_t ADR, uint8_t DATA) @@ -605,15 +601,10 @@ static uint8_t SI4463_read_byte( uint8_t ADR ) { uint8_t DATA ; set_SPI_mode(SPI_MODE_SI); -// SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED); - -// __disable_irq(); SI_CS_LOW; shiftOut( ADR ); DATA = shiftIn(); SI_CS_HIGH; -// __enable_irq(); - return DATA ; } @@ -648,11 +639,7 @@ void SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen) { uint8_t *ptr = (uint8_t *)data; set_SPI_mode(SPI_MODE_SI); - -//#define SHORT_DELAY my_microsecond_delay(1) -//#define SHORT_DELAY - - while (!SI4463_READ_CTS);// {SHORT_DELAY; } // Wait for CTS + SI4463_WAIT_CTS; // Wait for CTS SI_CS_LOW; #if 1 // Inline transfer while (len--){ @@ -667,8 +654,10 @@ void SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen) SI_CS_HIGH; if(out == NULL) return; // If we have an output buffer then read command response into it - while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes - while (!SI4463_READ_CTS);// { SHORT_DELAY; } // Wait for CTS + + while (SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) + (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes from SPI RX buffer + SI4463_WAIT_CTS; // Wait for CTS SI_CS_LOW; #if 1 @@ -1168,6 +1157,7 @@ static bool buf_read = false; static char Si446x_readRSSI(void){ char rssi; + SI4463_WAIT_CTS; // Wait for CTS #ifdef __USE_FFR_FOR_RSSI__ SI_CS_LOW; SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_ID_START_RX); @@ -1188,11 +1178,13 @@ static char Si446x_readRSSI(void){ while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx SI_CS_HIGH; - while (!SI4463_READ_CTS); // Wait for CTS + while (SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) + (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes + SI4463_WAIT_CTS; // Wait for CTS SI_CS_LOW; SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_CMD_BUFF); // read answer while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx - SPI_READ_16BIT(SI4432_SPI); // Drop SI446X_CMD_GET_MODEM_STATUS read and SI446X_CMD_READ_CMD_BUFF read + SPI_READ_8BIT(SI4432_SPI); // Drop SI446X_CMD_READ_CMD_BUFF read SPI_WRITE_16BIT(SI4432_SPI, 0xFFFF); // begin read 2 bytes SPI_WRITE_16BIT(SI4432_SPI, 0xFFFF); // next read 2 bytes while (SPI_IS_BUSY(SI4432_SPI)); // wait tx @@ -1239,9 +1231,10 @@ void SI446x_Fill(int s, int start) systime_t measure = chVTGetSystemTimeX(); int i = start; +// For SI446X_CMD_READ_FRR_A need drop Rx buffer +#if 0 + SI4463_WAIT_CTS; // Wait for CTS while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes -#if 1 - while (!SI4463_READ_CTS); // Wait for CTS #endif __disable_irq(); do { @@ -1327,8 +1320,7 @@ void SI4432_Listen(int s) uint8_t max = 0; uint16_t count = 0; operation_requested = OP_NONE; - while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes - while (!SI4463_READ_CTS); // Wait for CTS +// SI4463_WAIT_CTS; // Wait for CTS do { uint8_t v = Si446x_readRSSI(); if (max < v) // Peak @@ -1359,8 +1351,7 @@ int16_t Si446x_RSSI(void) int i = setting.repeat; int32_t RSSI_RAW = 0; - while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes - while (!SI4463_READ_CTS); // Wait for CTS +// SI4463_WAIT_CTS; // Wait for CTS do{ // if (MODE_INPUT(setting.mode) && RSSI_R #define SAMPLE_COUNT 1 From 7b257ba37e700a5028345c0aa7898975334ce58f Mon Sep 17 00:00:00 2001 From: erikkaashoek Date: Mon, 3 May 2021 08:27:27 +0200 Subject: [PATCH 4/8] Update radio_config_Si4468_100kHz.h --- radio_config_Si4468_100kHz.h | 54 ++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/radio_config_Si4468_100kHz.h b/radio_config_Si4468_100kHz.h index 348d1c7..4caac81 100644 --- a/radio_config_Si4468_100kHz.h +++ b/radio_config_Si4468_100kHz.h @@ -19,15 +19,15 @@ // INPUT DATA /* -// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15 -// MOD_type: 2 Rsymb(sps): 180000 Fdev(Hz): 300000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 2 Rsymb(sps): 50000 Fdev(Hz): 25000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz -// # WB filter 15 (BW = 103.75 kHz); NB-filter 15 (BW = 103.75 kHz) +// # WB filter 2 (BW = 103.06 kHz); NB-filter 2 (BW = 103.06 kHz) // -// Modulation index: 3.333 +// Modulation index: 1 */ @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x11, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -474,7 +474,7 @@ // Descriptions: // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. */ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14 +#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 /* // Set properties: RF_PKT_CONFIG1_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x1B, 0x77, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x07, 0xA1, 0x20, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x03 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6 +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x6A /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x00, 0x20, 0x00, 0xB5, 0x00, 0x53 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xB5, 0x00, 0x4B /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x03, 0x16, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0xAA +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0xDA /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x03, 0x0C, 0x80 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCC, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x02, 0xD5, 0x55, 0x00, 0x28, 0x0C, 0x84, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x04, 0xFE, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0x00, 0x06, 0x00, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x90, 0xA7 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x62, 0x44, 0x25, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00 /* // Set properties: RF_PA_TC_1_1 @@ -755,7 +755,7 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5D +#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x3D /* // Set properties: RF_SYNTH_PFDCP_CPFF_7_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! From 76dd3d8f4540e535268ee0bd83363b4d6f8d2d29 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Mon, 3 May 2021 08:35:43 +0300 Subject: [PATCH 5/8] Use defines in some cases --- si4468.c | 51 ++++++++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/si4468.c b/si4468.c index c07b3d4..9d9908e 100644 --- a/si4468.c +++ b/si4468.c @@ -758,13 +758,24 @@ static void SI4463_set_state(si446x_state_t newState) SI4463_do_api(data, sizeof(data), NULL, 0); } -static uint8_t gpio_state[4] = { 7,8,0,0 }; +static uint8_t gpio_state[4] = { + SI446X_GPIO_MODE_DIV_CLK, + SI446X_GPIO_MODE_CTS, + SI446X_GPIO_MODE_DONOTHING, + SI446X_GPIO_MODE_DONOTHING +}; void SI4463_refresh_gpio(void) { - uint8_t data2[] = - { - 0x13, gpio_state[0], gpio_state[1], gpio_state[2], gpio_state[3], 0, 0, 0 + uint8_t data2[] = { + SI446X_CMD_GPIO_PIN_CFG, + gpio_state[0], // GPIO[0] + gpio_state[1], // GPIO[1] + gpio_state[2], // GPIO[2] + gpio_state[3], // GPIO[3] + 0, // NIRQ + 0, // SDO + 0 // GEN_CONFIG }; SI4463_do_api(data2, sizeof(data2), NULL, 0); } @@ -797,9 +808,8 @@ void SI4463_set_output_level(int t) if (SI4463_in_tx_mode) { #if 1 { - uint8_t data[] = - { - 0x11, 0x22, 0x04, 0x00, // PA_MODE + uint8_t data[] = { + SI446X_CMD_SET_PROPERTY, 0x22, 0x04, 0x00, // PA_MODE 0x08, // Coarse PA mode and class E PA Fine PA mode = 0x04 (uint8_t)SI4463_output_level, // Level 0x00, // Duty @@ -828,9 +838,8 @@ void SI4463_start_tx(uint8_t CHANNEL) #endif #if 1 { - uint8_t data[] = - { - 0x11, 0x20, 0x01, 0x00, + uint8_t data[] = { + SI446X_CMD_SET_PROPERTY, 0x20, 0x01, 0x00, 0x00, // CW mode }; SI4463_do_api(data, sizeof(data), NULL, 0); @@ -838,9 +847,8 @@ void SI4463_start_tx(uint8_t CHANNEL) #endif #if 1 { - uint8_t data[] = - { - 0x11, 0x22, 0x04, 0x00, // PA_MODE + uint8_t data[] = { + SI446X_CMD_SET_PROPERTY, 0x22, 0x04, 0x00, // PA_MODE 0x08, // Coarse PA mode and class E PA Fine PA mode = 0x04 (uint8_t)SI4463_output_level, // Level 0x00, // Duty @@ -878,7 +886,7 @@ void SI4463_start_tx(uint8_t CHANNEL) void SI4463_start_rx(uint8_t CHANNEL) { - si446x_state_t s = SI4463_get_state(); + si446x_state_t s = SI4463_get_state(); if (s == SI446X_STATE_TX){ SI4463_set_state(SI446X_STATE_READY); } @@ -953,15 +961,14 @@ void SI4463_clear_int_status(void) void set_calibration_freq(int ref) { if (ref >= 0) { - SI4463_set_gpio(0, 7); // GPIO 0 is clock out - - uint8_t data2[5] = { - 0x11, 0x00, 0x01, 0x01, 0x40 // GLOBAL_CLK_CFG Clock config + SI4463_set_gpio(0, SI446X_GPIO_MODE_DIV_CLK); // GPIO 0 is clock out + uint8_t data2[5] = { // GLOBAL_CLK_CFG Clock config + SI446X_CMD_SET_PROPERTY, SI446X_PROP_GROUP_GLOBAL, 0x01, 0x01, + 0x40|(ref<<3)// DIVIDED_CLK_EN = 1, DIVIDED_CLK_SEL = ref, CLK_32K_SEL = 0 }; - data2[4] |= ref<<3; SI4463_do_api(data2, 5, NULL, 0); } else { - SI4463_set_gpio(0, 1); // stop clock out + SI4463_set_gpio(0, SI446X_GPIO_MODE_TRISTATE); // stop clock out } } @@ -969,9 +976,7 @@ si446x_info_t SI4463_info; void Si446x_getInfo(si446x_info_t* info) { - uint8_t data[8] = { - SI446X_CMD_PART_INFO - }; + uint8_t data[8] = {SI446X_CMD_PART_INFO}; SI4463_do_api(data, 1, data, 8); info->chipRev = data[0]; From 2d4864658cb4bf5f0298a1b6dc6d4f3ac8f0d6f7 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Mon, 3 May 2021 08:41:19 +0300 Subject: [PATCH 6/8] Remove hack --- si4468.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/si4468.c b/si4468.c index 9d9908e..f52cd07 100644 --- a/si4468.c +++ b/si4468.c @@ -1004,10 +1004,7 @@ float Si446x_get_temp(void) { uint8_t data[8] = { SI446X_CMD_GET_ADC_READING, 0x10, 0 }; SI4463_do_api(data, 3, data, 8); - int i = 4; - if (data[0]==255) - i = 6; - float t = (data[i] << 8) + data[i+1]; + float t = (data[4] << 8) + data[5]; t = (899.0 * t /4096.0) - 293.0; if (t > old_temp - TEMP_HISTERESE && t < old_temp + TEMP_HISTERESE) { return(old_temp); From 82097cd011ae10028785105d9402548381f963d6 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Mon, 3 May 2021 08:54:15 +0300 Subject: [PATCH 7/8] Use one offset api call --- si4468.c | 65 +++++++++++++++++++------------------------------------- 1 file changed, 22 insertions(+), 43 deletions(-) diff --git a/si4468.c b/si4468.c index f52cd07..20023ec 100644 --- a/si4468.c +++ b/si4468.c @@ -1082,22 +1082,19 @@ void set_RSSI_comp(void) // MODEM_RSSI_COMP - RSSI compensation value. // // #define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40 - uint8_t data[5] = { - 0x11, - 0x20, - 0x01, - 0x4E, - 0x40 + SI446X_CMD_SET_PROPERTY, + SI446X_PROP_GROUP_MODEM, + 0x01, + 0x4E, // MODEM_RSSI_COMP set as + 0x40 // RSSI_COMP }; SI4463_do_api(data, sizeof(data), NULL, 0); } -int SI4463_offset_active = false; - -void si_set_offset(int16_t offset) -{ +bool SI4463_offset_active = false; +static void SI4463_set_offset(int16_t offset){ // Set properties: MODEM_FREQ_OFFSET // Number of properties: 2 // Group ID: 0x20 @@ -1107,49 +1104,31 @@ void si_set_offset(int16_t offset) // MODEM_FREQ_OFFSET1 - High byte of the offset // MODEM_FREQ_OFFSET2 - Low byte of the offset // - - SI4463_offset_value = offset; uint8_t data[] = { - 0x11, - 0x20, - 0x02, - 0x0d, - (uint8_t) ((offset>>8) & 0xff), - (uint8_t) ((offset) & 0xff) + SI446X_CMD_SET_PROPERTY, + SI446X_PROP_GROUP_MODEM, + 0x02, + 0x0d, // MODEM_FREQ_OFFSET + (uint8_t) ((offset>>8) & 0xff), + (uint8_t) ((offset) & 0xff) }; SI4463_do_api(data, sizeof(data), NULL, 0); SI4463_offset_changed = true; SI4463_offset_active = (offset != 0); } +// Set offset for frequency +void si_set_offset(int16_t offset) +{ + SI4463_offset_value = offset; + SI4463_set_offset(offset); +} +// Set additional offset for fm modulation output void si_fm_offset(int16_t offset) { - // Set properties: MODEM_FREQ_OFFSET - // Number of properties: 2 - // Group ID: 0x20 - // Start ID: 0x0d - // Default values: 0x00, 0x00 - // Descriptions: - // MODEM_FREQ_OFFSET1 - High byte of the offset - // MODEM_FREQ_OFFSET2 - Low byte of the offset - // - - offset = SI4463_offset_value + offset; - - - - uint8_t data[] = { - 0x11, - 0x20, - 0x02, - 0x0d, - (uint8_t) ((offset>>8) & 0xff), - (uint8_t) ((offset) & 0xff) - }; - SI4463_do_api(data, sizeof(data), NULL, 0); - SI4463_offset_changed = true; - SI4463_offset_active = (offset != 0); + SI4463_set_offset(offset + SI4463_offset_value); } + #ifdef __FAST_SWEEP__ extern deviceRSSI_t age[POINTS_COUNT]; static int buf_index = 0; From 421310205e92e7713fe5bb169a7eeac4f59c0e0c Mon Sep 17 00:00:00 2001 From: DiSlord Date: Mon, 3 May 2021 08:55:30 +0300 Subject: [PATCH 8/8] Code style --- si4468.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/si4468.c b/si4468.c index 20023ec..d5a9da5 100644 --- a/si4468.c +++ b/si4468.c @@ -1093,7 +1093,7 @@ void set_RSSI_comp(void) } -bool SI4463_offset_active = false; +static bool SI4463_offset_active = false; static void SI4463_set_offset(int16_t offset){ // Set properties: MODEM_FREQ_OFFSET // Number of properties: 2 @@ -1118,14 +1118,13 @@ static void SI4463_set_offset(int16_t offset){ } // Set offset for frequency -void si_set_offset(int16_t offset) -{ +void si_set_offset(int16_t offset) { SI4463_offset_value = offset; SI4463_set_offset(offset); } + // Set additional offset for fm modulation output -void si_fm_offset(int16_t offset) -{ +void si_fm_offset(int16_t offset) { SI4463_set_offset(offset + SI4463_offset_value); }