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Removed port names

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Removed_REF_marker
erikkaashoek 5 years ago
parent 5b1f2cfcee
commit d21044b276
4 changed files with 178 additions and 98 deletions
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161
NANOVNA_STM32_F303/board.h
Unescape View File

@ -27,6 +27,7 @@
#define BOARD_NANOVNA_STM32_F303
#define BOARD_NAME "tinySA-H4"
#include <stm32f303xc.h>
/*
* Board frequencies.
*/
@ -63,33 +64,41 @@
#define GPIOA_XP 6
#define GPIOA_YP 7
//#define GPIOA_MCO 8
#define GPIO_PE_SEL 9
#define GPIO_PE GPIOA
#define GPIOA_RF_PWR 10
#define GPIO_PE_SEL 9
#define GPIO_PE_SEL_PORT GPIOA
#define GPIO_RF_PWR 10
#define GPIO_RF_PWR_PORT GPIOA
#define GPIOA_USB_DM 11
#define GPIOA_USB_DP 12
#define GPIOA_JTMS 13
#define GPIOA_JTCK 14
#define GPIOA_LCD_RESET 15
#define GPIO_LCD_RESET 15
#define GPIO_LCD_RESET_PORT GPIOA
#define GPIOB_XN 0
#define GPIOB_YN 1
#define GPIOB_RX_SEL 2
#define GPIO_RX_SEL 2
#define GPIO_RX_SEL_PORT GPIOB
#define GPIOB_SPI_SCLK 3
#define GPIOB_SPI_MISO 4
#define GPIOB_SPI_MOSI 5
#define GPIOB_LCD_CS 6
#define GPIOB_LCD_CD 7
#define GPIOB_I2C1_SCL 8
#define GPIOB_I2C1_SDA 9
#define GPIOB_LO_SEL 10
#define GPIOB_SD_CS 11
#define GPIOB_I2S2_WCLK 12
#define GPIOB_I2S2_BCLK 13
#define GPIOB_I2S2_MISO 14
#define GPIOB_I2S2_MOSI 15
#define GPIO_LCD_CS 6
#define GPIO_LCD_CS_PORT GPIOB
#define GPIO_LCD_CD 7
#define GPIO_LCD_CD_PORT GPIOB
//#define 8 8
//#define 9 9
#define GPIO_LO_SEL 10
#define GPIO_LO_SEL_PORT GPIOB
#define GPIO_SD_CS 11
#define GPIO_SD_CS_PORT GPIOB
//#define 12 12
//#define 13 13
//#define GPIOB_I2S2_MISO 14
//#define 15 15
#define GPIOC_LED 13
#define GPIO_LED 13
#define GPIO_LED_PORT GPIOC
#define GPIOF_OSC_IN 0
#define GPIOF_OSC_OUT 1
@ -136,12 +145,12 @@
PIN_MODE_ANALOG(GPIOA_YP) | \
PIN_MODE_ALTERNATE(8U) | \
PIN_MODE_OUTPUT(GPIO_PE_SEL) | \
PIN_MODE_OUTPUT(GPIOA_RF_PWR) | \
PIN_MODE_OUTPUT(GPIO_RF_PWR) | \
PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
PIN_MODE_ALTERNATE(GPIOA_JTMS) | \
PIN_MODE_ALTERNATE(GPIOA_JTCK) | \
PIN_MODE_OUTPUT(GPIOA_LCD_RESET))
PIN_MODE_OUTPUT(GPIO_LCD_RESET))
#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0U) | \
PIN_OTYPE_PUSHPULL(1U) | \
PIN_OTYPE_PUSHPULL(2U) | \
@ -152,12 +161,12 @@
PIN_OTYPE_PUSHPULL(7U) | \
PIN_OTYPE_PUSHPULL(8U) | \
PIN_OTYPE_PUSHPULL(GPIO_PE_SEL) | \
PIN_OTYPE_PUSHPULL(GPIOA_RF_PWR) | \
PIN_OTYPE_PUSHPULL(GPIO_RF_PWR) | \
PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \
PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \
PIN_OTYPE_PUSHPULL(GPIOA_LCD_RESET))
PIN_OTYPE_PUSHPULL(GPIO_LCD_RESET))
#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(0) | \
PIN_OSPEED_2M(1) | \
PIN_OSPEED_2M(2) | \
@ -168,12 +177,12 @@
PIN_OSPEED_2M(7) | \
PIN_OSPEED_100M(8U) | \
PIN_OSPEED_100M(GPIO_PE_SEL) | \
PIN_OSPEED_100M(GPIOA_RF_PWR) | \
PIN_OSPEED_100M(GPIO_RF_PWR) | \
PIN_OSPEED_100M(GPIOA_USB_DM) | \
PIN_OSPEED_100M(GPIOA_USB_DP) | \
PIN_OSPEED_100M(GPIOA_JTMS) | \
PIN_OSPEED_100M(GPIOA_JTCK) | \
PIN_OSPEED_100M(GPIOA_LCD_RESET))
PIN_OSPEED_100M(GPIO_LCD_RESET))
#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \
PIN_PUPDR_PULLDOWN(1) | \
PIN_PUPDR_PULLDOWN(2) | \
@ -184,12 +193,12 @@
PIN_PUPDR_FLOATING(7) | \
PIN_PUPDR_PULLUP(8U) | \
PIN_PUPDR_PULLUP(GPIO_PE_SEL) | \
PIN_PUPDR_PULLUP(GPIOA_RF_PWR) | \
PIN_PUPDR_PULLUP(GPIO_RF_PWR) | \
PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
PIN_PUPDR_PULLDOWN(GPIOA_JTMS) | \
PIN_PUPDR_PULLDOWN(GPIOA_JTCK) | \
PIN_PUPDR_PULLDOWN(GPIOA_LCD_RESET))
PIN_PUPDR_PULLDOWN(GPIO_LCD_RESET))
#define VAL_GPIOA_ODR (PIN_ODR_HIGH(0) | \
PIN_ODR_HIGH(1) | \
PIN_ODR_HIGH(2) | \
@ -200,12 +209,12 @@
PIN_ODR_HIGH(7) | \
PIN_ODR_HIGH(8U) | \
PIN_ODR_HIGH(GPIO_PE_SEL) | \
PIN_ODR_HIGH(GPIOA_RF_PWR) | \
PIN_ODR_HIGH(GPIO_RF_PWR) | \
PIN_ODR_HIGH(GPIOA_USB_DM) | \
PIN_ODR_HIGH(GPIOA_USB_DP) | \
PIN_ODR_HIGH(GPIOA_JTMS) | \
PIN_ODR_HIGH(GPIOA_JTCK) | \
PIN_ODR_HIGH(GPIOA_LCD_RESET))
PIN_ODR_HIGH(GPIO_LCD_RESET))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \
PIN_AFIO_AF(1, 0) | \
PIN_AFIO_AF(2, 0) | \
@ -216,12 +225,12 @@
PIN_AFIO_AF(7, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8U, 0) | \
PIN_AFIO_AF(GPIO_PE_SEL, 0) | \
PIN_AFIO_AF(GPIOA_RF_PWR, 0) | \
PIN_AFIO_AF(GPIO_RF_PWR, 0) | \
PIN_AFIO_AF(GPIOA_USB_DM, 14) | \
PIN_AFIO_AF(GPIOA_USB_DP, 14) | \
PIN_AFIO_AF(GPIOA_JTMS, 0) | \
PIN_AFIO_AF(GPIOA_JTCK, 0) | \
PIN_AFIO_AF(GPIOA_LCD_RESET, 0))
PIN_AFIO_AF(GPIO_LCD_RESET, 0))
/*
* GPIOB setup:
@ -239,100 +248,100 @@
*/
#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_XN) | \
PIN_MODE_ANALOG(GPIOB_YN) | \
PIN_MODE_OUTPUT(GPIOB_RX_SEL) | \
PIN_MODE_OUTPUT(GPIO_RX_SEL) | \
PIN_MODE_ALTERNATE(GPIOB_SPI_SCLK) | \
PIN_MODE_ALTERNATE(GPIOB_SPI_MISO) | \
PIN_MODE_ALTERNATE(GPIOB_SPI_MOSI) | \
PIN_MODE_OUTPUT(6) | \
PIN_MODE_OUTPUT(7) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
PIN_MODE_OUTPUT(GPIOB_LO_SEL) | \
PIN_MODE_OUTPUT(GPIOB_SD_CS) | \
PIN_MODE_ALTERNATE(GPIOB_I2S2_WCLK) | \
PIN_MODE_ALTERNATE(GPIOB_I2S2_BCLK) | \
PIN_MODE_ALTERNATE(8) | \
PIN_MODE_ALTERNATE(9) | \
PIN_MODE_OUTPUT(GPIO_LO_SEL) | \
PIN_MODE_OUTPUT(GPIO_SD_CS) | \
PIN_MODE_ALTERNATE(12) | \
PIN_MODE_ALTERNATE(13) | \
PIN_MODE_ALTERNATE(14) | \
PIN_MODE_ALTERNATE(GPIOB_I2S2_MOSI))
PIN_MODE_ALTERNATE(15))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \
PIN_OTYPE_PUSHPULL(1) | \
PIN_OTYPE_PUSHPULL(GPIOB_RX_SEL) | \
PIN_OTYPE_PUSHPULL(GPIO_RX_SEL) | \
PIN_OTYPE_PUSHPULL(3) | \
PIN_OTYPE_PUSHPULL(4) | \
PIN_OTYPE_PUSHPULL(5) | \
PIN_OTYPE_PUSHPULL(6) | \
PIN_OTYPE_PUSHPULL(7) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \
PIN_OTYPE_PUSHPULL(GPIOB_LO_SEL) | \
PIN_OTYPE_PUSHPULL(GPIOB_SD_CS) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_WCLK) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_BCLK) | \
PIN_OTYPE_PUSHPULL(8) | \
PIN_OTYPE_PUSHPULL(9) | \
PIN_OTYPE_PUSHPULL(GPIO_LO_SEL) | \
PIN_OTYPE_PUSHPULL(GPIO_SD_CS) | \
PIN_OTYPE_PUSHPULL(12) | \
PIN_OTYPE_PUSHPULL(13) | \
PIN_OTYPE_PUSHPULL(14) | \
PIN_OTYPE_PUSHPULL(GPIOB_I2S2_MOSI))
PIN_OTYPE_PUSHPULL(15))
#define VAL_GPIOB_OSPEEDR (PIN_PUPDR_FLOATING(GPIOB_XN) | \
PIN_PUPDR_FLOATING(GPIOB_YN) | \
PIN_OSPEED_100M(GPIOB_RX_SEL) | \
PIN_OSPEED_100M(GPIO_RX_SEL) | \
PIN_OSPEED_100M(3) | \
PIN_OSPEED_100M(4) | \
PIN_OSPEED_100M(5) | \
PIN_OSPEED_100M(6) | \
PIN_OSPEED_100M(7) | \
PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \
PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \
PIN_OSPEED_100M(GPIOB_LO_SEL) | \
PIN_OSPEED_100M(GPIOB_SD_CS) | \
PIN_OSPEED_100M(GPIOB_I2S2_WCLK) | \
PIN_OSPEED_100M(GPIOB_I2S2_BCLK) | \
PIN_OSPEED_100M(8) | \
PIN_OSPEED_100M(9) | \
PIN_OSPEED_100M(GPIO_LO_SEL) | \
PIN_OSPEED_100M(GPIO_SD_CS) | \
PIN_OSPEED_100M(12) | \
PIN_OSPEED_100M(13) | \
PIN_OSPEED_100M(14) | \
PIN_OSPEED_100M(GPIOB_I2S2_MOSI))
PIN_OSPEED_100M(15))
#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(0) | \
PIN_PUPDR_PULLUP(1) | \
PIN_PUPDR_PULLUP(GPIOB_RX_SEL) | \
PIN_PUPDR_PULLUP(GPIO_RX_SEL) | \
PIN_PUPDR_PULLUP(3) | \
PIN_PUPDR_PULLUP(4) | \
PIN_PUPDR_PULLUP(5) | \
PIN_PUPDR_PULLUP(6) | \
PIN_PUPDR_PULLUP(7) | \
PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \
PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \
PIN_PUPDR_PULLUP(GPIOB_LO_SEL) | \
PIN_PUPDR_PULLUP(GPIOB_SD_CS) | \
PIN_PUPDR_PULLUP(GPIOB_I2S2_WCLK) | \
PIN_PUPDR_PULLUP(GPIOB_I2S2_BCLK) | \
PIN_PUPDR_PULLUP(8) | \
PIN_PUPDR_PULLUP(9) | \
PIN_PUPDR_PULLUP(GPIO_LO_SEL) | \
PIN_PUPDR_PULLUP(GPIO_SD_CS) | \
PIN_PUPDR_PULLUP(12) | \
PIN_PUPDR_PULLUP(13) | \
PIN_PUPDR_PULLUP(14) | \
PIN_PUPDR_PULLUP(GPIOB_I2S2_MOSI))
PIN_PUPDR_PULLUP(15))
#define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \
PIN_ODR_HIGH(1) | \
PIN_ODR_HIGH(GPIOB_RX_SEL) | \
PIN_ODR_HIGH(GPIO_RX_SEL) | \
PIN_ODR_HIGH(3) | \
PIN_ODR_HIGH(4) | \
PIN_ODR_HIGH(5) | \
PIN_ODR_HIGH(6) | \
PIN_ODR_HIGH(7) | \
PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \
PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \
PIN_ODR_HIGH(GPIOB_LO_SEL) | \
PIN_ODR_HIGH(GPIOB_SD_CS) | \
PIN_ODR_HIGH(GPIOB_I2S2_WCLK) | \
PIN_ODR_HIGH(GPIOB_I2S2_BCLK) | \
PIN_ODR_HIGH(8) | \
PIN_ODR_HIGH(9) | \
PIN_ODR_HIGH(GPIO_LO_SEL) | \
PIN_ODR_HIGH(GPIO_SD_CS) | \
PIN_ODR_HIGH(12) | \
PIN_ODR_HIGH(13) | \
PIN_ODR_HIGH(14) | \
PIN_ODR_HIGH(GPIOB_I2S2_MOSI))
PIN_ODR_HIGH(15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \
PIN_AFIO_AF(1, 0) | \
PIN_AFIO_AF(GPIOB_RX_SEL, 0) | \
PIN_AFIO_AF(GPIO_RX_SEL, 0) | \
PIN_AFIO_AF(GPIOB_SPI_SCLK, 5) | \
PIN_AFIO_AF(GPIOB_SPI_MOSI, 5) | \
PIN_AFIO_AF(GPIOB_SPI_MISO, 5) | \
PIN_AFIO_AF(6, 0) | \
PIN_AFIO_AF(7, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
PIN_AFIO_AF(GPIOB_LO_SEL, 0) | \
PIN_AFIO_AF(GPIOB_SD_CS, 0) | \
PIN_AFIO_AF(GPIOB_I2S2_WCLK, 5) | \
PIN_AFIO_AF(GPIOB_I2S2_BCLK, 5) | \
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 4) | \
PIN_AFIO_AF(9, 4) | \
PIN_AFIO_AF(GPIO_LO_SEL, 0) | \
PIN_AFIO_AF(GPIO_SD_CS, 0) | \
PIN_AFIO_AF(12, 5) | \
PIN_AFIO_AF(13, 5) | \
PIN_AFIO_AF(14, 0) | \
PIN_AFIO_AF(GPIOB_I2S2_MOSI, 5))
PIN_AFIO_AF(15, 5))
/*
* GPIOC setup:
*

12
ili9341.c
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@ -27,12 +27,12 @@
#define __USE_DISPLAY_DMA_RX__
// Pin macros for LCD
#define LCD_CS_LOW palClearPad(GPIOB, GPIOB_LCD_CS)
#define LCD_CS_HIGH palSetPad(GPIOB, GPIOB_LCD_CS)
#define LCD_RESET_ASSERT palClearPad(GPIOA, GPIOA_LCD_RESET)
#define LCD_RESET_NEGATE palSetPad(GPIOA, GPIOA_LCD_RESET)
#define LCD_DC_CMD palClearPad(GPIOB, GPIOB_LCD_CD)
#define LCD_DC_DATA palSetPad(GPIOB, GPIOB_LCD_CD)
#define LCD_CS_LOW palClearPad(GPIO_LCD_CS_PORT, GPIO_LCD_CS)
#define LCD_CS_HIGH palSetPad(GPIO_LCD_CS_PORT, GPIO_LCD_CS)
#define LCD_RESET_ASSERT palClearPad(GPIO_LCD_RESET_PORT, GPIO_LCD_RESET)
#define LCD_RESET_NEGATE palSetPad(GPIO_LCD_RESET_PORT, GPIO_LCD_RESET)
#define LCD_DC_CMD palClearPad(GPIO_LCD_CD_PORT, GPIO_LCD_CD)
#define LCD_DC_DATA palSetPad(GPIO_LCD_CD_PORT, GPIO_LCD_CD)
#define LCD_SPI SPI1
// Set SPI bus speed for LCD

71
radio_config_Si4468_undef.h
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@ -0,0 +1,71 @@
#ifdef RADIO_CONFIG_H_
#undef RADIO_CONFIG_H_
#undef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
#undef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
#undef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
#undef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
#undef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
#undef RF_POWER_UP
#undef RF_GPIO_PIN_CFG
#undef RF_GLOBAL_XO_TUNE_1
#undef RF_GLOBAL_CONFIG_1
#undef RF_PREAMBLE_CONFIG_1
#undef RF_MODEM_MOD_TYPE_12
#undef RF_MODEM_FREQ_DEV_0_1
#undef RF_MODEM_TX_RAMP_DELAY_12
#undef RF_MODEM_BCR_NCO_OFFSET_2_12
#undef RF_MODEM_AFC_LIMITER_1_3
#undef RF_MODEM_AGC_CONTROL_1
#undef RF_MODEM_AGC_WINDOW_SIZE_12
#undef RF_MODEM_RAW_CONTROL_5
#undef RF_MODEM_RSSI_JUMP_THRESH_4
#undef RF_MODEM_RAW_SEARCH2_2
#undef RF_MODEM_SPIKE_DET_2
#undef RF_MODEM_RSSI_MUTE_1
#undef RF_MODEM_DSA_CTRL1_5
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
#undef RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
#undef RF_PA_TC_1
#undef RF_SYNTH_PFDCP_CPFF_7
#undef RF_FREQ_CONTROL_INTE_8
#undef RF_START_RX
#undef RF_IRCAL
#undef RF_IRCAL_1
#undef RF_GLOBAL_CLK_CFG_1
#undef RF_GLOBAL_CONFIG_1_1
#undef RF_INT_CTL_ENABLE_1
#undef RF_FRR_CTL_A_MODE_4
#undef RF_PREAMBLE_CONFIG_STD_1_1
#undef RF_PKT_CONFIG1_1
#undef RF_MODEM_MOD_TYPE_12_1
#undef RF_MODEM_FREQ_DEV_0_1_1
#undef RF_MODEM_TX_RAMP_DELAY_12_1
#undef RF_MODEM_BCR_NCO_OFFSET_2_12_1
#undef RF_MODEM_AFC_LIMITER_1_3_1
#undef RF_MODEM_AGC_CONTROL_1_1
#undef RF_MODEM_AGC_WINDOW_SIZE_12_1
#undef RF_MODEM_RAW_CONTROL_10
#undef RF_MODEM_RAW_SEARCH2_2_1
#undef RF_MODEM_SPIKE_DET_2_1
#undef RF_MODEM_RSSI_MUTE_1_1
#undef RF_MODEM_DSA_CTRL1_5_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1
#undef RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1
#undef RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1
#undef RF_PA_TC_1_1
#undef RF_SYNTH_PFDCP_CPFF_7_1
#undef RF_FREQ_CONTROL_INTE_8_1
#undef RADIO_CONFIGURATION_DATA_ARRAY
#undef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
#undef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
#undef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
#undef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
#undef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
#undef RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED
#undef RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE
#undef RADIO_CONFIGURATION_DATA_RADIO_PATCH
#undef RADIO_CONFIGURATION_DATA
#endif /* RADIO_CONFIG_H_ */

32
si4432.c
Unescape View File

@ -52,16 +52,16 @@ static uint32_t new_port_moder;
#endif
#define CS_SI0_HIGH palSetPad(GPIOB, GPIOB_RX_SEL)
#define CS_SI1_HIGH palSetPad(GPIOB, GPIOB_LO_SEL)
#define CS_SI0_HIGH palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL)
#define CS_SI1_HIGH palSetPad(GPIO_RX_SEL_PORT, GPIOB_LO_SEL)
//#define CS_PE_HIGH palSetPad(GPIOA, GPIOA_PE_SEL)
#define RF_POWER_HIGH palSetPad(GPIOB, GPIOB_RF_PWR)
//#define SPI2_CLK_HIGH palSetPad(GPIOB, GPIO_SPI2_CLK)
//#define SPI2_CLK_LOW palClearPad(GPIOB, GPIO_SPI2_CLK)
#define CS_SI0_LOW palClearPad(GPIOB, GPIOB_RX_SEL)
#define CS_SI1_LOW palClearPad(GPIOB, GPIOB_LO_SEL)
#define CS_SI0_LOW palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL)
#define CS_SI1_LOW palClearPad(GPIO_RX_SEL_PORT, GPIOB_LO_SEL)
//#define CS_PE_LOW palClearPad(GPIOA, GPIOA_PE_SEL)
#define SPI1_CLK_HIGH palSetPad(GPIOB, GPIOB_SPI_SCLK)
@ -74,8 +74,8 @@ static uint32_t new_port_moder;
#define SPI1_SDO ((palReadPort(GPIOB)>>GPIOB_SPI_MISO)&1)
#define SPI1_portSDO (palReadPort(GPIOB)&(1<<GPIOB_SPI_MISO))
#ifdef __PE4302__
#define CS_PE_HIGH palSetPad(GPIO_PE, GPIO_PE_SEL)
#define CS_PE_LOW palClearPad(GPIO_PE, GPIO_PE_SEL)
#define CS_PE_HIGH palSetPad(GPIO_PE_SEL_PORT, GPIO_PE_SEL)
#define CS_PE_LOW palClearPad(GPIO_PE_SEL_PORT, GPIO_PE_SEL)
#endif
//#define MAXLOG 1024
@ -1212,22 +1212,22 @@ int SI4463_wait_for_cts(void)
void SI4463_write_byte(uint8_t ADR, uint8_t DATA)
{
set_SPI_mode(SPI_MODE_SI);
palClearPad(GPIOB, GPIOB_RX_SEL);
palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
ADR |= 0x80 ; // RW = 1
shiftOut( ADR );
shiftOut( DATA );
palSetPad(GPIOB, GPIOB_RX_SEL);
palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
}
void SI4463_write_buffer(uint8_t ADR, uint8_t *DATA, int len)
{
set_SPI_mode(SPI_MODE_SI);
palClearPad(GPIOB, GPIOB_RX_SEL);
palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
ADR |= 0x80 ; // RW = 1
shiftOut( ADR );
while (len-- > 0)
shiftOut( *(DATA++) );
palSetPad(GPIOB, GPIOB_RX_SEL);
palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
}
@ -1236,10 +1236,10 @@ uint8_t SI4463_read_byte( uint8_t ADR )
set_SPI_mode(SPI_MODE_SI);
uint8_t DATA ;
set_SPI_mode(SPI_MODE_SI);
palClearPad(GPIOB, GPIOB_RX_SEL);
palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
shiftOut( ADR );
DATA = shiftIn();
palSetPad(GPIOB, GPIOB_RX_SEL);
palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
return DATA ;
}
@ -1251,7 +1251,7 @@ uint8_t SI4463_get_response(void* buff, uint8_t len)
if (!cts) {
return false;
}
palClearPad(GPIOB, GPIOB_RX_SEL);
palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
shiftOut( SI446X_CMD_READ_CMD_BUFF );
cts = (shiftIn() == 0xFF);
if (cts)
@ -1261,7 +1261,7 @@ uint8_t SI4463_get_response(void* buff, uint8_t len)
((uint8_t*)buff)[i] = shiftIn();
}
}
palSetPad(GPIOB, GPIOB_RX_SEL);
palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
return cts;
}
@ -1289,11 +1289,11 @@ void SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen)
if (SI4463_wait_for_cts())
#endif
{
palClearPad(GPIOB, GPIOB_RX_SEL);
palClearPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
for(uint8_t i=0;i<len;i++) {
shiftOut(((uint8_t*)data)[i]); // (pgm_read_byte(&((uint8_t*)data)[i]));
}
palSetPad(GPIOB, GPIOB_RX_SEL);
palSetPad(GPIO_RX_SEL_PORT, GPIO_RX_SEL);
#if 0
if(((uint8_t*)data)[0] == SI446X_CMD_IRCAL) // If we're doing an IRCAL then wait for its completion without a timeout since it can sometimes take a few seconds
#if 0

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