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@ -69,15 +69,17 @@ si5351_init(void)
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}
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}
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static const uint8_t disable_output[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_CLK_POWERDOWN,
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SI5351_CLK_POWERDOWN,
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SI5351_CLK_POWERDOWN
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};
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void si5351_disable_output(void)
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{
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uint8_t reg[4];
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0xff);
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reg[0] = SI5351_REG_16_CLK0_CONTROL;
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reg[1] = SI5351_CLK_POWERDOWN;
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reg[2] = SI5351_CLK_POWERDOWN;
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reg[3] = SI5351_CLK_POWERDOWN;
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si5351_bulk_write(reg, 4);
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si5351_bulk_write(disable_output, sizeof(disable_output));
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}
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void si5351_enable_output(void)
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@ -85,19 +87,19 @@ void si5351_enable_output(void)
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si5351_write(SI5351_REG_3_OUTPUT_ENABLE_CONTROL, 0x00);
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}
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void si5351_reset_pll(void)
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static void si5351_reset_pll(void)
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{
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//si5351_write(SI5351_REG_177_PLL_RESET, SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
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si5351_write(SI5351_REG_177_PLL_RESET, 0xAC);
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}
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void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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static void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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uint8_t mult,
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uint32_t num,
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uint32_t denom)
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{
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/* Get the appropriate starting point for the PLL registers */
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const uint8_t pllreg_base[] = {
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static const uint8_t pllreg_base[] = {
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SI5351_REG_26_PLL_A,
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SI5351_REG_34_PLL_B
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};
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@ -147,9 +149,9 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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si5351_bulk_write(reg, 9);
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}
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void
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static void
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si5351_setupMultisynth(uint8_t output,
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uint8_t pllSource,
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uint8_t pllSource,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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@ -157,12 +159,12 @@ si5351_setupMultisynth(uint8_t output,
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uint8_t drive_strength)
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{
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/* Get the appropriate starting point for the PLL registers */
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const uint8_t msreg_base[] = {
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static const uint8_t msreg_base[] = {
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SI5351_REG_42_MULTISYNTH0,
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SI5351_REG_50_MULTISYNTH1,
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SI5351_REG_58_MULTISYNTH2,
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};
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const uint8_t clkctrl[] = {
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static const uint8_t clkctrl[] = {
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SI5351_REG_16_CLK0_CONTROL,
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SI5351_REG_17_CLK1_CONTROL,
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SI5351_REG_18_CLK2_CONTROL
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@ -226,7 +228,7 @@ si5351_setupMultisynth(uint8_t output,
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#define PLL_N 32
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#define PLLFREQ (XTALFREQ * PLL_N)
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void
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static void
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si5351_set_frequency_fixedpll(int channel, int pll, uint32_t pllfreq, uint32_t freq,
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int rdiv, uint8_t drive_strength, int mul)
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{
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@ -255,7 +257,7 @@ si5351_set_frequency_fixedpll(int channel, int pll, uint32_t pllfreq, uint32_t f
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si5351_setupMultisynth(channel, pll, div, num, denom, rdiv, drive_strength);
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}
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void
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static void
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si5351_set_frequency_fixeddiv(int channel, int pll, uint32_t freq, int div,
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uint8_t drive_strength, int mul)
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{
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@ -291,6 +293,7 @@ si5351_set_frequency_fixeddiv(int channel, int pll, uint32_t freq, int div,
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* 100~150MHz fractional PLL 600-900MHz, fixed divider 6
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* 150~200MHz fractional PLL 600-900MHz, fixed divider 4
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*/
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#if 0
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void
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si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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{
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@ -303,7 +306,7 @@ si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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si5351_set_frequency_fixeddiv(channel, SI5351_PLL_B, freq, 4, drive_strength, 1);
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}
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}
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#endif
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int current_band = -1;
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