diff --git a/SI4463_radio_config.h b/SI4463_radio_config.h index 06e7adb..a067f59 100644 --- a/SI4463_radio_config.h +++ b/SI4463_radio_config.h @@ -10,6 +10,8 @@ * @n Copyright 2017 Silicon Laboratories, Inc. * @n http://www.silabs.com */ +//#define _1kHz + #if 0 #ifndef RADIO_CONFIG_H_ #define RADIO_CONFIG_H_ @@ -818,8 +820,6 @@ // ----------------------- 3kHz ----------------------------------------------- #endif -//--------------------------------------------------------------------------------------------- - /*! @file radio_config.h * @brief This file contains the automatically generated * configurations. @@ -832,8 +832,6 @@ * @n Copyright 2017 Silicon Laboratories, Inc. * @n http://www.silabs.com */ -#define RBW_850 1 -//#define RBW_11 #ifndef RADIO_CONFIG_H_ #define RADIO_CONFIG_H_ @@ -843,20 +841,20 @@ // INPUT DATA /* -// Crys_freq(Hz): 26000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15 -// MOD_type: 1 Rsymb(sps): 80000 Fdev(Hz): 800000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433 API_TC: 29 fhst: 10000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// Crys_freq(Hz): 26000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 2 Rsymb(sps): 433333 Fdev(Hz): 1 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.1 Chip-Version: 2 +// RF Freq.(MHz): 433.8 API_TC: 29 fhst: 1000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // // # RX IF frequency is -406250 Hz // # WB filter 1 (BW = 793.61 kHz); NB-filter 1 (BW = 793.61 kHz) // -// Modulation index: 20 +// Modulation index: 0 */ // CONFIGURATION PARAMETERS #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x5A +#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x64 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000 @@ -874,7 +872,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x11, 0x14, 0x07, 0x00, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x11, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -966,7 +964,7 @@ // MODEM_BCR_GEAR - RX BCR loop gear control. // MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. */ -#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0x44, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0 +#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0x44, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x00, 0xD0 /* // Set properties: RF_MODEM_AFC_GEAR_7 @@ -1130,11 +1128,7 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#ifdef RBW_850 -#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x0A -#else -#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x3F -#endif +#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x3D /* // Set properties: RF_SYNTH_PFDCP_CPFF_7 @@ -1169,7 +1163,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x03, 0x27, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x00, 0x51, 0x20, 0xFE /* // Command: RF_START_RX @@ -1198,7 +1192,7 @@ // Descriptions: // GLOBAL_CLK_CFG - Clock configuration options. */ -#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x40 +#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00 /* // Set properties: RF_GLOBAL_CONFIG_1_1 @@ -1234,7 +1228,7 @@ // FRR_CTL_C_MODE - Fast Response Register C Configuration. // FRR_CTL_D_MODE - Fast Response Register D Configuration. */ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x03, 0x01, 0x05, 0x07 +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x03, 0x01, 0x00, 0x00 /* // Set properties: RF_PREAMBLE_CONFIG_STD_1_1 @@ -1245,7 +1239,7 @@ // Descriptions: // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. */ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14 +#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 /* // Set properties: RF_PKT_CONFIG1_1 @@ -1278,11 +1272,8 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#ifdef RBW_850 -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x09, 0x00, 0x07, 0x0C, 0x35, 0x00, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 -#else -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x09, 0x00, 0x07, 0x00, 0x03, 0xE8, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 -#endif +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x42, 0x1F, 0x12, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 + /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 // Number of properties: 1 @@ -1310,10 +1301,10 @@ // MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. // MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. */ -#ifdef RBW_850 // #if 0 //#ifdef RBW_850 -#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x00, 0x80, 0x08, 0x03, 0x80, 0x00, 0x04, 0x30 +#ifdef _1kHz +#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0xF0, 0x11 #else -#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x00, 0x80, 0x08, 0x03, 0x80, 0x00, 0x3A, 0x11 +#define RF_MODEM_TX_RAMP_DELAY_8_1 0x11, 0x20, 0x08, 0x18, 0x01, 0x00, 0x08, 0x03, 0x80, 0x00, 0x00, 0x30 #endif /* // Set properties: RF_MODEM_BCR_OSR_1_9_1 @@ -1332,11 +1323,8 @@ // MODEM_BCR_GEAR - RX BCR loop gear control. // MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. */ -#ifdef RBW_850 -#define RF_MODEM_BCR_OSR_1_9_1 0x11, 0x20, 0x09, 0x22, 0x00, 0x51, 0x06, 0x4D, 0x32, 0x03, 0x29, 0x00, 0xC2 -#else -#define RF_MODEM_BCR_OSR_1_9_1 0x11, 0x20, 0x09, 0x22, 0x01, 0x53, 0x01, 0x83, 0x2B, 0x00, 0xC1, 0x00, 0xC2 -#endif +#define RF_MODEM_BCR_OSR_1_9_1 0x11, 0x20, 0x09, 0x22, 0x00, 0x3C, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x00, 0xD0 + /* // Set properties: RF_MODEM_AFC_GEAR_7_1 // Number of properties: 7 @@ -1352,11 +1340,8 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#ifdef RBW_850 -#define RF_MODEM_AFC_GEAR_7_1 0x11, 0x20, 0x07, 0x2C, 0x54, 0x36, 0x03, 0x27, 0x06, 0x0A, 0x80 -#else -#define RF_MODEM_AFC_GEAR_7_1 0x11, 0x20, 0x07, 0x2C, 0x54, 0x36, 0x00, 0x01, 0x31, 0x24, 0x80 -#endif +#define RF_MODEM_AFC_GEAR_7_1 0x11, 0x20, 0x07, 0x2C, 0x00, 0x23, 0x0F, 0xFF, 0x01, 0x97, 0xA0 + /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 // Number of properties: 1 @@ -1366,11 +1351,8 @@ // Descriptions: // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. */ -#ifdef RBW_850 -#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0x62 -#else -#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0x6A -#endif +#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2 + /* // Set properties: RF_MODEM_AGC_WINDOW_SIZE_9_1 // Number of properties: 9 @@ -1388,11 +1370,8 @@ // MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. // MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. */ -#ifdef RBW_850 -#define RF_MODEM_AGC_WINDOW_SIZE_9_1 0x11, 0x20, 0x09, 0x38, 0x11, 0x12, 0x12, 0x00, 0x02, 0xFF, 0xFF, 0x00, 0x28 -#else -#define RF_MODEM_AGC_WINDOW_SIZE_9_1 0x11, 0x20, 0x09, 0x38, 0x11, 0x4A, 0x4A, 0x00, 0x02, 0xFF, 0xFF, 0x00, 0x2A -#endif +#define RF_MODEM_AGC_WINDOW_SIZE_9_1 0x11, 0x20, 0x09, 0x38, 0x21, 0x09, 0x09, 0x00, 0x02, 0x00, 0x00, 0x00, 0x27 + /* // Set properties: RF_MODEM_OOK_CNT1_9 // Number of properties: 9 @@ -1410,11 +1389,8 @@ // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. // MODEM_RSSI_THRESH - Configures the RSSI threshold. */ -#ifdef RBW_850 -#define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0x84, 0x01, 0xD6, 0x8C, 0x07, 0xFF, 0x01, 0x80, 0xFF -#else -#define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0x84, 0x01, 0xD6, 0x8C, 0x00, 0x76, 0x01, 0x80, 0xFF -#endif +#define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0xA4, 0x03, 0xD6, 0x03, 0x00, 0x00, 0x01, 0x80, 0xFF + /* // Set properties: RF_MODEM_RSSI_CONTROL_1 // Number of properties: 1 @@ -1435,11 +1411,8 @@ // Descriptions: // MODEM_RSSI_COMP - RSSI compensation value. */ -#ifdef RBW_850 #define RF_MODEM_RSSI_COMP_1_1 0x11, 0x20, 0x01, 0x4E, 0x40 -#else -#define RF_MODEM_RSSI_COMP_1_1 0x11, 0x20, 0x01, 0x4E, 0x3A -#endif + /* // Set properties: RF_MODEM_CLKGEN_BAND_1_1 // Number of properties: 1 @@ -1471,10 +1444,10 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#ifdef RBW_850 -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01 +#ifdef _1kHz +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00 #else -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01 #endif /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -1496,10 +1469,10 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#ifdef RBW_850 -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9 +#ifdef _1kHz +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63 #else -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9 #endif /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -1521,10 +1494,10 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#ifdef RBW_850 -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F +#ifdef _1kHz +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F #else -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F #endif /* // Set properties: RF_PA_TC_1_1 @@ -1535,11 +1508,8 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#ifdef RBW_850 -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x4A -#else -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5F -#endif +#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5D + /* // Set properties: RF_SYNTH_PFDCP_CPFF_7_1 // Number of properties: 7 @@ -1555,7 +1525,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -1573,7 +1543,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0C, 0xEC, 0x4E, 0x03, 0x27, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xE8, 0x5E, 0x00, 0x51, 0x20, 0xFE // AUTOMATICALLY GENERATED CODE! diff --git a/nanovna.h b/nanovna.h index c73f06f..e20b8bd 100644 --- a/nanovna.h +++ b/nanovna.h @@ -28,6 +28,7 @@ //#define __SI4432__ //#define __PE4302__ #define __SI4463__ +#define __ADF4351__ //#define __SIMULATION__ //#define __PIPELINE__ #define __SCROLL__ diff --git a/sa_core.c b/sa_core.c index 7703f6e..51a8484 100644 --- a/sa_core.c +++ b/sa_core.c @@ -16,9 +16,9 @@ * Boston, MA 02110-1301, USA. */ -#ifdef __SI4432__ +//#ifdef __SI4432__ #include "SI4432.h" // comment out for simulation -#endif +//#endif #include "stdlib.h" #pragma GCC push_options @@ -184,10 +184,8 @@ uint32_t calc_min_sweep_time_us(void) // Estimate minimum sweep time in if (MODE_OUTPUT(setting.mode)) t = 200*sweep_points; // 200 microseconds is the delay set in perform when sweeping in output mode else { - uint32_t bare_sweep_time; -#ifdef __SI4432__ + uint32_t bare_sweep_time=0; bare_sweep_time = (SI4432_step_delay + MEASURE_TIME) * (sweep_points); // Single RSSI delay and measurement time in uS while scanning -#endif if (FREQ_IS_CW()) { bare_sweep_time = MINIMUM_SWEEP_TIME; // minimum sweep time in fast CW mode if (setting.repeat != 1 || setting.sweep_time_us >= 100*ONE_MS_TIME || setting.spur != 0) // if no fast CW sweep possible @@ -826,7 +824,6 @@ void set_fast_speedup(int s) void calculate_step_delay(void) { -#ifdef __SI4432__ if (setting.step_delay_mode == SD_MANUAL || setting.step_delay != 0) { // The latter part required for selftest 3 SI4432_step_delay = setting.step_delay; if (setting.offset_delay != 0) // Override if set @@ -836,6 +833,7 @@ void calculate_step_delay(void) if (setting.frequency_step == 0) { // zero span mode, not dependent on selected RBW SI4432_step_delay = 0; } else { +#ifdef __SI4432__ #if 1 // Table for double offset delay if (actual_rbw_x10 >= 1910) { SI4432_step_delay = 300; SI4432_offset_delay = 100; } else if (actual_rbw_x10 >= 1420) { SI4432_step_delay = 350; SI4432_offset_delay = 100; } @@ -856,6 +854,19 @@ void calculate_step_delay(void) else if (actual_rbw_x10 >= 90) { SI4432_step_delay = 1700; SI4432_offset_delay = 400; } else if (actual_rbw_x10 >= 50) { SI4432_step_delay = 3300; SI4432_offset_delay = 400; } else { SI4432_step_delay = 6400; SI4432_offset_delay =1600; } +#endif +#endif +#ifdef __SI4463__ + if (actual_rbw_x10 >= 1910) { SI4432_step_delay = 300; SI4432_offset_delay = 100; } + else if (actual_rbw_x10 >= 1420) { SI4432_step_delay = 350; SI4432_offset_delay = 100; } + else if (actual_rbw_x10 >= 750) { SI4432_step_delay = 450; SI4432_offset_delay = 100; } + else if (actual_rbw_x10 >= 560) { SI4432_step_delay = 650; SI4432_offset_delay = 100; } + else if (actual_rbw_x10 >= 370) { SI4432_step_delay = 700; SI4432_offset_delay = 200; } + else if (actual_rbw_x10 >= 180) { SI4432_step_delay = 1100; SI4432_offset_delay = 300; } + else if (actual_rbw_x10 >= 90) { SI4432_step_delay = 1700; SI4432_offset_delay = 400; } + else if (actual_rbw_x10 >= 50) { SI4432_step_delay = 3300; SI4432_offset_delay = 800; } + else if (actual_rbw_x10 >= 20) { SI4432_step_delay = 7000; SI4432_offset_delay = 800; } + else { SI4432_step_delay = 20000; SI4432_offset_delay =1600; } #endif if (setting.step_delay_mode == SD_PRECISE) // In precise mode wait twice as long for RSSI to stabalize SI4432_step_delay *= 2; @@ -865,7 +876,6 @@ void calculate_step_delay(void) if (setting.offset_delay != 0) // Override if set SI4432_offset_delay = setting.offset_delay; } -#endif } void apply_settings(void) // Ensure all settings in the setting structure are translated to the right HW setup @@ -980,6 +990,7 @@ void setupSA(void) PE4302_init(); PE4302_Write_Byte(0); #endif + ADF4351_Setup(); #if 0 // Measure fast scan time setting.sweep_time_us = 0; setting.additional_step_delay_us = 0; @@ -1004,8 +1015,8 @@ void set_freq(int V, unsigned long freq) // translate the requested frequency { if (old_freq[V] == freq) // Do not change HW if not needed return; - if (V <= 1) { #ifdef __SI4432__ + if (V <= 1) { SI4432_Sel = V; if (freq < 240000000 || freq > 960000000) { // Impossible frequency, simply ignore, should never happen. real_old_freq[V] = freq + 1; // No idea why this is done........ @@ -1065,7 +1076,10 @@ void set_freq(int V, unsigned long freq) // translate the requested frequency SI4432_Set_Frequency(freq); // Not in fast mode real_old_freq[V] = freq; } + } else #endif + if (V==2){ + ADF4351_set_frequency(V-2,freq,3); } #ifdef __ULTRA_SA__ else { @@ -1215,10 +1229,18 @@ void update_rbw(void) // calculate the actual_rbw and the vbwSteps (# } else actual_rbw_x10 = 2*setting.vbw_x10; // rbw is twice the frequency step to ensure no gaps in coverage } +#ifdef __SI4432__ if (actual_rbw_x10 < 26) actual_rbw_x10 = 26; if (actual_rbw_x10 > 6000) actual_rbw_x10 = 6000; +#endif +#ifdef __SI4463__ + if (actual_rbw_x10 < 11) + actual_rbw_x10 = 11; + if (actual_rbw_x10 > 8500) + actual_rbw_x10 = 8500; +#endif if (setting.spur && actual_rbw_x10 > 3000) actual_rbw_x10 = 2500; // if spur suppression reduce max rbw to fit within BPF @@ -1672,6 +1694,17 @@ pureRSSI_t perform(bool break_on_operation, int i, uint32_t f, int tracking) else set_freq (SI4432_LO, local_IF+lf); // otherwise to above IF #endif +#ifdef __ADF4351__ + if (setting.mode == M_LOW) { + if (!setting.tracking && S_STATE(setting.below_IF)) { // if in low input mode and below IF + if (lf > local_IF) + set_freq (ADF4351_LO, lf - local_IF); // set LO SI4432 to below IF frequency + else + set_freq (ADF4351_LO, local_IF-lf); // set LO SI4432 to below IF frequency + } else + set_freq (ADF4351_LO, local_IF+lf); // otherwise to above IF + } +#endif #endif } diff --git a/si4432.c b/si4432.c index eb32e96..3fbdc73 100644 --- a/si4432.c +++ b/si4432.c @@ -217,6 +217,10 @@ void set_10mhz(uint32_t f) setting_frequency_10mhz = f; } +int SI4432_step_delay = 1500; +int SI4432_offset_delay = 1500; +#define MINIMUM_WAIT_FOR_RSSI 280 + #ifdef __SI4432__ #define CS_SI0_HIGH palSetPad(GPIOC, GPIO_RX_SEL) #define CS_SI1_HIGH palSetPad(GPIOC, GPIO_LO_SEL) @@ -491,7 +495,6 @@ void SI4432_Set_Frequency ( uint32_t Freq ) { // SI4432_Write_Byte( 0x07, 0x0B); } -int SI4432_step_delay = 1500; //extern int setting.repeat; #ifdef __FAST_SWEEP__ @@ -545,8 +548,6 @@ void SI4432_Fill(int s, int start) } #endif -#define MINIMUM_WAIT_FOR_RSSI 280 -int SI4432_offset_delay = 300; pureRSSI_t getSI4432_RSSI_correction(void){ return SI4432_RSSI_correction; @@ -863,51 +864,25 @@ float Simulated_SI4432_RSSI(uint32_t i, int s) #endif //------------------------------- ADF4351 ------------------------------------- -#ifdef __ULTRA_SA__ +#ifdef __ADF4351__ #define bitRead(value, bit) (((value) >> (bit)) & 0x01) #define bitSet(value, bit) ((value) |= (1UL << (bit))) #define bitClear(value, bit) ((value) &= ~(1UL << (bit))) #define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) -#define CS_ADF0_HIGH palSetPad(GPIOA, 9) -#define CS_ADF1_HIGH palSetPad(GPIOA, 10) - -#define CS_ADF0_LOW palClearPad(GPIOA, 9) -#define CS_ADF1_LOW palClearPad(GPIOA, 10) - -#define SPI3_CLK_HIGH palSetPad(GPIOA, 1) -#define SPI3_CLK_LOW palClearPad(GPIOA, 1) - -#define SPI3_SDI_HIGH palSetPad(GPIOA, 2) -#define SPI3_SDI_LOW palClearPad(GPIOA, 2) - +#define CS_ADF0_HIGH palSetPad(GPIOB, 10) +#define CS_ADF1_HIGH palSetPad(GPIOB, 10) -void ADF_shiftOut(uint8_t val) -{ - uint8_t i; - for (i = 0; i < 8; i++) { - if (val & (1 << (7 - i))) - SPI3_SDI_HIGH; - else - SPI3_SDI_LOW; -// chThdSleepMicroseconds(10); - SPI3_CLK_HIGH; -// chThdSleepMicroseconds(10); - SPI3_CLK_LOW; -// chThdSleepMicroseconds(10); - } -} - -//unsigned long registers[6] = {0x4580A8, 0x80080C9, 0x4E42, 0x4B3, 0xBC803C, 0x580005} ; -//unsigned long registers[6] = {0x4C82C8, 0x80083E9, 0x6E42, 0x8004B3, 0x8C81FC, 0x580005} ; +#define CS_ADF0_LOW palClearPad(GPIOB, 10) +#define CS_ADF1_LOW palClearPad(GPIOB, 10) //uint32_t registers[6] = {0x320000, 0x8008011, 0x4E42, 0x4B3,0x8C803C , 0x580005} ; //25 MHz ref uint32_t registers[6] = {0xA00000, 0x8000011, 0x4E42, 0x4B3,0xDC003C , 0x580005} ; //10 MHz ref int debug = 0; -int ADF4351_LE[2] = { 9, 10}; +int ADF4351_LE[2] = { 10, 10}; int ADF4351_Mux = 7; @@ -928,7 +903,7 @@ double RFout, //Output freq in MHz Chrystal[6] = {10.0,10.0,10.0,10.0,10.0,10.0}, #endif - OutputChannelSpacing = 0.010, // = 0.01 + OutputChannelSpacing = 0.001, // = 0.01 FRACF; // Temp unsigned int long RFint, // Output freq/10Hz @@ -942,22 +917,23 @@ uint8_t lock=2; //Not used // Lock = A4 -void ADF4351_Setup() +void ADF4351_Setup(void) { // palSetPadMode(GPIOA, 1, PAL_MODE_OUTPUT_PUSHPULL ); // palSetPadMode(GPIOA, 2, PAL_MODE_OUTPUT_PUSHPULL ); - SPI3_CLK_HIGH; - SPI3_SDI_HIGH; +// SPI3_CLK_HIGH; +// SPI3_SDI_HIGH; CS_ADF0_HIGH; - CS_ADF1_HIGH; -// bitSet (registers[2], 17); // R set to 8 +// CS_ADF1_HIGH; + + // bitSet (registers[2], 17); // R set to 8 // bitClear (registers[2], 14); // R set to 8 // while(1) { // - ADF4351_set_frequency(0,100000000,0); - ADF4351_set_frequency(1,150000000,0); + ADF4351_set_frequency(0,2000000000,0); +// ADF4351_set_frequency(1,150000000,0); // ADF4351_Set(0); // ADF4351_Set(1); // chThdSleepMilliseconds(1000); @@ -975,38 +951,43 @@ void ADF4351_Setup() void ADF4351_WriteRegister32(int channel, const uint32_t value) { - palClearPad(GPIOA, ADF4351_LE[channel]); + // set_SPI_mode(SPI_MODE_SI); + // chThdSleepMicroseconds(10); + palClearPad(GPIOB, ADF4351_LE[channel]); // chThdSleepMicroseconds(10); - for (int i = 3; i >= 0; i--) ADF_shiftOut((value >> (8 * i)) & 0xFF); + for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF); // chThdSleepMicroseconds(10); - palSetPad(GPIOA, ADF4351_LE[channel]); + palSetPad(GPIOB, ADF4351_LE[channel]); // chThdSleepMicroseconds(10); - palClearPad(GPIOA, ADF4351_LE[channel]); + palClearPad(GPIOB, ADF4351_LE[channel]); // chThdSleepMicroseconds(10); } -void ADF4351_disable_output() +void ADF4351_Set(int channel) +{ for (int i = 5; i >= 0; i--) { + ADF4351_WriteRegister32(channel, registers[i]); +// if (debug) Serial.println(registers[i],HEX); +} +} + +void ADF4351_disable_output(void) { bitClear (registers[4], 5); // digital lock ADF4351_Set(0); } -void ADF4351_enable_output() +void ADF4351_enable_output(void) { bitSet (registers[4], 5); // digital lock ADF4351_Set(0); } -void ADF4351_Set(int channel) -{ for (int i = 5; i >= 0; i--) { - ADF4351_WriteRegister32(channel, registers[i]); -// if (debug) Serial.println(registers[i],HEX); -} -} void ADF4351_set_frequency(int channel, unsigned long freq, int drive) // freq / 10Hz { ADF4351_prep_frequency(channel,freq, drive); ADF4351_Set(channel); + if (SI4432_step_delay>10) + my_microsecond_delay(SI4432_step_delay); } void ADF4351_spur_mode(int S) @@ -1220,7 +1201,6 @@ void ADF4351_prep_frequency(int channel, unsigned long freq, int drive) // freq } - #endif // ------------------------------ SI4463 ------------------------------------- @@ -1490,9 +1470,14 @@ int16_t Si446x_RSSI(void) 0xFF }; // volatile si446x_state_t s = getState(); - + chThdSleepMicroseconds(SI4432_step_delay); +again: SI4463_do_api(data, 2, data, 3); + if (data[2] == 255) + goto again; int16_t rssi = data[2] - 120 * 2; + if (rssi > 0) + rssi = -150*2; return DEVICE_TO_PURE_RSSI(rssi); } diff --git a/si4432.h b/si4432.h index da7d774..2b65aac 100644 --- a/si4432.h +++ b/si4432.h @@ -22,6 +22,13 @@ #define __SI4432_H__ +void start_SI4432_SPI_mode(void); +void stop_SI4432_SPI_mode(void); + +extern int SI4432_step_delay; +extern int SI4432_offset_delay; + + #ifdef __SI4432__ // @@ -109,11 +116,6 @@ extern volatile int SI4432_Sel; // currently selected SI4432 -void start_SI4432_SPI_mode(void); -void stop_SI4432_SPI_mode(void); - -extern int SI4432_step_delay; -extern int SI4432_offset_delay; extern int SI4432_frequency_changed; extern int SI4432_offset_changed; @@ -148,7 +150,7 @@ int SI4432_is_fast_mode(void); bool PE4302_Write_Byte(unsigned char DATA ); void PE4302_init(void); -#ifdef __ULTRA_SA__ +#ifdef __ADF4351__ extern int ADF4351_LE[]; extern int debug; void ADF4351_Setup(void); @@ -179,6 +181,7 @@ void setState(si446x_state_t newState); extern si446x_info_t SI4463_info; void Si446x_getInfo(si446x_info_t* info); void SI4463_init(void); +#define ADF4351_LO 2 #endif diff --git a/ui_sa.c b/ui_sa.c index d44b13d..0d8156b 100644 --- a/ui_sa.c +++ b/ui_sa.c @@ -989,7 +989,7 @@ static UI_FUNCTION_CALLBACK(menu_marker_delete_cb) } } -static const uint16_t rbwsel_x10[]={0,30,100,300,1000,3000,6000}; +static const uint16_t rbwsel_x10[]={0,10,30,100,300,1000,3000}; static UI_FUNCTION_ADV_CALLBACK(menu_rbw_acb) { (void)item;