From b47a95b1bd553f638b66a67c16a613090ae6400b Mon Sep 17 00:00:00 2001 From: erikkaashoek Date: Thu, 31 Dec 2020 14:48:20 +0100 Subject: [PATCH] First tuning --- NANOVNA_STM32_F303/board.h | 2 +- main.c | 4 +-- nanovna.h | 10 +++--- radio_config_Si4468_850kHz.h | 58 +++++++++++++++--------------- radio_config_Si4468_default.h | 66 +++++++++++++++++------------------ sa_core.c | 20 ++++++++--- si4432.c | 36 +++++++++++-------- 7 files changed, 106 insertions(+), 90 deletions(-) diff --git a/NANOVNA_STM32_F303/board.h b/NANOVNA_STM32_F303/board.h index f16289e..a23812f 100644 --- a/NANOVNA_STM32_F303/board.h +++ b/NANOVNA_STM32_F303/board.h @@ -55,7 +55,7 @@ /* on-board */ -#if 0 // Set to 1 to build for prototype HW +#if 1 // Set to 1 to build for prototype HW #define TINYSA4_PROTO #define GPIO_LED 0 #define LINE_LED PAL_LINE(GPIOA,GPIO_LED) diff --git a/main.c b/main.c index 20f9a77..9fdee20 100644 --- a/main.c +++ b/main.c @@ -901,7 +901,7 @@ config_t config = { .cor_am = -14, .cor_wfm = -17, .cor_nfm = -17, - .ultra = true, + .ultra = false, }; //properties_t current_props; @@ -2436,7 +2436,7 @@ static const VNAShellCommand commands[] = { "g", cmd_g, CMD_WAIT_MUTEX }, #endif #ifdef __ADF4351__ - { "x", cmd_x, 0 }, + { "x", cmd_x, CMD_WAIT_MUTEX }, #endif {NULL , NULL , 0} }; diff --git a/nanovna.h b/nanovna.h index a02076c..f6a08be 100644 --- a/nanovna.h +++ b/nanovna.h @@ -17,7 +17,7 @@ * Boston, MA 02110-1301, USA. */ #include "ch.h" -//#define TINYSA4_PROTO +#define TINYSA4_PROTO //#ifdef TINYSA_F303 #include "adc_F303.h" @@ -63,11 +63,11 @@ #define HIGH_MAX_FREQ_MHZ 960 #endif #ifdef TINYSA4 -#define DEFAULT_IF ((uint32_t)978000000) -#define DEFAULT_SPUR_IF ((uint32_t)979000000) +#define DEFAULT_IF ((uint32_t)977000000) +#define DEFAULT_SPUR_IF ((uint32_t)978000000) #define DEFAULT_MAX_FREQ ((uint32_t)800000000) -#define HIGH_MIN_FREQ_MHZ 850 -#define HIGH_MAX_FREQ_MHZ 1150 +#define HIGH_MIN_FREQ_MHZ 825 +#define HIGH_MAX_FREQ_MHZ 1130 #endif /* * main.c diff --git a/radio_config_Si4468_850kHz.h b/radio_config_Si4468_850kHz.h index f8a4f6b..850524d 100644 --- a/radio_config_Si4468_850kHz.h +++ b/radio_config_Si4468_850kHz.h @@ -19,20 +19,20 @@ // INPUT DATA /* -// Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 425000 Fdev(Hz): 212500 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 2 Rsymb(sps): 400000 Fdev(Hz): 200000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 900 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0 // -// # RX IF frequency is -406250 Hz -// # WB filter 1 (BW = 793.61 kHz); NB-filter 1 (BW = 793.61 kHz) +// # RX IF frequency is -468750 Hz +// # WB filter 1 (BW = 915.70 kHz); NB-filter 1 (BW = 915.70 kHz) // // Modulation index: 1 */ // CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 @@ -45,13 +45,13 @@ // Command: RF_POWER_UP // Description: Command to power-up the device and select the operational mode and functionality. */ -#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80 +#define RF_POWER_UP 0x02, 0x01, 0x01, 0x01, 0xC9, 0xC3, 0x80 /* // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x02, 0x02, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -106,7 +106,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00 /* // Set properties: RF_MODEM_FREQ_DEV_0_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x23 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -174,7 +174,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x66, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1 @@ -207,7 +207,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0F, 0x0F, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_5 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x99, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -308,7 +308,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 @@ -330,7 +330,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 @@ -352,7 +352,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00 /* // Set properties: RF_PA_TC_1 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x40, 0xD9, 0x90, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x21 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x3D, 0x09, 0x00, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x1B /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x7A +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x4F /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x3D +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x4B /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x5E, 0x86, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x08, 0x5F +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0D, 0xA7 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x9A, 0x00 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xEA, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x21, 0x09, 0x09, 0x80, 0x02, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x08, 0x08, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x02, 0x0A, 0x01, 0x00, 0xFF, 0x08, 0x10, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0xFF, 0x08, 0x00, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x07, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0F, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x3B, 0x08, 0x00, 0x00, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_default.h b/radio_config_Si4468_default.h index d18cde7..4414474 100644 --- a/radio_config_Si4468_default.h +++ b/radio_config_Si4468_default.h @@ -19,20 +19,20 @@ // INPUT DATA /* -// Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 433333 Fdev(Hz): 1 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 +// MOD_type: 2 Rsymb(sps): 400000 Fdev(Hz): 200000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 900 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 0 // -// # RX IF frequency is -406250 Hz -// # WB filter 1 (BW = 793.61 kHz); NB-filter 1 (BW = 793.61 kHz) +// # RX IF frequency is -468750 Hz +// # WB filter 1 (BW = 915.70 kHz); NB-filter 1 (BW = 915.70 kHz) // -// Modulation index: 0 +// Modulation index: 1 */ // CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L +#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 @@ -45,13 +45,13 @@ // Command: RF_POWER_UP // Description: Command to power-up the device and select the operational mode and functionality. */ -#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80 +#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80 /* // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x02, 0x02, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -106,7 +106,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00 /* // Set properties: RF_MODEM_FREQ_DEV_0_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x23 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -174,7 +174,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x66, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1 @@ -207,7 +207,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0F, 0x0F, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_5 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x99, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -308,7 +308,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 @@ -330,7 +330,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 @@ -352,7 +352,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00 /* // Set properties: RF_PA_TC_1 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -427,7 +427,7 @@ // Descriptions: // GLOBAL_CLK_CFG - Clock configuration options. */ -#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00 +#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x40 /* // Set properties: RF_GLOBAL_CONFIG_1_1 @@ -463,7 +463,7 @@ // FRR_CTL_C_MODE - Fast Response Register C Configuration. // FRR_CTL_D_MODE - Fast Response Register D Configuration. */ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x05, 0x01, 0x07, 0x09 +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_PREAMBLE_CONFIG_STD_1_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x42, 0x1F, 0x12, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x3D, 0x09, 0x00, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x1B /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x00 +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x4F /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xE8, 0x00, 0x4B /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x08, 0x89 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0D, 0xA7 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x92, 0x00 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xEA, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x21, 0x09, 0x09, 0x80, 0x02, 0x00, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x08, 0x08, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x08, 0x10, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0xFF, 0x08, 0x00, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x01, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x3B, 0x08, 0x00, 0x00, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/sa_core.c b/sa_core.c index dcdace1..3330f2b 100644 --- a/sa_core.c +++ b/sa_core.c @@ -73,7 +73,8 @@ void update_min_max_freq(void) maxFreq = HIGH_MAX_FREQ_MHZ * 1000000; break; case M_GENHIGH: -#if 0 +//#define __HIGH_OUT_ADF4351__ +#ifdef __HIGH_OUT_ADF4351__ minFreq = 135000000; maxFreq = 4290000000U; #else @@ -1525,8 +1526,10 @@ case M_GENHIGH: // Direct output from 1 } SI4432_Transmit(setting.lo_drive); #endif + +#ifdef __HIGH_OUT_ADF4351__ #ifdef __SI4468__ - SI4463_init_tx(); + SI4463_init_rx(); #endif ADF4351_enable(true); #ifndef TINYSA4_PROTO @@ -1537,7 +1540,14 @@ case M_GENHIGH: // Direct output from 1 ADF4351_enable_out(true); // Must be enabled to have aux output #endif ADF4351_aux_drive(setting.lo_drive); - enable_rx_output(false); +#else + ADF4351_enable_aux_out(false); + ADF4351_enable_out(false); +#ifdef __SI4468__ + SI4463_init_tx(); +#endif +#endif + enable_rx_output(true); enable_high(true); enable_extra_lna(false); enable_ultra(false); @@ -1833,7 +1843,7 @@ static void calculate_static_correction(void) // Calculate the - (S_STATE(setting.agc)? 0 : +12) - (S_STATE(setting.lna)? 0 : +21) + get_attenuation() - + (setting.extra_lna ? -20.0 : 0) // TODO <------------------------- set correct value + + (setting.extra_lna ? -23.0 : 0) // TODO <------------------------- set correct value - setting.offset); } @@ -2173,7 +2183,7 @@ modulation_again: } else if (setting.mode == M_HIGH) { set_freq (SI4463_RX, lf); // sweep RX, local_IF = 0 in high mode } else if (setting.mode == M_GENHIGH) { -#if 0 // Let SI TX only +#ifndef __HIGH_OUT_ADF4351__ // Let SI TX only set_freq (SI4463_RX, lf); // sweep RX, local_IF = 0 in high mode local_IF = 0; #else diff --git a/si4432.c b/si4432.c index 29dc20e..afeca98 100644 --- a/si4432.c +++ b/si4432.c @@ -1039,7 +1039,8 @@ void ADF4351_Setup(void) ADF4351_set_frequency(0,200000000); - ADF4351_mux(6); // Show lock on led + ADF4351_mux(2); // No led + // ADF4351_mux(6); // Show lock on led // ADF4351_set_frequency(1,150000000,0); // ADF4351_Set(0); @@ -1059,6 +1060,7 @@ void ADF4351_Setup(void) void ADF4351_WriteRegister32(int channel, const uint32_t value) { + registers[value & 0x07] = value; for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF); palSetLine(ADF4351_LE[channel]); my_microsecond_delay(1); // Must @@ -1265,7 +1267,7 @@ uint64_t ADF4351_prep_frequency(int channel, uint64_t freq) // freq / 10Hz my_microsecond_delay(10); } max_delta = freq - actual_freq; - if (max_delta > 50000 || max_delta < -50000 || freq == 0) { + if (max_delta > 100000 || max_delta < -100000 || freq == 0) { while(1) my_microsecond_delay(10); } @@ -1543,6 +1545,10 @@ void SI4463_refresh_gpio(void) void SI4463_set_gpio(int i, int s) { gpio_state[i] = s; +#if 0 // debug gpio + gpio_state[2] = 3; + gpio_state[3] = 2; +#endif SI4463_refresh_gpio(); } @@ -1916,8 +1922,8 @@ int16_t Si446x_RSSI(void) ADF4351_frequency_changed = false; SI4463_offset_changed = false; } - - int j = 1; //setting.repeat; +#define SAMPLE_COUNT 3 + int j = SAMPLE_COUNT; //setting.repeat; int RSSI_RAW_ARRAY[3]; do{ again: @@ -1932,7 +1938,7 @@ int16_t Si446x_RSSI(void) if (j == 0) break; my_microsecond_delay(20); }while(1); -#if 0 +#if SAMPLE_COUNT == 3 int t; if (RSSI_RAW_ARRAY[0] > RSSI_RAW_ARRAY[1]) { t = RSSI_RAW_ARRAY[1]; @@ -2342,11 +2348,11 @@ void SI4463_set_freq(uint32_t freq) } if (SI4463_band == -1) return; -#ifdef TINYSA4_PROTO +//#ifdef TINYSA4_PROTO #define freq_xco 30000000 -#else -#define freq_xco 26000000 -#endif +//#else +//#define freq_xco 26000000 +//#endif if (SI4463_offset_active) { si_set_offset(0); SI4463_offset_active = false; @@ -2364,7 +2370,7 @@ void SI4463_set_freq(uint32_t freq) while(1) my_microsecond_delay(10); } - if ((SI4463_band == prev_band)) { + if (false && (SI4463_band == prev_band)) { int vco = 2091 + ((((freq / 4 ) * SI4463_outdiv - 850000000)/1000) * 492) / 200000; if (SI4463_in_tx_mode) { @@ -2444,7 +2450,7 @@ void SI4463_set_freq(uint32_t freq) // #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A uint8_t data2[] = { 0x11, 0x20, 0x01, 0x51, - 0x10 + (uint8_t)(SI4463_band + (Npresc ? 0x08 : 0)) // 0x08 for high performance mode, 0x10 to skip recal + /* 0x10 + */ (uint8_t)(SI4463_band + (Npresc ? 0x08 : 0)) // 0x08 for high performance mode, 0x10 to skip recal }; SI4463_do_api(data2, sizeof(data2), NULL, 0); // my_microsecond_delay(30000); @@ -2459,21 +2465,21 @@ void SI4463_set_freq(uint32_t freq) SI4463_start_tx(0); else { SI4463_start_rx(SI4463_channel); -#if 1 +#if 0 si446x_state_t s = SI4463_get_state(); if (s != SI446X_STATE_RX) { SI4463_start_rx(SI4463_channel); - osalThreadSleepMilliseconds(1000); + my_microsecond_delay(1000); #if 1 si446x_state_t s = SI4463_get_state(); if (s != SI446X_STATE_RX) { - osalThreadSleepMilliseconds(3000); + my_microsecond_delay(3000); goto retry; } #endif } - } #endif + } SI4463_wait_for_cts(); // SI4463_set_gpio(3,GPIO_LOW); SI4463_frequency_changed = true;