From ab6f1b2be41421901943ab0a9386e17de8d9aa14 Mon Sep 17 00:00:00 2001 From: erikkaashoek Date: Fri, 18 Mar 2022 11:54:24 +0100 Subject: [PATCH] Squashed commit of the following: commit ce0121fc6ad45c8a6b7be9dae1d77341ce26a720 Author: erikkaashoek Date: Fri Mar 18 11:53:23 2022 +0100 Updated filters and RBW calculation --- main.c | 4 +-- nanovna.h | 4 +-- plot.c | 10 +++++- radio_config_Si4468_100kHz.h | 54 ++++++++++++++++---------------- radio_config_Si4468_10kHz.h | 50 +++++++++++++++--------------- radio_config_Si4468_30kHz.h | 54 ++++++++++++++++---------------- radio_config_Si4468_850kHz.h | 6 ++-- radio_config_Si4468_default.h | 10 +++--- sa_core.c | 58 ++++++++++++++++++----------------- si4468.c | 8 ++--- ui_sa.c | 8 +++-- 11 files changed, 139 insertions(+), 127 deletions(-) diff --git a/main.c b/main.c index c58058e..099110d 100644 --- a/main.c +++ b/main.c @@ -921,8 +921,8 @@ config_t config = { }, .correction_value = { - { 10.5, +2.3, +1.9, -0.2, -0.2, 0, -0.7, +1.8, +1.8, +9.7, +3.8, +4.4, +4.3, +8.3, +8.3, +9, +9, +9, +11, +11,}, // low in - { 10.5, +2.3, +1.9, -0.2, -0.2, 0, -0.7, +1.8, +1.8, +9.7, +3.8, +4.4, +4.3, +8.3, +8.3, +9, +9, +9, +11, +11,}, // low in + { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // low in + { 10.5, +3, +1 , -0.1, 0, 0, -1.1, +1.5, +1.8, +9.7, +3.8, +3.5, +4, +8, +10.5, +13, +17.5, +20, +24, +28,}, // lna in { 11.5, 7, 6, 3.5, 1.5, 0.5, -0.2, 0, 0, -0.5, +1.5, +2, +4, +6.5, +9, +13, +13, +13, +13, +13, }, // low out }, .setting_frequency_30mhz = 30000000ULL * FREQ_MULTIPLIER, diff --git a/nanovna.h b/nanovna.h index 0472ba1..713da9d 100644 --- a/nanovna.h +++ b/nanovna.h @@ -18,7 +18,7 @@ */ #include "ch.h" -#ifdef TINYSA_F303 +//#ifdef TINYSA_F303 #ifdef TINYSA_F072 #error "Remove comment for #ifdef TINYSA_F303" #endif @@ -26,7 +26,7 @@ #define TINYSA4 #endif #define TINYSA4_PROTO -#endif +//#endif #ifdef TINYSA_F072 #ifdef TINYSA_F303 diff --git a/plot.c b/plot.c index 162a409..c7a6700 100644 --- a/plot.c +++ b/plot.c @@ -1520,7 +1520,15 @@ static void trace_print_value_string( // Only used at one place if (FREQ_IS_CW()) { plot_printf(ptr2, sizeof(buf2) - 9, "%.3Fs", idx*setting.actual_sweep_time_us/(float)((sweep_points - 1)*ONE_SECOND_TIME)); } else { - plot_printf(ptr2, sizeof(buf2) - 9, "%9.5QHz", freq); + freq_t step = getFrequency(1)-getFrequency(0); + int digits = 1; + if (freq>1000000 && step != 0) { + while (step < 1000000 && digits<5) { + digits++; + step = step*10; + } + } + plot_printf(ptr2, sizeof(buf2) - 9, "%9.*QHz", digits, freq); } const char *format; if (UNIT_IS_LINEAR(setting.unit)) diff --git a/radio_config_Si4468_100kHz.h b/radio_config_Si4468_100kHz.h index 4caac81..348d1c7 100644 --- a/radio_config_Si4468_100kHz.h +++ b/radio_config_Si4468_100kHz.h @@ -19,15 +19,15 @@ // INPUT DATA /* -// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 50000 Fdev(Hz): 25000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15 +// MOD_type: 2 Rsymb(sps): 180000 Fdev(Hz): 300000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz -// # WB filter 2 (BW = 103.06 kHz); NB-filter 2 (BW = 103.06 kHz) +// # WB filter 15 (BW = 103.75 kHz); NB-filter 15 (BW = 103.75 kHz) // -// Modulation index: 1 +// Modulation index: 3.333 */ @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x11, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF /* // Command: RF_START_RX @@ -474,7 +474,7 @@ // Descriptions: // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. */ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 +#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14 /* // Set properties: RF_PKT_CONFIG1_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x07, 0xA1, 0x20, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x03 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x1B, 0x77, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x6A +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xB5, 0x00, 0x4B +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x00, 0x20, 0x00, 0xB5, 0x00, 0x53 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0xDA +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x03, 0x16, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0xAA /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCC, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x03, 0x0C, 0x80 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x10, 0x10, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x02, 0xD5, 0x55, 0x00, 0x28, 0x0C, 0x84, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0x00, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x04, 0xFE, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x90, 0xA7 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x62, 0x44, 0x25, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_PA_TC_1_1 @@ -755,7 +755,7 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x3D +#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5D /* // Set properties: RF_SYNTH_PFDCP_CPFF_7_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_10kHz.h b/radio_config_Si4468_10kHz.h index 9b07055..2803d47 100644 --- a/radio_config_Si4468_10kHz.h +++ b/radio_config_Si4468_10kHz.h @@ -19,15 +19,15 @@ // INPUT DATA /* -// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 5000 Fdev(Hz): 2500 RXBW(Hz): 10000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15 +// MOD_type: 2 Rsymb(sps): 19000 Fdev(Hz): 100000 RXBW(Hz): 10000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz -// # WB filter 4 (BW = 10.33 kHz); NB-filter 4 (BW = 10.33 kHz) +// # WB filter 13 (BW = 10.65 kHz); NB-filter 13 (BW = 10.65 kHz) // -// Modulation index: 1 +// Modulation index: 10.526 */ @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF /* // Command: RF_START_RX @@ -474,7 +474,7 @@ // Descriptions: // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. */ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 +#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14 /* // Set properties: RF_PKT_CONFIG1_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0xC3, 0x50, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x02, 0xE6, 0x30, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x0D /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x57 +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x20, 0x0C, 0xB5, 0x00, 0x5E +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x30, 0x50, 0x00, 0xB5, 0x00, 0x42 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x76, 0x1A, 0x05, 0x72, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x16 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xC8, 0x4B, 0x03, 0xE1, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0x0E /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0xCE, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x53, 0x80 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x15, 0x15, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0E, 0x0E, 0x80, 0x02, 0xFF, 0xFF, 0x00, 0x28, 0x0C, 0x84, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x55, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x07, 0xFF, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0xC2, 0xA7 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x44, 0x7F, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F /* // Set properties: RF_PA_TC_1_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_30kHz.h b/radio_config_Si4468_30kHz.h index 5c83c8b..0236df1 100644 --- a/radio_config_Si4468_30kHz.h +++ b/radio_config_Si4468_30kHz.h @@ -19,15 +19,15 @@ // INPUT DATA /* -// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 30000 Fdev(Hz): 7500 RXBW(Hz): 30000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 1 +// Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 15 +// MOD_type: 2 Rsymb(sps): 58000 Fdev(Hz): 100000 RXBW(Hz): 30000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 0 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz -// # WB filter 9 (BW = 32.77 kHz); NB-filter 9 (BW = 32.77 kHz) +// # WB filter 13 (BW = 31.96 kHz); NB-filter 13 (BW = 31.96 kHz) // -// Modulation index: 0.5 +// Modulation index: 3.448 */ @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -207,7 +207,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x00, 0x00, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_5 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF /* // Command: RF_START_RX @@ -474,7 +474,7 @@ // Descriptions: // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. */ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 +#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x14 /* // Set properties: RF_PKT_CONFIG1_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x04, 0x93, 0xE0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x01 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x08, 0xD9, 0xA0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x0D /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x06 +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xA7 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x10, 0x00, 0xB5, 0x00, 0x53 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xB5, 0x00, 0x41 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x83 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xEB, 0x3F, 0x03, 0xF0, 0x00, 0xC3, 0x00, 0x54, 0x23, 0x80, 0x2B /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xF5, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x04, 0x36, 0x80 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x12, 0x12, 0x80, 0x02, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0E, 0x0E, 0x80, 0x02, 0xDC, 0xB1, 0x00, 0x28, 0x0C, 0x84, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xC0, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x06, 0xA8, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x1A, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x96, 0xA7 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x06, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x44, 0x32, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0xC6, 0xC1, 0xB2, 0x9C, 0x80, 0x63 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x47, 0x2F, 0x1B, 0x0E, 0x05, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x0F /* // Set properties: RF_PA_TC_1_1 @@ -755,7 +755,7 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x1D +#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x3D /* // Set properties: RF_SYNTH_PFDCP_CPFF_7_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_850kHz.h b/radio_config_Si4468_850kHz.h index dbfb510..8260608 100644 --- a/radio_config_Si4468_850kHz.h +++ b/radio_config_Si4468_850kHz.h @@ -236,7 +236,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x18, 0x10, 0x40 +#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2 @@ -463,7 +463,7 @@ // FRR_CTL_C_MODE - Fast Response Register C Configuration. // FRR_CTL_D_MODE - Fast Response Register D Configuration. */ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x0A, 0x00, 0x00, 0x00 +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_PREAMBLE_CONFIG_STD_1_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x02, 0x7F, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x1A, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x02, 0x7F, 0x01, 0x00, 0xFF, 0x08, 0x08, 0x1A, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 diff --git a/radio_config_Si4468_default.h b/radio_config_Si4468_default.h index d940661..8da30db 100644 --- a/radio_config_Si4468_default.h +++ b/radio_config_Si4468_default.h @@ -185,7 +185,7 @@ // Descriptions: // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. */ -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0 +#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0 // 0xE0 /* // Set properties: RF_MODEM_AGC_WINDOW_SIZE_12 @@ -463,7 +463,7 @@ // FRR_CTL_C_MODE - Fast Response Register C Configuration. // FRR_CTL_D_MODE - Fast Response Register D Configuration. */ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x0A, 0x00, 0x00, 0x00 +#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_PREAMBLE_CONFIG_STD_1_1 @@ -586,7 +586,7 @@ // Descriptions: // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. */ -#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE2 +#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0x00 // 0xE2 /* // Set properties: RF_MODEM_AGC_WINDOW_SIZE_12_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x02, 0x4C, 0xCD, 0x00, 0x27, 0x0C, 0x84, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x00, 0x00, 0x80, 0x02, 0x4C, 0xCD, 0x00, 0x27, 0x0C, 0x84, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x02, 0x7F, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x1A, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x8F, 0x02, 0x7F, 0x01, 0x00, 0xFF, 0x08, 0x08, 0x1A, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 diff --git a/sa_core.c b/sa_core.c index 96ccf80..1e23944 100644 --- a/sa_core.c +++ b/sa_core.c @@ -2235,7 +2235,7 @@ void update_rbw(void) // calculate the actual_rbw and the vbwSteps (# #endif } frequency_step_x10 = 3000; // default value for zero span - if (setting.frequency_step > 0 && MODE_INPUT(setting.mode)) { + if (setting.frequency_step > 0) { frequency_step_x10 = (setting.frequency_step)/100; } @@ -2243,17 +2243,11 @@ void update_rbw(void) // calculate the actual_rbw and the vbwSteps (# if (temp_actual_rbw_x10 == 0) { // if auto rbw if (setting.step_delay_mode==SD_FAST) { // if in fast scanning -#ifdef __SI4432__ - if (setting.fast_speedup > 2) - temp_actual_rbw_x10 = 6*frequency_step_x10; // rbw is six times the frequency step to ensure no gaps in coverage as there are some weird jumps - else - temp_actual_rbw_x10 = 4*frequency_step_x10; // rbw is four times the frequency step to ensure no gaps in coverage as there are some weird jumps -#endif -#ifdef __SI4463__ temp_actual_rbw_x10 = frequency_step_x10; -#endif + } else if (setting.step_delay_mode==SD_PRECISE) { + temp_actual_rbw_x10 = 4*frequency_step_x10; } else { - temp_actual_rbw_x10 = 2*frequency_step_x10; // rbw is twice the frequency step to ensure no gaps in coverage + temp_actual_rbw_x10 = 2*frequency_step_x10; } } #ifdef __SI4432__ @@ -2276,26 +2270,31 @@ void update_rbw(void) // calculate the actual_rbw and the vbwSteps (# SI4432_Sel = MODE_SELECT(setting.mode); #endif #ifdef __SI4463__ -// if (setting.spur_removal && actual_rbw_x10 > 3000) // Will depend on BPF width <------------------ TODO ------------------------- -// actual_rbw_x10 = 3000; // if spur suppression reduce max rbw to fit within BPF + // Not needed #endif - actual_rbw_x10 = set_rbw(actual_rbw_x10); // see what rbw the SI4432 can realize - if (setting.frequency_step > 0 && MODE_INPUT(setting.mode)) { // When doing frequency scanning in input mode -#ifdef TINYSA4 - if (frequency_step_x10 > actual_rbw_x10) { - vbwSteps = 1+((frequency_step_x10 + actual_rbw_x10 - 1) / actual_rbw_x10); //((int)(2 * (frequency_step_x10 + (actual_rbw_x10/8)) / actual_rbw_x10)); // calculate # steps in between each frequency step due to rbw being less than frequency step + + actual_rbw_x10 = set_rbw(actual_rbw_x10); // see what rbw the be can realized + + + if (setting.frequency_step > 0) { + freq_t target_frequency_step_x10; + + if (setting.step_delay_mode==SD_FAST) { + target_frequency_step_x10 = frequency_step_x10; + } else if (setting.step_delay_mode==SD_PRECISE) { + target_frequency_step_x10 = 4*frequency_step_x10; + } else { + target_frequency_step_x10 = 2*frequency_step_x10; + } + + if (target_frequency_step_x10 > actual_rbw_x10) { // RBW too small + vbwSteps = (target_frequency_step_x10 + actual_rbw_x10 - 1) / actual_rbw_x10; //((int)(2 * (frequency_step_x10 + (actual_rbw_x10/8)) / actual_rbw_x10)); // calculate # steps in between each frequency step due to rbw being less than frequency step + if (vbwSteps<1) + vbwSteps = 1; } -#else - vbwSteps = ((int)(2 * (frequency_step_x10 + (actual_rbw_x10/2)) / actual_rbw_x10)); // calculate # steps in between each frequency step due to rbw being less than frequency step -#endif - if (setting.step_delay_mode==SD_PRECISE) // if in Precise scanning - vbwSteps *= 2; // use twice as many steps - if (vbwSteps < 1) // at least one step, should never happen - vbwSteps = 1; - } else { // in all other modes - frequency_step_x10 = actual_rbw_x10; } -#ifdef TINYSA4 + + #ifdef TINYSA4 done: fill_spur_table(); // IF frequency depends on selected RBW #endif @@ -3563,7 +3562,10 @@ again: // Spur redu ADF4351_R_counter(3); } else #endif - ADF4351_R_counter(1); + if (get_sweep_frequency(ST_SPAN)<500000) + ADF4351_R_counter(3); + else + ADF4351_R_counter(1); } } else { if (local_modulo == 0) { diff --git a/si4468.c b/si4468.c index 0d128cd..b29f72d 100644 --- a/si4468.c +++ b/si4468.c @@ -1609,10 +1609,10 @@ static const RBW_t RBW_choices[] = {SI4463_RBW_600kHz, -10,6000, 8}, {SI4463_RBW_850kHz, -9,8500, 8}, #else - {SI4463_RBW_02kHz, 18,3, 20}, - {SI4463_RBW_1kHz, 13,10, 15}, - {SI4463_RBW_3kHz, 8,30, 10}, - {SI4463_RBW_10kHz, 3,100, 10}, + {SI4463_RBW_02kHz, 18,3, 25}, + {SI4463_RBW_1kHz, 18,10, 15}, + {SI4463_RBW_3kHz, 13,30, 10}, + {SI4463_RBW_10kHz, 18,100, 20}, {SI4463_RBW_30kHz, 3,300, 15}, {SI4463_RBW_100kHz, -2,1000, 15}, // OK {SI4463_RBW_300kHz, -2,3000, 10}, diff --git a/ui_sa.c b/ui_sa.c index dc0643a..a606412 100644 --- a/ui_sa.c +++ b/ui_sa.c @@ -660,7 +660,7 @@ UI_FUNCTION_CALLBACK(menu_curve_confirm_cb) (void)item; if (data) { float new_offset = local_actual_level - peakLevel + config.correction_value[current_curve][current_curve_index]; // calculate offset based on difference between measured peak level and known peak level - if (new_offset > -25 && new_offset < 25) { + if (new_offset > -30 && new_offset < 30) { config.correction_value[current_curve][current_curve_index] = new_offset; config_save(); } @@ -3706,11 +3706,13 @@ redraw_cal_status: calculate_step_delay(); setting.actual_sweep_time_us = calc_min_sweep_time_us(); } - ili9341_set_foreground((setting.step_delay || setting.sweep_time_us ) ? LCD_BRIGHT_COLOR_GREEN : LCD_FG_COLOR); #if 0 // Activate for sweep time debugging lcd_printf(x, y, "%cScan:\n%5.3Fs", fscan[setting.step_delay_mode&3], (float)setting.sweep_time_us/ONE_SECOND_TIME); #endif - lcd_printf(x, y, "%cScan:\n%5.3Fs", fscan[setting.step_delay_mode&3], (float)setting.actual_sweep_time_us/ONE_SECOND_TIME); + ili9341_set_foreground((setting.step_delay_mode&3) != 0 ? LCD_BRIGHT_COLOR_GREEN : LCD_FG_COLOR); + lcd_printf(x, y, "%cScan:", fscan[setting.step_delay_mode&3]); + ili9341_set_foreground((setting.step_delay || setting.sweep_time_us ) ? LCD_BRIGHT_COLOR_GREEN : LCD_FG_COLOR); + lcd_printf(x, y+YSTEP, "%5.3Fs",(float)setting.actual_sweep_time_us/ONE_SECOND_TIME); y = add_quick_menu(y+=YSTEP, (menuitem_t *)menu_sweep_speed);