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@ -790,7 +790,21 @@ static void SI4463_set_properties(uint16_t prop, void* values, uint8_t len)
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#define GLOBAL_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00
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#define GLOBAL_CLK_CFG 0x11, 0x00, 0x01, 0x01, 0x00
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// ---------------------------------------------------------------------------------------------------- v ------------ RSSI control byte
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#define GLOBAL_RF_MODEM_RAW_CONTROL 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x06, 0x03, 0x10, 0x40
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#define GLOBAL_RF_MODEM_RAW_CONTROL 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x06, 0x03, 0x10, 0x40
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//0x11 SI446X_CMD_SET_PROPERTY
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//0x20 SI446X_PROP_GROUP_MODEM
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//0x0A 10 Count
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//0x45 Start register
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//0x03 [0x45] MODEM_RAW_CONTROL
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//0x00 [0x46] RAWEYE[10:8]
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//0x00 [0x47] RAWEYE[7:0]
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//0x01 [0x48] MODEM_ANT_DIV_MODE
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//0x00 [0x49] MODEM_ANT_DIV_CONTROL
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//0xFF [0x4A] MODEM_RSSI_THRESH
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//0x06 [0x4B] MODEM_RSSI_JUMP_THRESH
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//0x03 [0x4C] MODEM_RSSI_CONTROL
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//0x10 [0x4D] MODEM_RSSI_CONTROL2
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//0x40 [0x4E] MODEM_RSSI_COMP
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// -----------------------------------------------------------------------------------------------------^ --------------
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#define GLOBAL_RF_MODEM_AGC_CONTROL 0x11, 0x20, 0x01, 0x35, 0xF1 // Override AGC gain increase
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@ -969,7 +983,7 @@ void SI4463_start_rx(uint8_t CHANNEL)
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0,
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0,
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0,
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0,// 8,
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8,// 8,
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0,// SI446X_CMD_START_RX_ARG_NEXT_STATE2_RXVALID_STATE_ENUM_RX,
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0, //SI446X_CMD_START_RX_ARG_NEXT_STATE3_RXINVALID_STATE_ENUM_RX
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};
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@ -1195,6 +1209,9 @@ void si_fm_offset(int16_t offset)
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//
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offset = SI4463_offset_value + offset;
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uint8_t data[] = {
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0x11,
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0x20,
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@ -1207,31 +1224,35 @@ void si_fm_offset(int16_t offset)
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SI4463_offset_changed = true;
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SI4463_offset_active = (offset != 0);
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}
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#ifdef __FAST_SWEEP__
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extern deviceRSSI_t age[POINTS_COUNT];
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static int buf_index = 0;
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static bool buf_read = false;
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uint32_t old_t = 0;
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//#define __USE_FFR_FOR_RSSI__
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static char Si446x_readRSSI(void){
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char rssi;
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#ifdef __USE_FFR_FOR_RSSI__
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_ID_START_RX);
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while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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SPI_READ_8BIT(SI4432_SPI); // Skip command byte response
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SI_CS_HIGH;
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_FRR_A);
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SPI_WRITE_8BIT(SI4432_SPI, 0x00); // begin read 1 bytes
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SPI_WRITE_8BIT(SI4432_SPI, 0x00); // begin read 1 bytes
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while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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SPI_READ_8BIT(SI4432_SPI); // Skip command byte response
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char rssi = SPI_READ_8BIT(SI4432_SPI); // Get FRR A
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rssi = SPI_READ_8BIT(SI4432_SPI); // Get FRR A
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SI_CS_HIGH;
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#else
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_GET_MODEM_STATUS);
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while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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SI_CS_HIGH;
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while (!SI4463_READ_CTS); // Wait for CTS
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_CMD_BUFF); // read answer
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@ -1243,8 +1264,10 @@ static char Si446x_readRSSI(void){
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SPI_READ_8BIT(SI4432_SPI); // read CMD_ COMPLETE
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SPI_READ_8BIT(SI4432_SPI); // MODEM_PEND
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SPI_READ_8BIT(SI4432_SPI); // MODEM_STATUS
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char rssi = SPI_READ_8BIT(SI4432_SPI); // CURR_RSSI
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// char rssi = SPI_READ_8BIT(SI4432_SPI); // LATCH_RSSI
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rssi = SPI_READ_8BIT(SI4432_SPI); // CURR_RSSI
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// SPI_WRITE_8BIT(SI4432_SPI, 0x00);
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// while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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// rssi = SPI_READ_8BIT(SI4432_SPI); // LATCH_RSSI
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SI_CS_HIGH;
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#endif
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return rssi;
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@ -1266,25 +1289,55 @@ void SI446x_Fill(int s, int start)
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#endif
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// SPI_BR_SET(SI4432_SPI, SI4432_SPI_FASTSPEED);
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uint32_t t = setting.additional_step_delay_us;
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static uint32_t old_t = 0;
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if (t < old_t +100 && t + 100 > old_t) { // avoid oscillation
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t = (t + old_t) >> 1;
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}
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old_t = t;
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// __disable_irq();
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systime_t measure = chVTGetSystemTimeX();
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int i = start;
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while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes
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#if 0
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while (!SI4463_READ_CTS); // Wait for CTS
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#endif
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__disable_irq();
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do {
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#if 0
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age[i] = Si446x_readRSSI();
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if (++i >= sweep_points) break;
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if (t)
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my_microsecond_delay(t);
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#else
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#if 0
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_ID_START_RX);
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while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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SPI_READ_8BIT(SI4432_SPI); // Skip command byte response
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SI_CS_HIGH;
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#endif
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if (t)
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my_microsecond_delay(t);
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again:
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SI_CS_LOW;
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SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_FRR_A);
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SPI_WRITE_8BIT(SI4432_SPI, 0x00); // begin read 1 bytes
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while (SPI_IS_BUSY(SI4432_SPI)) ; // wait tx
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SPI_READ_8BIT(SI4432_SPI); // Skip command byte response
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age[i] = SPI_READ_8BIT(SI4432_SPI); // Get FRR A
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SI_CS_HIGH;
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// volatile uint8_t state = getFRR(SI446X_CMD_READ_FRR_B);
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if (age[i] == 0) goto again;
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if (++i >= sweep_points) break;
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#endif
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} while(1);
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__enable_irq();
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setting.measure_sweep_time_us = (chVTGetSystemTimeX() - measure)*100;
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// __enable_irq();
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buf_index = (start<=0 ? 0 : start); // Is used to skip 1st entry during level triggering
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buf_read = true;
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}
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@ -1605,10 +1658,9 @@ freq_t SI4463_set_freq(freq_t freq)
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#endif
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} else
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return 0;
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if (SI4463_offset_active) {
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si_set_offset(0);
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SI4463_offset_active = false;
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}
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si_set_offset(0);
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uint32_t R = (freq * SI4463_outdiv) / (Npresc ? 2*config.setting_frequency_30mhz : 4*config.setting_frequency_30mhz) - 1; // R between 0x00 and 0x7f (127)
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uint64_t MOD = 524288; // = 2^19
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uint32_t F = ((freq * SI4463_outdiv*MOD) / (Npresc ? 2*config.setting_frequency_30mhz : 4*config.setting_frequency_30mhz)) - R*MOD;
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@ -1724,27 +1776,10 @@ freq_t SI4463_set_freq(freq_t freq)
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// SI4463_clear_int_status();
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#if 0
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retry:
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#endif
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if (SI4463_in_tx_mode)
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SI4463_start_tx(0);
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else {
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SI4463_start_rx(SI4463_channel);
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#if 0
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si446x_state_t s = SI4463_get_state();
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if (s != SI446X_STATE_RX) {
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SI4463_start_rx(SI4463_channel);
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my_microsecond_delay(1000);
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#if 1
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si446x_state_t s = SI4463_get_state();
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if (s != SI446X_STATE_RX) {
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my_microsecond_delay(3000);
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goto retry;
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}
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#endif
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}
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#endif
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}
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SI4463_wait_for_cts();
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// SI4463_set_gpio(3,GPIO_LOW);
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@ -1771,9 +1806,7 @@ void SI4463_init_rx(void)
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#endif
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clear_frequency_cache();
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SI4463_start_rx(SI4463_channel);
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Si446x_getInfo(&SI4463_info);
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// Si446x_getInfo(&SI4463_info);
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prev_band = -1; // 433MHz
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}
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