From 8443630550036d11d067daa5253ae5e865e8e436 Mon Sep 17 00:00:00 2001 From: erikkaashoek Date: Sun, 24 Jan 2021 17:19:18 +0100 Subject: [PATCH] FAST scanning working --- ili9341.c | 4 ++ nanovna.h | 2 +- radio_config_Si4468_100kHz.h | 32 +++++++------- radio_config_Si4468_10kHz.h | 32 +++++++------- radio_config_Si4468_1kHz.h | 32 +++++++------- radio_config_Si4468_200Hz.h | 32 +++++++------- radio_config_Si4468_300kHz.h | 32 +++++++------- radio_config_Si4468_30kHz.h | 32 +++++++------- radio_config_Si4468_3kHz.h | 32 +++++++------- radio_config_Si4468_850kHz.h | 40 +++++++++--------- radio_config_Si4468_default.h | 40 +++++++++--------- sa_core.c | 79 ++++++++++++----------------------- si4432.c | 6 +++ ui_sa.c | 22 +++++----- 14 files changed, 202 insertions(+), 215 deletions(-) diff --git a/ili9341.c b/ili9341.c index 833f1c6..3c9e3c6 100644 --- a/ili9341.c +++ b/ili9341.c @@ -473,6 +473,8 @@ void ili9341_fill(int x, int y, int w, int h) send_region("fill", x,y,w,h); spi_buffer[0] = background_color; send_buffer((uint8_t *)spi_buffer, 2); + osalThreadSleepMilliseconds(2); + // auto_capture = false; } // LCD_CS_HIGH; @@ -493,6 +495,8 @@ void ili9341_bulk(int x, int y, int w, int h) if (auto_capture) { send_region("bulk", x,y,w,h); send_buffer((uint8_t *)spi_buffer, w*h*2); + osalThreadSleepMilliseconds(2); + // auto_capture = false; } #endif diff --git a/nanovna.h b/nanovna.h index 40d6dcf..d88b17a 100644 --- a/nanovna.h +++ b/nanovna.h @@ -65,7 +65,7 @@ #define HIGH_MAX_FREQ_MHZ 960 #endif #ifdef TINYSA4 -#define DEFAULT_IF ((uint32_t)977000000) +#define DEFAULT_IF ((uint32_t)977100000) #define DEFAULT_SPUR_OFFSET ((uint32_t)1500000) #define DEFAULT_MAX_FREQ ((uint32_t)800000000) #define HIGH_MIN_FREQ_MHZ 825 diff --git a/radio_config_Si4468_100kHz.h b/radio_config_Si4468_100kHz.h index 92d6751..7d33b40 100644 --- a/radio_config_Si4468_100kHz.h +++ b/radio_config_Si4468_100kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 50000 Fdev(Hz): 25000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 50000 Fdev(Hz): 25000 RXBW(Hz): 100000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 2 (BW = 103.06 kHz); NB-filter 2 (BW = 103.06 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xF9, 0x00, 0x4B +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x20, 0x20, 0x00, 0xB5, 0x00, 0x4B /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0xDA +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0xDA /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0xAA, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x85, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_10kHz.h b/radio_config_Si4468_10kHz.h index 3f96389..b919176 100644 --- a/radio_config_Si4468_10kHz.h +++ b/radio_config_Si4468_10kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 5000 Fdev(Hz): 2500 RXBW(Hz): 10000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 5000 Fdev(Hz): 2500 RXBW(Hz): 10000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 4 (BW = 10.33 kHz); NB-filter 4 (BW = 10.33 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x20, 0x0C, 0xF9, 0x00, 0x5E +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x20, 0x0C, 0xB5, 0x00, 0x5E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x76, 0x1A, 0x05, 0x72, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x16 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x05, 0x76, 0x1A, 0x05, 0x72, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x16 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x55, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0x55, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x04, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x84, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0A, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x62, 0x04, 0x0A, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_1kHz.h b/radio_config_Si4468_1kHz.h index 970b2ac..cee6c51 100644 --- a/radio_config_Si4468_1kHz.h +++ b/radio_config_Si4468_1kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 500 Fdev(Hz): 250 RXBW(Hz): 1000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 500 Fdev(Hz): 250 RXBW(Hz): 1000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 2 (BW = 1.07 kHz); NB-filter 2 (BW = 1.07 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x54, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x54, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x06, 0x90, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x02 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x06, 0x90, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x02 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x99, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0x99, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x85, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_200Hz.h b/radio_config_Si4468_200Hz.h index c3e5cf0..f9b3bd6 100644 --- a/radio_config_Si4468_200Hz.h +++ b/radio_config_Si4468_200Hz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 100 Fdev(Hz): 50 RXBW(Hz): 200 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 100 Fdev(Hz): 50 RXBW(Hz): 200 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 11 (BW = 0.21 kHz); NB-filter 11 (BW = 0.21 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x74, 0xF9, 0x00, 0xC3 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x74, 0xB5, 0x00, 0xC3 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x02, 0x9F, 0x17, 0x02, 0xA0, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x01 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x02, 0x9F, 0x17, 0x02, 0xA0, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x01 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0xA4, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x00, 0xA4, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x05, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x65, 0x04, 0x05, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_300kHz.h b/radio_config_Si4468_300kHz.h index b7f058d..5dc016f 100644 --- a/radio_config_Si4468_300kHz.h +++ b/radio_config_Si4468_300kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 150000 Fdev(Hz): 75000 RXBW(Hz): 300000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 150000 Fdev(Hz): 75000 RXBW(Hz): 300000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 1 (BW = 305.23 kHz); NB-filter 1 (BW = 305.23 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x10, 0x00, 0xF9, 0x00, 0x43 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x00, 0x10, 0x00, 0xB5, 0x00, 0x43 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xAE, 0x14, 0x07, 0xA4, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x05, 0x1F +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xAE, 0x14, 0x07, 0xA4, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x05, 0x1F /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xDF, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0xDF, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x06, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x86, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0E, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x0E, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x39, 0x04, 0x0B, 0x05, 0x04, 0x01, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_30kHz.h b/radio_config_Si4468_30kHz.h index 81071d5..4b6efed 100644 --- a/radio_config_Si4468_30kHz.h +++ b/radio_config_Si4468_30kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 15000 Fdev(Hz): 7500 RXBW(Hz): 30000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 15000 Fdev(Hz): 7500 RXBW(Hz): 30000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 3 (BW = 30.87 kHz); NB-filter 3 (BW = 30.87 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x30, 0x10, 0x00, 0xF9, 0x00, 0x53 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x30, 0x10, 0x00, 0xB5, 0x00, 0x53 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x42 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x24, 0xDD, 0x06, 0x2B, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x42 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x7F, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0x7F, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x85, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0B, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x62, 0x04, 0x0B, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_3kHz.h b/radio_config_Si4468_3kHz.h index d1050d8..ebed6b9 100644 --- a/radio_config_Si4468_3kHz.h +++ b/radio_config_Si4468_3kHz.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 1500 Fdev(Hz): 750 RXBW(Hz): 3000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 1500 Fdev(Hz): 750 RXBW(Hz): 3000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 2 (BW = 3.22 kHz); NB-filter 2 (BW = 3.22 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xF0, 0x20, 0x2C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xF0, 0x20, 0x2C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x06, 0x90, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x07 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x06, 0x90, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x07 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0x99, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x01, 0x99, 0x01, 0x00, 0xFF, 0x06, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x85, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x0C, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_850kHz.h b/radio_config_Si4468_850kHz.h index b4ba52e..3ca3569 100644 --- a/radio_config_Si4468_850kHz.h +++ b/radio_config_Si4468_850kHz.h @@ -20,14 +20,14 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 500000 Fdev(Hz): 300000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 500000 Fdev(Hz): 250000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 1 (BW = 915.70 kHz); NB-filter 1 (BW = 915.70 kHz) // -// Modulation index: 1.2 +// Modulation index: 1 */ @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x28 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x22 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0xF6 +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x22 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xB5, 0x00, 0x3C /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0x1C, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x08, 0x89 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x00, 0xD0, 0x08, 0x00, 0x23, 0x08, 0x89 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x02, 0x4C, 0xCD, 0x00, 0x27, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x02, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x02, 0x7F, 0x01, 0x00, 0xFF, 0x08, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x02, 0x14, 0x01, 0x00, 0xFF, 0x08, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x08, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x87, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x13, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x10, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_default.h b/radio_config_Si4468_default.h index 7cd4f70..3ca3569 100644 --- a/radio_config_Si4468_default.h +++ b/radio_config_Si4468_default.h @@ -20,9 +20,9 @@ // INPUT DATA /* // Crys_freq(Hz): 30000000 Crys_tol(ppm): 0 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 400000 Fdev(Hz): 200000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 977 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 +// MOD_type: 2 Rsymb(sps): 500000 Fdev(Hz): 250000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 3 Rsymb_error: 0.15 Chip-Version: 2 +// RF Freq.(MHz): 977 API_TC: 29 fhst: 100000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// API_ARR_Det_en: 1 Fdev_error: 0 API_ETSI: 1 // // # RX IF frequency is -468750 Hz // # WB filter 1 (BW = 915.70 kHz); NB-filter 1 (BW = 915.70 kHz) @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xB5, 0x00, 0x4E /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x12, 0x00, 0x11 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -222,7 +222,7 @@ // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. */ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 +#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x83, 0x00, 0x85, 0x01, 0x00 /* // Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 @@ -260,7 +260,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 +#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x83, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1 @@ -286,7 +286,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x04, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x08, 0x80, 0x00, 0x0D, 0xA7, 0x20, 0xFF /* // Command: RF_START_RX @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x3D, 0x09, 0x00, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x1B +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x4C, 0x4B, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x22 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -518,7 +518,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x4F +#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x22 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x4B +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x09, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xB5, 0x00, 0x3C /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0xD3, 0xA0, 0x06, 0xD4, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0D, 0xA7 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x89, 0x07, 0xFF, 0x00, 0xD0, 0x08, 0x00, 0x23, 0x08, 0x89 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xEA, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x77, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x08, 0x08, 0x80, 0x02, 0x40, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x22, 0x07, 0x07, 0x80, 0x02, 0x40, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x01, 0xAA, 0x01, 0x00, 0xFF, 0x08, 0x00, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x83, 0x02, 0x14, 0x01, 0x00, 0xFF, 0x08, 0x08, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -652,7 +652,7 @@ // MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. // MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. */ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x05, 0x07 +#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x87, 0x07 /* // Set properties: RF_MODEM_RSSI_MUTE_1_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0C, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x61, 0x04, 0x10, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x14, 0x07, 0x0B, 0x02, 0x10, 0x73, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x22, 0x22, 0x20, 0xFF +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x40, 0x09, 0x11, 0x11, 0x0D, 0xA7, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/sa_core.c b/sa_core.c index e8aa7ff..90bcaea 100644 --- a/sa_core.c +++ b/sa_core.c @@ -48,6 +48,7 @@ int debug_frequencies = false; static unsigned long old_freq[5] = { 0, 0, 0, 0,0}; static unsigned long real_old_freq[5] = { 0, 0, 0, 0,0}; +static long real_offset = 0; //int setting.refer = -1; // Off by default const int reffer_freq[] = {30000000, 15000000, 10000000, 4000000, 3000000, 2000000, 1000000}; @@ -1086,7 +1087,7 @@ void calculate_step_delay(void) #endif #endif #ifdef __SI4463__ - if (actual_rbw_x10 >= 8500) { SI4432_step_delay = 400; SI4432_offset_delay = 100; spur_gate = 50; } + if (actual_rbw_x10 >= 6000) { SI4432_step_delay = 200; SI4432_offset_delay = 100; spur_gate = 50; } else if (actual_rbw_x10 >= 3000) { SI4432_step_delay = 400; SI4432_offset_delay = 100; spur_gate = 50; } else if (actual_rbw_x10 >= 1000) { SI4432_step_delay = 400; SI4432_offset_delay = 100; spur_gate = 70; } else if (actual_rbw_x10 >= 300) { SI4432_step_delay = 1000; SI4432_offset_delay = 30; spur_gate = 80; } @@ -1247,6 +1248,8 @@ void setupSA(void) #define OFFSET_LOWER_BOUND 0 #endif +static int fast_counter = 0; + void set_freq(int V, unsigned long freq) // translate the requested frequency into a setting of the SI4432 { if (old_freq[V] == freq) // Do not change HW if not needed @@ -1332,62 +1335,29 @@ void set_freq(int V, unsigned long freq) // translate the requested frequency } else if (V==ADF4351_LO2) { real_old_freq[V] = ADF4351_set_frequency(V-ADF4351_LO, freq); } else if (V==SI4463_RX) { - if (false && setting.step_delay_mode == SD_FAST) { // If in extra fast scanning mode and NOT SI4432_RX !!!!!! - int delta = freq - real_old_freq[V]; -//#define OFFSET_STEP 14.30555 -#define OFFSET_STEP 12.3981 + if (setting.step_delay_mode == SD_FAST && fast_counter++ < 100) { // If in extra fast scanning mode and NOT SI4432_RX !!!!!! + long delta = (long)freq - (long)real_old_freq[V]; +#define OFFSET_STEP 14.30555 // 30MHz +//#define OFFSET_STEP 12.3981 #define OFFSET_RANGE 937500 // Hz + real_offset = delta; if (real_old_freq[V] >= 480000000) // 480MHz, high band delta = delta >> 1; - delta = ((float)delta) / OFFSET_STEP; // Calculate and set the offset register i.s.o programming a new frequency - if (delta > - 0x6fff && delta < 0x6fff) { // and requested frequency can easily be reached by using the offset registers -#if 0 - if (real_old_freq[V] >= 480000000) - shell_printf("%d: Offs %q HW %d\r\n", SI4432_Sel, (uint32_t)(real_old_freq[V]+delta*2), real_old_freq[V]); - else - shell_printf("%d: Offs %q HW %d\r\n", SI4432_Sel, (uint32_t)(real_old_freq[V]+delta*1), real_old_freq[V]); -#endif + delta = ((float)delta) / OFFSET_STEP; // Calculate and set the offset register i.s.o programming a new frequency + if (delta > - 0x7fff && delta < 0x7fff) { // and requested frequency can be reached by using the offset registers static int old_delta = 0x20000; if (old_delta != delta) { si_set_offset(delta); // Signal offset changed so RSSI retrieval is delayed for frequency settling old_delta = delta; } - old_freq[V] = freq; - } else { -#ifdef __WIDE_OFFSET__ - uint32_t target_f = freq; // Impossible to use offset so set SI4432 to new frequency -#if 0 - if (freq < real_old_freq[V]) { // sweeping down - if (freq - OFFSET_RANGE >= 480000000) { - target_f = freq - OFFSET_RANGE*2; - } else { - target_f = freq - OFFSET_RANGE; - } - SI4463_set_freq(target_f); - si_set_offset(0x7fff); // set offset to most positive - real_old_freq[V] = target_f; - } else { // sweeping up - if (freq + OFFSET_RANGE >= 480000000) { - target_f = freq + OFFSET_RANGE*2; - } else { - target_f = freq + OFFSET_RANGE; - } -#else - { -#endif - real_old_freq[V] = SI4463_set_freq(target_f); // Also sets offset to zero - } -#else - SI4432_Set_Frequency(freq); // Impossible to use offset so set SI4432 to new frequency - SI4432_Write_2_Byte(SI4432_FREQ_OFFSET1, 0, 0); // set offset to zero -// SI4432_Write_Byte(SI4432_FREQ_OFFSET2, 0); - real_old_freq[V] = freq; -#endif + goto done; } - } else { - real_old_freq[V] = SI4463_set_freq(freq); // Not in fast mode } + fast_counter = 0; // Offset tuning not possible + real_offset = 0; + real_old_freq[V] = SI4463_set_freq(freq); // Not in fast mode } +done: old_freq[V] = freq; } @@ -2350,7 +2320,12 @@ modulation_again: #endif } if (debug_frequencies && SDU1.config->usbp->state == USB_ACTIVE) { - uint32_t f = real_old_freq[ADF4351_LO] - real_old_freq[SI4463_RX]; + + uint32_t f; + if (setting.mode == M_LOW || setting.mode == M_GENLOW) + f = real_old_freq[ADF4351_LO] - (real_old_freq[SI4463_RX] + real_offset); + else + f = real_old_freq[SI4463_RX] + real_offset; float f_error; if (setting.frequency_step == 0) { f_error = ((float)f-(float)frequencies[i]); @@ -2358,7 +2333,7 @@ modulation_again: f_error = ((float)f-(float)frequencies[i])/setting.frequency_step; } char shifted = ( LO_shifted ? '>' : ' '); - shell_printf ("%d:LO=%11.6q\t%cIF=%11.6q\tF=%11.6q\tD=%.2f\r\n", i, real_old_freq[ADF4351_LO], shifted, real_old_freq[SI4463_RX], f , f_error); + shell_printf ("%d:LO=%11.6q\t%cIF=%11.6q\tF=%11.6q\tD=%.2f\r\n", i, real_old_freq[ADF4351_LO], shifted, real_old_freq[SI4463_RX] + real_offset, f , f_error); osalThreadSleepMilliseconds(100); } // ------------------------- end of processing when in output mode ------------------------------------------------ @@ -3355,7 +3330,7 @@ const test_case_t test_case [] = {TC_MEASURE, TPH_30MHZ, 270, 4, -40, 10, -65 }, // 14 Calibrate power high mode {TC_END, 0, 0, 0, 0, 0, 0}, #define TEST_RBW 16 - {TC_MEASURE, TP_30MHZ, 30, 1, -20, 10, -60 }, // 16 Measure RBW step time + {TC_MEASURE, TP_30MHZ, 30, 1, CAL_LEVEL, 10, -60 }, // 16 Measure RBW step time {TC_END, 0, 0, 0, 0, 0, 0}, {TC_MEASURE, TPH_30MHZ, 300, 4, -48, 10, -65 }, // 14 Calibrate power high mode {TC_MEASURE, TPH_30MHZ_SWITCH,300, 4, -40, 10, -65 }, // 14 Calibrate power high mode @@ -3842,7 +3817,7 @@ void self_test(int test) setting.frequency_IF=config.frequency_IF1; ui_mode_normal(); test_prepare(TEST_RBW); - setting.step_delay = 8000; + setting.step_delay = 15000; for (int j= 0; j < SI4432_RBW_count; j++ ) { if (setting.test_argument != 0) j = setting.test_argument; @@ -3904,8 +3879,8 @@ void self_test(int test) setting.step_delay = setting.step_delay * 4 / 5; #endif - setting.offset_delay = 1600; -#if 0 // Enable for offset tuning stepping + setting.offset_delay = 5000; +#if 1 // Enable for offset tuning stepping test_value = saved_peakLevel; if ((uint32_t)(setting.rbw_x10 * 1000) / (sweep_points) < 8000) { // fast mode possible while (setting.offset_delay > 0 && test_value != 0 && test_value > saved_peakLevel - 1.5) { diff --git a/si4432.c b/si4432.c index 33e05a8..d400bce 100644 --- a/si4432.c +++ b/si4432.c @@ -1961,6 +1961,12 @@ int16_t Si446x_RSSI(void) my_microsecond_delay(10); goto again; } +#if 0 + if (data[2] == 0) { +// my_microsecond_delay(10); + goto again; + } +#endif RSSI_RAW_ARRAY[--j] = data[2]; if (j == 0) break; my_microsecond_delay(20); diff --git a/ui_sa.c b/ui_sa.c index 1453f2e..5d92fdc 100644 --- a/ui_sa.c +++ b/ui_sa.c @@ -1185,11 +1185,13 @@ static UI_FUNCTION_CALLBACK(menu_marker_delete_cb) } static const uint16_t rbwsel_x10[]={0,3,10,30,100,300,1000,3000,6000}; +static const char* rbwsel_text[]={"auto","300","1k","3k","10k","30k","100k","300k","600k"}; + static UI_FUNCTION_ADV_CALLBACK(menu_rbw_acb) { (void)item; if (b){ - b->param_1.u = rbwsel_x10[data]*100; + b->param_1.text = rbwsel_text[data]; b->icon = setting.rbw_x10 == rbwsel_x10[data] ? BUTTON_ICON_GROUP_CHECKED : BUTTON_ICON_GROUP; return; } @@ -1638,14 +1640,14 @@ static const menuitem_t menu_average[] = { static const menuitem_t menu_rbw[] = { { MT_ADV_CALLBACK, 0, " AUTO", menu_rbw_acb}, - { MT_ADV_CALLBACK, 1, "%3.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 2, "%3.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 3, "%4.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 4, "%4.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 5, "%4.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 6, "%4.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 7, "%3.1qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 8, "%3.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 1, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 2, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 3, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 4, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 5, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 6, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 7, "%sHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 8, "%sHz", menu_rbw_acb}, { MT_CANCEL, 0, S_LARROW" BACK", NULL }, { MT_NONE, 0, NULL, NULL } // sentinel }; @@ -2676,7 +2678,7 @@ redraw_cal_status: ili9341_drawstring("RBW:", x, y); y += YSTEP; - plot_printf(buf, BLEN, "%.1FkHz", actual_rbw_x10/10.0); + plot_printf(buf, BLEN, "%.1FHz", actual_rbw_x10*100.0); y = add_quick_menu(buf, x, y,(menuitem_t *)menu_rbw); #if 0