From 7fdaa5a5210acd6e76fd9eb8162a73e0bdf59fe1 Mon Sep 17 00:00:00 2001 From: erikkaashoek Date: Thu, 17 Jun 2021 16:48:40 +0200 Subject: [PATCH] Tuned RBW factors and repaired save/load --- flash.c | 6 +++++- nanovna.h | 10 +++++++++- sa_core.c | 12 ++++++------ si4468.c | 18 +++++++++--------- 4 files changed, 29 insertions(+), 17 deletions(-) diff --git a/flash.c b/flash.c index c7c6ef0..fd8accf 100644 --- a/flash.c +++ b/flash.c @@ -221,12 +221,16 @@ caldata_recall(uint16_t id) /* duplicated saved data onto sram to be able to modify marker/trace */ memcpy(dst, src, sizeof(setting_t)); // Restore stored trace - memcpy(stored_t, &src[1], sizeof(stored_t)); + src = &(src[1]); + volatile void *dst2 = stored_t; + memcpy(dst2, src, sizeof(stored_t)); update_min_max_freq(); update_frequencies(); set_scale(setting.scale); set_reflevel(setting.reflevel); set_waterfall(); + if (setting.show_stored) + enableTracesAtComplete(TRACE_STORED_FLAG); return 0; } #if 0 diff --git a/nanovna.h b/nanovna.h index 5a5848c..a23ae5c 100644 --- a/nanovna.h +++ b/nanovna.h @@ -1081,7 +1081,11 @@ extern int linear_averaging; // Flash save area - flash7 : org = 0x0801B000, len = 20k in *.ld file // 2k - for config save // 9 * 2k for setting_t + stored trace +#ifdef TINYSA4 +#define SAVEAREA_MAX 5 +#else #define SAVEAREA_MAX 9 +#endif // STM32 minimum page size for write #define FLASH_PAGESIZE 0x800 // config save area (flash7 addr) @@ -1090,13 +1094,17 @@ extern int linear_averaging; #endif #ifdef TINYSA4 -#define SAVE_CONFIG_ADDR 0x0803B000 +#define SAVE_CONFIG_ADDR 0x0803A800 #endif #define SAVE_CONFIG_SIZE 0x00000800 // setting_t save area (save area + config size) #define SAVE_PROP_CONFIG_ADDR (SAVE_CONFIG_ADDR + SAVE_CONFIG_SIZE) +#ifdef TINYSA4 +#define SAVE_PROP_CONFIG_SIZE 0x00001000 +#else #define SAVE_PROP_CONFIG_SIZE 0x00000800 +#endif // Should include all save slots #define SAVE_CONFIG_AREA_SIZE (SAVE_CONFIG_SIZE + SAVEAREA_MAX * SAVE_PROP_CONFIG_SIZE) diff --git a/sa_core.c b/sa_core.c index a24daf3..a400b5b 100644 --- a/sa_core.c +++ b/sa_core.c @@ -1493,13 +1493,13 @@ static const struct { float log_aver_correction; } step_delay_table[]={ // RBWx10 step_delay offset_delay spur_gate (value divided by 1000) - { 8500, 150, 50, 400, -90, 0.4}, - { 6000, 150, 50, 300, -95, 0.5}, - { 3000, 150, 50, 200, -95, 0.8}, - { 1000, 600, 100, 100, -105, 0.4}, - { 300, 800, 120, 100, -110, 0.9}, + { 8500, 150, 50, 400, -90, 0.7}, + { 6000, 150, 50, 300, -95, 0.8}, + { 3000, 150, 50, 200, -95, 1.3}, + { 1000, 600, 100, 100, -105, 0.3}, + { 300, 800, 120, 100, -110, 0.7}, { 100, 1500, 120, 100, -115, 0.5}, - { 30, 1500, 300, 100, -120, 1.2}, + { 30, 1500, 300, 100, -120, 0.7}, { 10, 5000, 600, 100, -122, 1.1}, { 3, 19000, 12000, 100, -125, 1.0} }; diff --git a/si4468.c b/si4468.c index 9827bec..43af3c7 100644 --- a/si4468.c +++ b/si4468.c @@ -1579,15 +1579,15 @@ typedef struct { static const RBW_t RBW_choices[] = { // BW register corr freq - {SI4463_RBW_02kHz, 21,3, 26}, - {SI4463_RBW_1kHz, 26,10, 10}, - {SI4463_RBW_3kHz, 22,30, 8}, - {SI4463_RBW_10kHz, 12,100, 9}, - {SI4463_RBW_30kHz, 12,300, 12}, - {SI4463_RBW_100kHz, 7,1000, 10}, - {SI4463_RBW_300kHz, 8,3000, 7}, - {SI4463_RBW_600kHz, 8,6000, 15}, - {SI4463_RBW_850kHz,18,8500, 15}, + {SI4463_RBW_02kHz, 20,3, 26}, + {SI4463_RBW_1kHz, 23,10, 8}, + {SI4463_RBW_3kHz, 17,30, 9}, + {SI4463_RBW_10kHz, 12,100, 7}, + {SI4463_RBW_30kHz, 12,300, 10}, + {SI4463_RBW_100kHz, 2,1000, 17}, + {SI4463_RBW_300kHz, 4,3000, 10}, + {SI4463_RBW_600kHz, 10,6000, 8}, + {SI4463_RBW_850kHz, 15,8500, 8}, }; const uint8_t SI4432_RBW_count = ((int)(sizeof(RBW_choices)/sizeof(RBW_t)));