From 4f13e0472c9608b470634cc7388723396e24af5d Mon Sep 17 00:00:00 2001 From: DiSlord Date: Wed, 3 Mar 2021 11:34:49 +0300 Subject: [PATCH 1/3] Move mcuconf.h files to board/CPU folder --- .settings/language.settings.xml | 73 ++- NANOVNA_STM32_F072/mcuconf.h | 478 ++++++++++++++++++ .../mcuconf.h | 0 mcuconf.h | 461 +---------------- 4 files changed, 530 insertions(+), 482 deletions(-) create mode 100644 NANOVNA_STM32_F072/mcuconf.h rename mcuconf_F303.h => NANOVNA_STM32_F303/mcuconf.h (100%) diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml index c2188e1..ac357e9 100644 --- a/.settings/language.settings.xml +++ b/.settings/language.settings.xml @@ -1,27 +1,52 @@ - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/NANOVNA_STM32_F072/mcuconf.h b/NANOVNA_STM32_F072/mcuconf.h new file mode 100644 index 0000000..1d4b073 --- /dev/null +++ b/NANOVNA_STM32_F072/mcuconf.h @@ -0,0 +1,478 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#ifdef TINYSA_F303 + +/* + * STM32F3xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F3xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#if 0 // 72MHz +#define STM32_HSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#else +#define STM32_HSI_ENABLED TRUE // 48MHz +#define STM32_HSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 // prediv HSI always 2 +#define STM32_USBPRE STM32_USBPRE_DIV1 +#endif +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +// Set SPI1 more faster use PPRE2 max speed +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2 +#define STM32_ADC12PRES STM32_ADC12PRES_DIV2 +//#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 +#define STM32_USART1SW STM32_USART1SW_PCLK +//#define STM32_USART2SW STM32_USART2SW_PCLK +//#define STM32_USART3SW STM32_USART3SW_PCLK +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +//#define STM32_I2C2SW STM32_I2C2SW_SYSCLK +#define STM32_TIM1SW STM32_TIM1SW_PCLK2 +#define STM32_TIM8SW STM32_TIM8SW_PCLK2 +#define STM32_USB_CLOCK_REQUIRED TRUE + +/* + * RTC driver system settings for stm32f303 + */ + +#ifndef VNA_USE_LSE +// Use 40kHz LSI +#define STM32_LSE_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTC_PRESA_VALUE 40 +#define STM32_RTC_PRESS_VALUE 1000 +#else +// Use 32768Hz LSE +#define STM32_LSE_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_LSEDRV (3 << 3) +#endif + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +//#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +//#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +//#define STM32_ADC_ADC34_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 2 +//#define STM32_ADC_ADC34_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2 +//#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 +//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK +//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +//#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 +#define STM32_ADC_DUAL_MODE FALSE + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 + +#define STM32_DISABLE_EXTI2122_HANDLER TRUE + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM4 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 +#define STM32_GPT_TIM4_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 +#define STM32_I2C_USE_DMA TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI1 FALSE +#define STM32_I2S_USE_SPI2 TRUE +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ + STM32_I2S_MODE_RX ) +#define STM32_I2S_SPI1_IRQ_PRIORITY 2 +#define STM32_I2S_SPI2_IRQ_PRIORITY 2 +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#else + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 +#define STM32_PREDIV_VALUE 1 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_ADCSW STM32_ADCSW_HSI14 +#define STM32_USBSW STM32_USBSW_HSI48 +#define STM32_CECSW STM32_CECSW_HSI +//#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_I2C1SW STM32_I2C1SW_SYSCLK +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 +#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 + +#define STM32_DISABLE_EXTI2122_HANDLER TRUE + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 TRUE +#define STM32_GPT_USE_TIM14 TRUE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 +#define STM32_GPT_TIM14_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 + +// I2C1 rx operation use DMA3, some as SPI1 DMA Tx used by LCD +#define STM32_I2C_USE_DMA FALSE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI1 FALSE +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI1_IRQ_PRIORITY 2 +#define STM32_I2S_SPI2_IRQ_PRIORITY 2 +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 TRUE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif + +#endif /* MCUCONF_H */ diff --git a/mcuconf_F303.h b/NANOVNA_STM32_F303/mcuconf.h similarity index 100% rename from mcuconf_F303.h rename to NANOVNA_STM32_F303/mcuconf.h diff --git a/mcuconf.h b/mcuconf.h index 1d4b073..b343ec3 100644 --- a/mcuconf.h +++ b/mcuconf.h @@ -14,465 +14,10 @@ limitations under the License. */ -#ifndef MCUCONF_H -#define MCUCONF_H - #ifdef TINYSA_F303 - -/* - * STM32F3xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F3xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#if 0 // 72MHz -#define STM32_HSI_ENABLED FALSE -#define STM32_HSE_ENABLED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_USBPRE STM32_USBPRE_DIV1P5 -#else -#define STM32_HSI_ENABLED TRUE // 48MHz -#define STM32_HSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSI -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 12 // prediv HSI always 2 -#define STM32_USBPRE STM32_USBPRE_DIV1 -#endif -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -// Set SPI1 more faster use PPRE2 max speed -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2 -#define STM32_ADC12PRES STM32_ADC12PRES_DIV2 -//#define STM32_ADC34PRES STM32_ADC34PRES_DIV1 -#define STM32_USART1SW STM32_USART1SW_PCLK -//#define STM32_USART2SW STM32_USART2SW_PCLK -//#define STM32_USART3SW STM32_USART3SW_PCLK -#define STM32_I2C1SW STM32_I2C1SW_SYSCLK -//#define STM32_I2C2SW STM32_I2C2SW_SYSCLK -#define STM32_TIM1SW STM32_TIM1SW_PCLK2 -#define STM32_TIM8SW STM32_TIM8SW_PCLK2 -#define STM32_USB_CLOCK_REQUIRED TRUE - -/* - * RTC driver system settings for stm32f303 - */ - -#ifndef VNA_USE_LSE -// Use 40kHz LSI -#define STM32_LSE_ENABLED FALSE -#define STM32_LSI_ENABLED TRUE -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTC_PRESA_VALUE 40 -#define STM32_RTC_PRESS_VALUE 1000 -#else -// Use 32768Hz LSE -#define STM32_LSE_ENABLED TRUE -#define STM32_LSI_ENABLED FALSE -#define STM32_RTCSEL STM32_RTCSEL_LSE -#define STM32_RTC_PRESA_VALUE 32 -#define STM32_RTC_PRESS_VALUE 1024 -#define STM32_LSEDRV (3 << 3) +#include "NANOVNA_STM32_F303/mcuconf.h" #endif -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 TRUE -#define STM32_ADC_USE_ADC2 TRUE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -//#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) -//#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC12_DMA_PRIORITY 2 -//#define STM32_ADC_ADC34_DMA_PRIORITY 2 -#define STM32_ADC_ADC12_IRQ_PRIORITY 2 -//#define STM32_ADC_ADC34_IRQ_PRIORITY 5 -#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2 -//#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 5 -//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK -//#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 -#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -//#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 -#define STM32_ADC_DUAL_MODE FALSE - -/* - * CAN driver system settings. - */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 TRUE -#define STM32_DAC_USE_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 - -/* - * EXT driver system settings. - */ -#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 - -#define STM32_DISABLE_EXTI2122_HANDLER TRUE - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 TRUE -#define STM32_GPT_USE_TIM4 TRUE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM4_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 TRUE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_I2C2_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_USE_SPI2 TRUE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ - STM32_I2S_MODE_RX ) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI2_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 TRUE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USART1_PRIORITY 3 -#define STM32_SERIAL_USART2_PRIORITY 3 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI2_IRQ_PRIORITY 2 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_IRQ_PRIORITY 3 -#define STM32_UART_USART2_IRQ_PRIORITY 3 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - -#else - -/* - * STM32F0xx drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 3...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -#define STM32F0xx_MCUCONF - -/* - * HAL driver system settings. - */ -#define STM32_NO_INIT FALSE -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_HSI_ENABLED TRUE -#define STM32_HSI14_ENABLED TRUE -#define STM32_HSI48_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED FALSE -#define STM32_LSE_ENABLED FALSE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2 -#define STM32_PREDIV_VALUE 1 -#define STM32_PLLMUL_VALUE 12 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE STM32_PPRE_DIV1 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCOSEL STM32_MCOSEL_PLLDIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_ADCSW STM32_ADCSW_HSI14 -#define STM32_USBSW STM32_USBSW_HSI48 -#define STM32_CECSW STM32_CECSW_HSI -//#define STM32_I2C1SW STM32_I2C1SW_HSI -#define STM32_I2C1SW STM32_I2C1SW_SYSCLK -#define STM32_USART1SW STM32_USART1SW_PCLK -#define STM32_RTCSEL STM32_RTCSEL_LSI - -/* - * ADC driver system settings. - */ -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) - -/* - * DAC driver system settings. - */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 TRUE -#define STM32_DAC_USE_DAC1_CH2 TRUE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) - -/* - * EXT driver system settings. - */ -#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI16_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI17_IRQ_PRIORITY 3 -#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3 - -#define STM32_DISABLE_EXTI2122_HANDLER TRUE - -/* - * GPT driver system settings. - */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 TRUE -#define STM32_GPT_USE_TIM14 TRUE -#define STM32_GPT_TIM1_IRQ_PRIORITY 2 -#define STM32_GPT_TIM2_IRQ_PRIORITY 2 -#define STM32_GPT_TIM3_IRQ_PRIORITY 2 -#define STM32_GPT_TIM14_IRQ_PRIORITY 2 - -/* - * I2C driver system settings. - */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_IRQ_PRIORITY 3 -#define STM32_I2C_I2C2_IRQ_PRIORITY 3 - -// I2C1 rx operation use DMA3, some as SPI1 DMA Tx used by LCD -#define STM32_I2C_USE_DMA FALSE -#define STM32_I2C_I2C1_DMA_PRIORITY 1 -#define STM32_I2C_I2C2_DMA_PRIORITY 1 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") - -/* - * I2S driver system settings. - */ -#define STM32_I2S_USE_SPI1 FALSE -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_SLAVE | \ - STM32_I2S_MODE_RX) -#define STM32_I2S_SPI1_IRQ_PRIORITY 2 -#define STM32_I2S_SPI2_IRQ_PRIORITY 2 -#define STM32_I2S_SPI1_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") - -/* - * ICU driver system settings. - */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 3 -#define STM32_ICU_TIM2_IRQ_PRIORITY 3 -#define STM32_ICU_TIM3_IRQ_PRIORITY 3 - -/* - * PWM driver system settings. - */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 3 -#define STM32_PWM_TIM2_IRQ_PRIORITY 3 -#define STM32_PWM_TIM3_IRQ_PRIORITY 3 - -/* - * SERIAL driver system settings. - */ -#define STM32_SERIAL_USE_USART1 TRUE -#define STM32_SERIAL_USE_USART2 FALSE -#define STM32_SERIAL_USART1_PRIORITY 3 -#define STM32_SERIAL_USART2_PRIORITY 3 - -/* - * SPI driver system settings. - */ -#define STM32_SPI_USE_SPI1 TRUE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 2 -#define STM32_SPI_SPI2_IRQ_PRIORITY 2 -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") - -/* - * ST driver system settings. - */ -#define STM32_ST_IRQ_PRIORITY 2 -#define STM32_ST_USE_TIMER 2 - -/* - * UART driver system settings. - */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USART1_IRQ_PRIORITY 3 -#define STM32_UART_USART2_IRQ_PRIORITY 3 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") - -/* - * USB driver system settings. - */ -#define STM32_USB_USE_USB1 TRUE -#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE -#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 - -/* - * WDG driver system settings. - */ -#define STM32_WDG_USE_IWDG FALSE - +#ifdef TINYSA_F072 +#include "NANOVNA_STM32_F072/mcuconf.h" #endif - -#endif /* MCUCONF_H */ From 71697475b75ac44db058ba969754e7cc33357c45 Mon Sep 17 00:00:00 2001 From: DiSlord Date: Wed, 3 Mar 2021 11:51:32 +0300 Subject: [PATCH 2/3] Update RTC module --- main.c | 36 ++++++++---- rtc.c | 177 +++++++++++++++++++++++++++++++++------------------------ ui.c | 24 +++++++- 3 files changed, 151 insertions(+), 86 deletions(-) diff --git a/main.c b/main.c index 95fe5b6..2090565 100644 --- a/main.c +++ b/main.c @@ -75,8 +75,6 @@ static volatile vna_shellcmd_t shell_function = 0; //#define ENABLED_DUMP // Allow get threads debug info #define ENABLE_THREADS_COMMAND -// RTC time not used -//#define ENABLE_TIME_COMMAND // Enable vbat_offset command, allow change battery voltage correction in config #define ENABLE_VBAT_OFFSET_COMMAND // Info about NanoVNA, need fore soft @@ -620,17 +618,35 @@ VNA_SHELL_FUNCTION(cmd_power) } #endif -#ifdef ENABLE_TIME_COMMAND -#if HAL_USE_RTC == FALSE -#error "Error cmd_time require define HAL_USE_RTC = TRUE in halconf.h" -#endif +#ifdef __USE_RTC__ VNA_SHELL_FUNCTION(cmd_time) { - RTCDateTime timespec; (void)argc; (void)argv; - rtcGetTime(&RTCD1, ×pec); - shell_printf("%d/%d/%d %d\r\n", timespec.year+1980, timespec.month, timespec.day, timespec.millisecond); + uint32_t dt_buf[2]; + dt_buf[0] = rtc_get_tr_bcd(); // TR should be read first for sync + dt_buf[1] = rtc_get_dr_bcd(); // DR should be read second + static const uint8_t idx_to_time[] = {6,5,4,2, 1, 0}; + static const char time_cmd[] = "y|m|d|h|min|sec"; + // 0 1 2 4 5 6 + // time[] ={sec, min, hr, 0, day, month, year, 0} + uint8_t *time = (uint8_t*)dt_buf; + if (argc == 3 && get_str_index(argv[0], "b") == 0){ + rtc_set_time(my_atoui(argv[1]), my_atoui(argv[2])); + return; + } + if (argc!=2) goto usage; + int idx = get_str_index(argv[0], time_cmd); + uint32_t val = my_atoui(argv[1]); + if (idx < 0 || val > 99) + goto usage; + // Write byte value in struct + time[idx_to_time[idx]] = ((val/10)<<4)|(val%10); // value in bcd format + rtc_set_time(dt_buf[1], dt_buf[0]); + return; +usage: + shell_printf("20%02X/%02X/%02X %02X:%02X:%02X\r\n"\ + "usage: time {[%s] 0-99} or {b 0xYYMMDD 0xHHMMSS}\r\n", time[6], time[5], time[4], time[2], time[1], time[0], time_cmd); } #endif @@ -2428,7 +2444,7 @@ static const VNAShellCommand commands[] = #ifdef __VNA__ {"offset" , cmd_offset , 0}, #endif -#ifdef ENABLE_TIME_COMMAND +#ifdef __USE_RTC__ {"time" , cmd_time , 0}, #endif {"dac" , cmd_dac , 0}, diff --git a/rtc.c b/rtc.c index 9bac4d9..dee4384 100644 --- a/rtc.c +++ b/rtc.c @@ -56,90 +56,119 @@ uint32_t rtc_get_FAT(void) { return fattime; } -void rtc_set_time(uint32_t dr, uint32_t tr) { - // Beginning of configuration procedure. - RTC->ISR |= RTC_ISR_INIT; - while ((RTC->ISR & RTC_ISR_INITF) == 0) - ; - // Writing the registers. - RTC->TR = tr; - RTC->DR = dr; +// Finish of configuration procedure. +static void rtc_exit_init(void) { RTC->ISR &= ~RTC_ISR_INIT; } -#define RTC_PRER(a, s) ((((a) - 1) << 16) | ((s) - 1)) +// Beginning of configuration procedure. +static bool rtc_enter_init(void){ + RTC->ISR |= RTC_ISR_INIT; + uint32_t count = 4*65536; + while (--count) + if (RTC->ISR & RTC_ISR_INITF) + return true; + return false; +} + +void rtc_set_time(uint32_t dr, uint32_t tr) { + if (rtc_enter_init()){ + RTC->TR = tr; // Write TR register + RTC->DR = dr; // Write TD register + } + rtc_exit_init(); +} + +#ifdef VNA_AUTO_SELECT_RTC_SOURCE + +// Enable LSE bypass if need +#if defined(STM32_LSE_BYPASS) +#define STM32_LSE_BYPASS RCC_BDCR_LSEBYP +#else +#define STM32_LSE_BYPASS 0 +#endif + +// Startup LSE or if not work, LSI generator +static void rtc_start_source(void){ + // LSE already work (enabled and ready) + if ((RCC->BDCR & (RCC_BDCR_LSEON|RCC_BDCR_LSERDY|STM32_LSE_BYPASS)) == (RCC_BDCR_LSEON|RCC_BDCR_LSERDY|STM32_LSE_BYPASS)) + return; + + // If LSE not enabled, try startup + RCC->BDCR |= STM32_LSEDRV | STM32_LSE_BYPASS | RCC_BDCR_LSEON; + // Waits until LSE is stable (need ~150ms for startup). + chThdSleepMilliseconds(200); + if (RCC->BDCR & RCC_BDCR_LSERDY) return; + + // Startup LSI if not allow start LSE + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0); +} + +static void resetBCDR(uint32_t rtc_drv){ + // Backup domain reset, for change source. + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + // Startup again source generator + rtc_start_source(); + // Select new clock source. And enable + RCC->BDCR|= rtc_drv; +} -// Initiate RTC clock, LSE or LSI generators initiate by ChibiOS !!! +void auto_backup_domain_init(void){ + // Init Backup domain, RTC clock source + uint32_t rtc_drv; + // Backup domain access enabled and left open. + PWR->CR |= PWR_CR_DBP; + // Start/check source + rtc_start_source(); + // Check LSE ready, if ok, select as source + rtc_drv = RCC->BDCR & RCC_BDCR_LSERDY ? STM32_RTCSEL_LSE|RCC_BDCR_RTCEN : // Select LSE as source + STM32_RTCSEL_LSI|RCC_BDCR_RTCEN; // Select LSI as source + // If the backup domain hasn't been initialized yet or work on different source, then proceed with initialization + if ((RCC->BDCR & (STM32_RTCSEL_MASK|RCC_BDCR_RTCEN)) != rtc_drv) + resetBCDR(rtc_drv); +/* + // Check RTC clock, and reset backup domain to LSI if clock not start + if (rtc_enter_init()) + rtc_exit_init(); + else + resetBCDR(STM32_RTCSEL_LSI|RCC_BDCR_RTCEN); +*/ +} +#endif + +// Initiate RTC clock void rtc_init(void){ +#ifdef VNA_AUTO_SELECT_RTC_SOURCE + // Auto start LSE or LSI source for RTC + auto_backup_domain_init(); +#else + // ChibiOS init BDCR LSE or LSI source by self from user defined in mcuconf.h source + // For add auto select RTC source need rewrite it + // see hal_lld_backup_domain_init() in hal_lld.c for every CPU + // Default RTC clock is LSE, but it possible not launch if no quartz installed +#endif + uint32_t src = RCC->BDCR & STM32_RTCSEL_MASK; + if (src == STM32_RTCSEL_NOCLOCK) return; + // If calendar has not been initialized yet or different PRER settings then proceed with the initial setup. // Disable write protection. RTC->WPR = 0xCA; RTC->WPR = 0x53; + uint32_t rtc_prer = (src == STM32_RTCSEL_LSE) ? STM32_RTC_LSE_PRER : + STM32_RTC_LSI_PRER; // If calendar has not been initialized yet then proceed with the initial setup. - if (!(RTC->ISR & RTC_ISR_INITS)) { - // Beginning of configuration procedure. - RTC->ISR |= RTC_ISR_INIT; - while ((RTC->ISR & RTC_ISR_INITF) == 0) - ; - RTC->CR = 0; - RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT. - RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE); - RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE); - RTC->ISR &= ~RTC_ISR_INIT; + if ((RTC->ISR & RTC_ISR_INITS) == 0 || RTC->PRER != rtc_prer) { + if (rtc_enter_init()){ + RTC->CR = 0; + RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT. + RTC->PRER = rtc_prer; // Prescaler value loaded in registers 2 times + RTC->PRER = rtc_prer; + } + // Finalizing of configuration procedure. + rtc_exit_init(); } else RTC->ISR &= ~RTC_ISR_RSF; -#if 0 - // ChibiOS init BDCR by self!! - // For add auto select RTC source need rewrite it - // see hal_lld_backup_domain_init() in hal_lld.c for every CPU - // Default RTC clock is LSE, but it possible not launch if no quartz installed - uint32_t rtc_drv = STM32_RTCSEL_LSI; - uint32_t rtc_prer = RTC_PRER(40, 1000); - - // If LSE off try launch it - if ((RCC->BDCR & RCC_BDCR_LSEON) == 0){ - // Try start LSE - RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; - uint32_t count = 65535; - do{ - if (RCC->BDCR & RCC_BDCR_LSERDY) break; - }while (--count);// Waits until LSE is stable. or count == 0 - } - // Check, if LSE ready, then prepare it data - if (RCC->BDCR & RCC_BDCR_LSERDY){ - rtc_drv = STM32_RTCSEL_LSE; - rtc_prer = RTC_PRER(32, 1024); - } else{ - // Try start LSI - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; - } - - PWR->CR |= PWR_CR_DBP; - // If the backup domain hasn't been initialized yet then proceed with initialization or source different - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0 || (RCC->BDCR & STM32_RTCSEL_MASK)!=rtc_drv) { - // Backup domain reset. - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - // Selects clock source. - RCC->BDCR |= rtc_drv; - // Disable write protection. - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - // Beginning of configuration procedure. - RTC->ISR |= RTC_ISR_INIT; - while ((RTC->ISR & RTC_ISR_INITF) == 0) - ; - // Prescaler value loaded in registers. - RTC->CR = 0; - RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT. - RTC->PRER = rtc_prer; - RTC->PRER = rtc_prer; - // Finalizing of configuration procedure. - RTC->ISR &= ~RTC_ISR_INIT; - RCC->BDCR |= RCC_BDCR_RTCEN; // RTC clock enabled. - } -#endif } -#endif +#endif // __USE_RTC__ diff --git a/ui.c b/ui.c index 2d109f8..43b7c00 100644 --- a/ui.c +++ b/ui.c @@ -474,8 +474,8 @@ show_version(void) do {shift>>=1; y+=5;} while (shift&1); ili9341_drawstring(info_about[i++], x, y+=5); } + char buf[96]; #ifdef TINYSA4 - static char buf[96]; extern const char *states[]; #define ENABLE_THREADS_COMMAND @@ -501,14 +501,34 @@ extern const char *states[]; } while (tp != NULL); #endif - #endif // TINYSA4 + uint16_t cnt = 0; while (true) { if (touch_check() == EVT_TOUCH_PRESSED) break; if (btn_check() & EVT_BUTTON_SINGLE_CLICK) break; + chThdSleepMilliseconds(40); + if ((cnt++)&0x07) continue; // Not update time so fast +#ifdef __USE_RTC__ + uint32_t tr = rtc_get_tr_bin(); // TR read first + uint32_t dr = rtc_get_dr_bin(); // DR read second + plot_printf(buf, sizeof(buf), "Time: 20%02d/%02d/%02d %02d:%02d:%02d" " (LS%c)", + RTC_DR_YEAR(dr), + RTC_DR_MONTH(dr), + RTC_DR_DAY(dr), + RTC_TR_HOUR(dr), + RTC_TR_MIN(dr), + RTC_TR_SEC(dr), + (RCC->BDCR & STM32_RTCSEL_MASK) == STM32_RTCSEL_LSE ? 'E' : 'I'); + ili9341_drawstring(buffer, x, y); +#endif +#if 1 + uint32_t vbat=adc_vbat_read(); + plot_printf(buf, sizeof(buf), "Batt: %d.%03dV", vbat/1000, vbat%1000); + ili9341_drawstring(buf, x, y + FONT_STR_HEIGHT + 2); +#endif } touch_start_watchdog(); From f972ba35a0da4dac068c1a78ef60a2ac2011e4be Mon Sep 17 00:00:00 2001 From: DiSlord Date: Wed, 3 Mar 2021 11:58:48 +0300 Subject: [PATCH 3/3] Fix touch calibrate string position on bigger display --- ui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ui.c b/ui.c index 43b7c00..f7f7607 100644 --- a/ui.c +++ b/ui.c @@ -388,7 +388,7 @@ touch_cal_exec(void) ili9341_line(LCD_WIDTH-1, LCD_HEIGHT-1, LCD_WIDTH-1, LCD_HEIGHT-32); ili9341_line(LCD_WIDTH-1, LCD_HEIGHT-1, LCD_WIDTH-32, LCD_HEIGHT-1); ili9341_line(LCD_WIDTH-1, LCD_HEIGHT-1, LCD_WIDTH-32, LCD_HEIGHT-32); - ili9341_drawstring("TOUCH LOWER RIGHT", 210, 200); + ili9341_drawstring("TOUCH LOWER RIGHT", LCD_WIDTH-17*(FONT_WIDTH)-30, LCD_HEIGHT-FONT_GET_HEIGHT-35); touch_wait_released(); // touch_wait_release();