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@ -931,6 +931,9 @@ uint32_t registers[6] = {0xC80000, 0x8008011, 0x1800C642, 0x48963,0xA5003C , 0x
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#else
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uint32_t registers[6] = {0xA00000, 0x8000011, 0x4E42, 0x4B3,0xDC003C , 0x580005} ; //10 MHz ref
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#endif
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uint32_t old_registers[6];
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bool reg_dirty[6] = {true, true, true, true, true, true};
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int debug = 0;
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ioline_t ADF4351_LE[2] = { LINE_LO_SEL, LINE_LO_SEL};
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//int ADF4351_Mux = 7;
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@ -954,7 +957,7 @@ uint64_t PFDRFout[6] = {XTAL,XTAL,XTAL,10000000,10000000,10000000}; //Reference
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//uint64_t Chrystal[6] = {XTAL,XTAL,XTAL,10000000,10000000,10000000};
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//double FRACF; // Temp
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volatile int64_t
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int64_t
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// INTA, // Temp
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ADF4350_modulo = 0, // Linked to spur table!!!!!
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// MOD,
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@ -1013,11 +1016,16 @@ void ADF4351_Setup(void)
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void ADF4351_WriteRegister32(int channel, const uint32_t value)
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{
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registers[value & 0x07] = value;
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for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF);
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palSetLine(ADF4351_LE[channel]);
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my_microsecond_delay(1); // Must
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palClearLine(ADF4351_LE[channel]);
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// if (reg_dirty[value & 0x07] || (value & 0x07) == 0) {
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if (old_registers[value & 0x07] != registers[value & 0x07] || (value & 0x07) == 0 ) {
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registers[value & 0x07] = value;
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for (int i = 3; i >= 0; i--) shiftOut((value >> (8 * i)) & 0xFF);
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palSetLine(ADF4351_LE[channel]);
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my_microsecond_delay(1); // Must
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palClearLine(ADF4351_LE[channel]);
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// reg_dirty[value & 0x07] = false;
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old_registers[value & 0x07] = registers[value & 0x07];
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}
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}
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void ADF4351_Set(int channel)
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@ -1038,12 +1046,14 @@ void ADF4351_Set(int channel)
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void ADF4351_disable_output(void)
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{
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bitClear (registers[4], 5); // main output
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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void ADF4351_enable_output(void)
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{
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bitSet (registers[4], 5); // main output
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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#endif
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@ -1090,6 +1100,7 @@ void ADF4351_spur_mode(int S)
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bitSet (registers[2], 30); // R set to 8
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else
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bitClear (registers[2], 30); // R set to 8
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reg_dirty[2] = true;
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ADF4351_Set(0);
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}
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@ -1116,6 +1127,8 @@ void ADF4351_R_counter(int R)
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clear_frequency_cache(); // When R changes the possible frequencies will change
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registers[2] &= ~ (((unsigned long)0x3FF) << 14);
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registers[2] |= (((unsigned long)R) << 14);
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reg_dirty[2] = true;
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ADF4351_Set(0);
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}
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@ -1123,6 +1136,7 @@ void ADF4351_mux(int R)
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{
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registers[2] &= ~ (((unsigned long)0x7) << 26);
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registers[2] |= (((unsigned long)R & (unsigned long)0x07) << 26);
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reg_dirty[2] = true;
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ADF4351_Set(0);
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}
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@ -1130,6 +1144,7 @@ void ADF4351_csr(int c)
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{
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registers[3] &= ~ (((unsigned long)0x1) << 18);
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registers[3] |= (((unsigned long)c & (unsigned long)0x01) << 18);
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reg_dirty[3] = true;
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ADF4351_Set(0);
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}
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@ -1137,6 +1152,7 @@ void ADF4351_fastlock(int c)
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{
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registers[3] &= ~ (((unsigned long)0x3) << 15);
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registers[3] |= (((unsigned long)c & (unsigned long)0x03) << 15);
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reg_dirty[3] = true;
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ADF4351_Set(0);
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}
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@ -1144,6 +1160,7 @@ void ADF4351_CP(int p)
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{
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registers[2] &= ~ (((unsigned long)0xF) << 9);
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registers[2] |= (((unsigned long)p) << 9);
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reg_dirty[2] = true;
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ADF4351_Set(0);
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}
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@ -1152,6 +1169,7 @@ void ADF4351_drive(int p)
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p &= 0x03;
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registers[4] &= ~ (((unsigned long)0x3) << 3);
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registers[4] |= (((unsigned long)p) << 3);
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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@ -1160,6 +1178,7 @@ void ADF4351_aux_drive(int p)
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p &= 0x03;
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registers[4] &= ~ (((unsigned long)0x3) << 6);
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registers[4] |= (((unsigned long)p) << 6);
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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#if 0
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@ -1207,10 +1226,11 @@ uint64_t ADF4351_prepare_frequency(int channel, uint64_t freq) // freq / 10Hz
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bitWrite (registers[4], 21, 0);
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bitWrite (registers[4], 20, 0);
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}
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reg_dirty[4] = true;
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#if 1
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volatile uint32_t PFDR = (uint32_t)PFDRFout[channel];
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uint32_t PFDR = (uint32_t)PFDRFout[channel];
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uint32_t MOD = ADF4350_modulo;
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if (MOD == 0)
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MOD = 60;
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@ -1225,7 +1245,7 @@ uint64_t ADF4351_prepare_frequency(int channel, uint64_t freq) // freq / 10Hz
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#else
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volatile uint64_t PFDR = PFDRFout[channel];
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uint64_t PFDR = PFDRFout[channel];
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uint16_t MOD = ADF4350_modulo;
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if (MOD == 0)
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MOD = 60;
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@ -1257,7 +1277,7 @@ uint64_t ADF4351_prepare_frequency(int channel, uint64_t freq) // freq / 10Hz
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#endif
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uint64_t actual_freq = ((uint64_t)PFDR *(INTA * MOD +FRAC))/OutputDivider / MOD;
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#if 0
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volatile int max_delta = PFDRFout[channel]/OutputDivider/MOD/100;
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int max_delta = PFDRFout[channel]/OutputDivider/MOD/100;
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if (actual_freq < freq - max_delta || actual_freq > freq + max_delta ){
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while(1)
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my_microsecond_delay(10);
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@ -1276,11 +1296,13 @@ uint64_t ADF4351_prepare_frequency(int channel, uint64_t freq) // freq / 10Hz
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registers[0] = 0;
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registers[0] = INTA << 15; // OK
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registers[0] = registers[0] + (FRAC << 3);
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reg_dirty[0] = true;
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if (MOD == 1) MOD = 2;
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registers[1] = 0;
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registers[1] = MOD << 3;
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registers[1] = registers[1] + 1 ; // restore address "001"
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bitSet (registers[1], 27); // Prescaler at 8/9
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reg_dirty[1] = true;
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return actual_freq;
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}
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@ -1290,6 +1312,7 @@ void ADF4351_enable(int s)
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bitClear(registers[4], 11); // Inverse logic!!!!!
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else
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bitSet(registers[4], 11);
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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@ -1299,6 +1322,7 @@ void ADF4351_enable_aux_out(int s)
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bitSet(registers[4], 8);
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else
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bitClear(registers[4], 8);
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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@ -1313,6 +1337,8 @@ void ADF4351_enable_out(int s)
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bitSet(registers[2], 5); // Enable power down
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bitSet(registers[2], 11); // Enable VCO power down
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}
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reg_dirty[2] = true;
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reg_dirty[4] = true;
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ADF4351_Set(0);
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}
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@ -1585,7 +1611,7 @@ void SI4463_set_output_level(int t)
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}
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void SI4463_start_tx(uint8_t CHANNEL)
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{
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// volatile si446x_state_t s;
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// si446x_state_t s;
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#if 0
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s = SI4463_get_state();
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if (s == SI446X_STATE_RX){
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@ -1649,7 +1675,7 @@ void SI4463_start_tx(uint8_t CHANNEL)
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void SI4463_start_rx(uint8_t CHANNEL)
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{
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volatile si446x_state_t s = SI4463_get_state();
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si446x_state_t s = SI4463_get_state();
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if (s == SI446X_STATE_TX){
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SI4463_set_state(SI446X_STATE_READY);
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}
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@ -2626,7 +2652,7 @@ void SI4463_init_rx(void)
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clear_frequency_cache();
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SI4463_start_rx(SI4463_channel);
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#if 0
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volatile si446x_state_t s ;
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si446x_state_t s ;
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again:
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Si446x_getInfo(&SI4463_info);
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@ -2675,7 +2701,7 @@ reset:
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#endif
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SI4463_start_tx(0);
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#if 0
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volatile si446x_state_t s ;
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si446x_state_t s ;
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again:
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Si446x_getInfo(&SI4463_info);
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