diff --git a/NANOVNA_STM32_F303/board.c b/NANOVNA_STM32_F303/board.c
index 59ab7f8..82b9c2f 100644
--- a/NANOVNA_STM32_F303/board.c
+++ b/NANOVNA_STM32_F303/board.c
@@ -126,4 +126,6 @@ void __early_init(void) {
  * Board-specific initialization code.
  */
 void boardInit(void) {
+    // Speedup flash latency
+  FLASH->ACR= FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_0;
 }
diff --git a/radio_config_Si4468_short.h b/radio_config_Si4468_short.h
index 1332eb2..6c0054e 100644
--- a/radio_config_Si4468_short.h
+++ b/radio_config_Si4468_short.h
@@ -16,23 +16,23 @@
 
 #undef RADIO_CONFIGURATION_DATA_ARRAY
 #define RADIO_CONFIGURATION_DATA_ARRAY { \
-		0x10, RF_MODEM_MOD_TYPE_12_1, \
+		0x10, RF_MODEM_MOD_TYPE_12_1,  \
 /*      0x05, RF_MODEM_FREQ_DEV_0_1_1, */ \
-        0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
-        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \
-        0x07, RF_MODEM_AFC_LIMITER_1_3_1, \
-        0x05, RF_MODEM_AGC_CONTROL_1_1, \
-        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \
+      0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
+/*        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1,*/ \
+/*        0x07, RF_MODEM_AFC_LIMITER_1_3_1,*/ \
+/*        0x05, RF_MODEM_AGC_CONTROL_1_1,*/ \
+/*        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1,*/ \
         0x0E, RF_MODEM_RAW_CONTROL_10, \
  /*     0x06, RF_MODEM_RAW_SEARCH2_2_1, */ \
  /*       0x06, RF_MODEM_SPIKE_DET_2_1, */ \
  /*       0x05, RF_MODEM_RSSI_MUTE_1_1, */ \
-        0x09, RF_MODEM_DSA_CTRL1_5_1, \
+ /*       0x09, RF_MODEM_DSA_CTRL1_5_1, */ \
         0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
         0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
         0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
-        0x05, RF_PA_TC_1_1, \
-        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \
+/*        0x05, RF_PA_TC_1_1, */ \
+/*        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, */ \
 /*        0x0C, RF_FREQ_CONTROL_INTE_8_1, */ \
         0x00 \
  }
diff --git a/sa_core.c b/sa_core.c
index d8f9638..45ca434 100644
--- a/sa_core.c
+++ b/sa_core.c
@@ -1419,9 +1419,9 @@ static const struct {
   {  1000,       300,          100,      100,   -105},
   {   300,       400,          120,      100,   -110},
   {   100,       600,          120,      100,   -115},
-  {    30,      1100,          300,      100,   -120},
+  {    30,      1500,          300,      100,   -120},
   {    10,      5000,          600,      100,   -122},
-  {     3,     14000,         3000,      100,   -125}
+  {     3,     19000,         3000,      100,   -125}
 };
 #endif
 
diff --git a/si4468.c b/si4468.c
index c0014f5..afb38a0 100644
--- a/si4468.c
+++ b/si4468.c
@@ -967,12 +967,22 @@ void SI4463_start_rx(uint8_t CHANNEL)
     SI4463_set_state(SI446X_STATE_READY);
   }
   SI4463_refresh_gpio();
+
+
+
+
 #if 0
   {
     uint8_t data[] =
     {
-     0x11, 0x20, 0x01, 0x00,
-     0x0A,  // Restore 2FSK mode
+       0x11, 0x10, 0x01, 0x03, 0xf0
+    };
+    SI4463_do_api(data, sizeof(data), NULL, 0); // Send PREAMBLE_CONFIG_STD_2 for long timeout
+  }
+  {
+    uint8_t data[] =
+    {
+     0x11, 0x20, 0x01, 0x00, 0x09,  // Restore OOK mode
     };
     SI4463_do_api(data, sizeof(data), NULL, 0);
   }
@@ -983,7 +993,7 @@ void SI4463_start_rx(uint8_t CHANNEL)
     0,
     0,
     0,
-    8,// 8,
+    0,// 8,
     0,// SI446X_CMD_START_RX_ARG_NEXT_STATE2_RXVALID_STATE_ENUM_RX,
     0, //SI446X_CMD_START_RX_ARG_NEXT_STATE3_RXINVALID_STATE_ENUM_RX
   };
@@ -1300,18 +1310,18 @@ void SI446x_Fill(int s, int start)
   systime_t measure = chVTGetSystemTimeX();
   int i = start;
   while(SPI_RX_IS_NOT_EMPTY(SI4432_SPI)) (void)SPI_READ_8BIT(SI4432_SPI);      // Remove lingering bytes
-#if 0
+#if 1
   while (!SI4463_READ_CTS);         // Wait for CTS
 #endif
   __disable_irq();
   do {
-#if 0
+#if 1
     age[i] = Si446x_readRSSI();
     if (++i >= sweep_points) break;
     if (t)
       my_microsecond_delay(t);
 #else
-#if 0
+#if 1
     SI_CS_LOW;
   SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_ID_START_RX);
   while (SPI_IS_BUSY(SI4432_SPI)) ;      // wait tx