diff --git a/NANOVNA_STM32_F303/board.h b/NANOVNA_STM32_F303/board.h index c193e1d..0811b95 100644 --- a/NANOVNA_STM32_F303/board.h +++ b/NANOVNA_STM32_F303/board.h @@ -354,7 +354,7 @@ PIN_MODE_INPUT(11) | \ PIN_MODE_INPUT(12) | \ PIN_MODE_OUTPUT(GPIOC_LED) | \ - PIN_MODE_OUTPUT(14) | \ + PIN_MODE_INPUT(14) | \ PIN_MODE_OUTPUT(15)) #define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ PIN_OTYPE_PUSHPULL(1) | \ diff --git a/SI4463_radio_config.h_saved b/SI4463_radio_config.h_saved deleted file mode 100644 index 294b05b..0000000 --- a/SI4463_radio_config.h_saved +++ /dev/null @@ -1,87 +0,0 @@ - -#ifndef RADIO_CONFIG_H_ -#define RADIO_CONFIG_H_ - -#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80 -#define RF_GPIO_PIN_CFG 0x13, 0x41, 0x41, 0x21, 0x20, 0x67, 0x4B, 0x00 -#define GLOBAL_2_0 0x11, 0x00, 0x04, 0x00, 0x52, 0x00, 0x18, 0x30 -#define MODEM_2_0 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00 -#define MODEM_2_1 0x11, 0x20, 0x01, 0x0C, 0x46 -#define MODEM_2_2 0x11, 0x20, 0x0C, 0x1C, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xE8, 0x00, 0x4E, 0x06, 0x8D, 0xB9, 0x00 -#define MODEM_2_3 0x11, 0x20, 0x0A, 0x28, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0xC6, 0xD4, 0x01, 0x5C -#define MODEM_2_4 0x11, 0x20, 0x0B, 0x39, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 -#define MODEM_2_5 0x11, 0x20, 0x09, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00, 0xFF, 0x06, 0x09, 0x10 -#define MODEM_2_6 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A -#define MODEM_2_7 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 -#define MODEM_2_8 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 -#define MODEM_CHFLT_2_0 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00 -#define MODEM_CHFLT_2_1 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B -#define MODEM_CHFLT_2_2 0x11, 0x21, 0x0B, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F -#define PA_2_0 0x11, 0x22, 0x01, 0x03, 0x1D -#define FREQ_CONTROL_2_0 0x11, 0x40, 0x08, 0x00, 0x37, 0x09, 0x00, 0x00, 0x44, 0x44, 0x20, 0xFE -#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 -#define INT_CTL_5_0 0x11, 0x01, 0x04, 0x00, 0x07, 0x18, 0x00, 0x00 -#define FRR_CTL_5_0 0x11, 0x02, 0x03, 0x00, 0x0A, 0x09, 0x00 -#define PREAMBLE_5_0 0x11, 0x10, 0x01, 0x04, 0x31 -#define SYNC_5_0 0x11, 0x11, 0x04, 0x01, 0xB4, 0x2B, 0x00, 0x00 -#define PKT_5_0 0x11, 0x12, 0x0A, 0x00, 0x04, 0x01, 0x08, 0xFF, 0xFF, 0x20, 0x00, 0x00, 0x2A, 0x01 -#define PKT_5_1 0x11, 0x12, 0x07, 0x0E, 0x01, 0x06, 0xAA, 0x00, 0x80, 0x02, 0x2A -#define MODEM_5_0 0x11, 0x20, 0x0A, 0x03, 0x1E, 0x84, 0x80, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x0D, 0xA7 -#define MODEM_5_1 0x11, 0x20, 0x0B, 0x1E, 0x10, 0x20, 0x00, 0xE8, 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD4 -#define MODEM_5_2 0x11, 0x20, 0x09, 0x2A, 0x00, 0x00, 0x00, 0x23, 0xC6, 0xD4, 0x00, 0xA9, 0xE0 -#define MODEM_5_3 0x11, 0x20, 0x05, 0x39, 0x10, 0x10, 0x80, 0x1A, 0x40 -#define MODEM_5_4 0x11, 0x20, 0x08, 0x46, 0x01, 0x15, 0x02, 0x00, 0x80, 0x06, 0x02, 0x18 -#define MODEM_5_5 0x11, 0x20, 0x01, 0x50, 0x84 -#define MODEM_5_6 0x11, 0x20, 0x01, 0x54, 0x04 -#define MODEM_5_7 0x11, 0x20, 0x01, 0x5D, 0x08 -#define MODEM_CHFLT_5_0 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08 -#define MODEM_CHFLT_5_1 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE -#define MODEM_CHFLT_5_2 0x11, 0x21, 0x0B, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F -#define SYNTH_5_0 0x11, 0x23, 0x06, 0x00, 0x34, 0x04, 0x0B, 0x04, 0x07, 0x70 -#define FREQ_CONTROL_5_0 0x11, 0x40, 0x04, 0x00, 0x38, 0x0D, 0xDD, 0xDD - -#define RADIO_CONFIGURATION_DATA_ARRAY { \ -0x07, RF_POWER_UP, \ -0x08, RF_GPIO_PIN_CFG, \ -0x08, GLOBAL_2_0, \ -0x10, MODEM_2_0, \ -0x05, MODEM_2_1, \ -0x10, MODEM_2_2, \ -0x0E, MODEM_2_3, \ -0x0F, MODEM_2_4, \ -0x0D, MODEM_2_5, \ -0x06, MODEM_2_6, \ -0x06, MODEM_2_7, \ -0x09, MODEM_2_8, \ -0x10, MODEM_CHFLT_2_0, \ -0x10, MODEM_CHFLT_2_1, \ -0x0F, MODEM_CHFLT_2_2, \ -0x05, PA_2_0, \ -0x0C, FREQ_CONTROL_2_0, \ -0x08, RF_START_RX, \ -0x05, RF_IRCAL, \ -0x05, RF_IRCAL_1, \ -0x08, INT_CTL_5_0, \ -0x07, FRR_CTL_5_0, \ -0x05, PREAMBLE_5_0, \ -0x08, SYNC_5_0, \ -0x0E, PKT_5_0, \ -0x0B, PKT_5_1, \ -0x0E, MODEM_5_0, \ -0x0F, MODEM_5_1, \ -0x0D, MODEM_5_2, \ -0x09, MODEM_5_3, \ -0x0C, MODEM_5_4, \ -0x05, MODEM_5_5, \ -0x05, MODEM_5_6, \ -0x05, MODEM_5_7, \ -0x10, MODEM_CHFLT_5_0, \ -0x10, MODEM_CHFLT_5_1, \ -0x0F, MODEM_CHFLT_5_2, \ -0x0A, SYNTH_5_0, \ -0x08, FREQ_CONTROL_5_0, \ -} - -#endif diff --git a/SI4468_radio_config_7kHz.h b/SI4468_radio_config_7kHz.h deleted file mode 100644 index c8eb38b..0000000 --- a/SI4468_radio_config_7kHz.h +++ /dev/null @@ -1,902 +0,0 @@ -/*! @file radio_config.h - * @brief This file contains the automatically generated - * configurations. - * - * @n WDS GUI Version: 3.2.11.0 - * @n Device: Si4468 Rev.: A2 - * - * @b COPYRIGHT - * @n Silicon Laboratories Confidential - * @n Copyright 2017 Silicon Laboratories, Inc. - * @n http://www.silabs.com - */ - -//#ifndef RADIO_CONFIG_H_ -#define RADIO_CONFIG_H_ - -// USER DEFINED PARAMETERS -// Define your own parameters here - -// INPUT DATA -/* -// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 100 Fdev(Hz): 1000 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 915 API_TC: 0 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 -// -// -// -// -// Modulation index: 20 -*/ - - -// CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000 - - -// CONFIGURATION COMMANDS - -/* -// Command: RF_POWER_UP -// Description: Command to power-up the device and select the operational mode and functionality. -*/ -#define RF_POWER_UP 0x02, 0x01, 0x01, 0x01, 0xC9, 0xC3, 0x80 - -/* -// Command: RF_GPIO_PIN_CFG -// Description: Configures the GPIO pins. -*/ -#define RF_GPIO_PIN_CFG 0x13, 0x11, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00 - -/* -// Set properties: RF_GLOBAL_XO_TUNE_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x00 -// Default values: 0x40, -// Descriptions: -// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator. -*/ -#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x00 - -/* -// Set properties: RF_GLOBAL_CONFIG_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x03 -// Default values: 0x20, -// Descriptions: -// GLOBAL_CONFIG - Global configuration settings. -*/ -#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20 - -/* -// Set properties: RF_PREAMBLE_CONFIG_1 -// Number of properties: 1 -// Group ID: 0x10 -// Start ID: 0x04 -// Default values: 0x21, -// Descriptions: -// PREAMBLE_CONFIG - General configuration bits for the Preamble field. -*/ -#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21 - -/* -// Set properties: RF_MODEM_MOD_TYPE_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x00 -// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, -// Descriptions: -// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. -// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. -// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. -// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. -// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x00 - -/* -// Set properties: RF_MODEM_FREQ_DEV_0_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x0C -// Default values: 0xD3, -// Descriptions: -// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x23 - -/* -// Set properties: RF_MODEM_TX_RAMP_DELAY_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x18 -// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, -// Descriptions: -// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. -// MODEM_MDM_CTRL - MDM control. -// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. -// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). -// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections. -// MODEM_IFPKD_THRESHOLDS - -// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -*/ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x4E - -/* -// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x24 -// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, -// Descriptions: -// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GEAR - RX BCR loop gear control. -// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. -// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls. -// MODEM_AFC_GEAR - RX AFC loop gear control. -// MODEM_AFC_WAIT - RX AFC loop wait time control. -// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -*/ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x06, 0x8D, 0xB9, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x11 - -/* -// Set properties: RF_MODEM_AFC_LIMITER_1_3 -// Number of properties: 3 -// Group ID: 0x20 -// Start ID: 0x30 -// Default values: 0x00, 0x40, 0xA0, -// Descriptions: -// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. -// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. -// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. -*/ -#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x66, 0xA0 - -/* -// Set properties: RF_MODEM_AGC_CONTROL_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x35 -// Default values: 0xE0, -// Descriptions: -// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. -*/ -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0 - -/* -// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x38 -// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, -// Descriptions: -// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. -// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. -// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. -// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. -// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. -// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector. -// MODEM_OOK_CNT1 - OOK control. -// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. -*/ -#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x11, 0x11, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 - -/* -// Set properties: RF_MODEM_RAW_CONTROL_5 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x45 -// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, -// Descriptions: -// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. -// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. -// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. -// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. -// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. -*/ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x85, 0x01, 0x00 - -/* -// Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 -// Number of properties: 4 -// Group ID: 0x20 -// Start ID: 0x4B -// Default values: 0x0C, 0x01, 0x00, 0x40, -// Descriptions: -// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold. -// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). -// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. -// MODEM_RSSI_COMP - RSSI compensation value. -*/ -#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40 - -/* -// Set properties: RF_MODEM_RAW_SEARCH2_2 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x50 -// Default values: 0x00, 0x08, -// Descriptions: -// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. -// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. -*/ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 - -/* -// Set properties: RF_MODEM_SPIKE_DET_2 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x54 -// Default values: 0x00, 0x00, -// Descriptions: -// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. -// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. -*/ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 - -/* -// Set properties: RF_MODEM_RSSI_MUTE_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x57 -// Default values: 0x00, -// Descriptions: -// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts. -*/ -#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00 - -/* -// Set properties: RF_MODEM_DSA_CTRL1_5 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x5B -// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, -// Descriptions: -// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm. -// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config -// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. -*/ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x00 -// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x0C -// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00, 0x7E, 0x64, 0x1B, 0xBA, 0x58, 0x0B - -/* -// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x18 -// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, -// Descriptions: -// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xDD, 0xCE, 0xD6, 0xE6, 0xF6, 0x00, 0x03, 0x03, 0x15, 0xF0, 0x3F, 0x00 - -/* -// Set properties: RF_PA_TC_1 -// Number of properties: 1 -// Group ID: 0x22 -// Start ID: 0x03 -// Default values: 0x5D, -// Descriptions: -// PA_TC - Configuration of PA ramping parameters. -*/ -#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x00 - -/* -// Set properties: RF_SYNTH_PFDCP_CPFF_7 -// Number of properties: 7 -// Group ID: 0x23 -// Start ID: 0x00 -// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, -// Descriptions: -// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. -// SYNTH_PFDCP_CPINT - Integration charge pump current selection. -// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. -// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. -// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. -// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. -// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. -*/ -#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 - -/* -// Set properties: RF_FREQ_CONTROL_INTE_8 -// Number of properties: 8 -// Group ID: 0x40 -// Start ID: 0x00 -// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, -// Descriptions: -// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. -// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. -// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. -*/ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3B, 0x08, 0x80, 0x00, 0x22, 0x22, 0x20, 0xFF - -/* -// Command: RF_START_RX -// Description: Switches to RX state and starts reception of a packet. -*/ -#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - -/* -// Command: RF_IRCAL -// Description: Image rejection calibration. -*/ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 - -/* -// Command: RF_IRCAL_1 -// Description: Image rejection calibration. -*/ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 - -/* -// Set properties: RF_GLOBAL_CLK_CFG_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x01 -// Default values: 0x00, -// Descriptions: -// GLOBAL_CLK_CFG - Clock configuration options. -*/ -#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00 - -/* -// Set properties: RF_GLOBAL_CONFIG_1_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x03 -// Default values: 0x20, -// Descriptions: -// GLOBAL_CONFIG - Global configuration settings. -*/ -#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20 - -/* -// Set properties: RF_INT_CTL_ENABLE_1 -// Number of properties: 1 -// Group ID: 0x01 -// Start ID: 0x00 -// Default values: 0x04, -// Descriptions: -// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. -*/ -#define RF_INT_CTL_ENABLE_1 0x11, 0x01, 0x01, 0x00, 0x00 - -/* -// Set properties: RF_FRR_CTL_A_MODE_4 -// Number of properties: 4 -// Group ID: 0x02 -// Start ID: 0x00 -// Default values: 0x01, 0x02, 0x09, 0x00, -// Descriptions: -// FRR_CTL_A_MODE - Fast Response Register A Configuration. -// FRR_CTL_B_MODE - Fast Response Register B Configuration. -// FRR_CTL_C_MODE - Fast Response Register C Configuration. -// FRR_CTL_D_MODE - Fast Response Register D Configuration. -*/ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 - -/* -// Set properties: RF_PREAMBLE_CONFIG_STD_1_1 -// Number of properties: 1 -// Group ID: 0x10 -// Start ID: 0x01 -// Default values: 0x14, -// Descriptions: -// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. -*/ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 - -/* -// Set properties: RF_PKT_CONFIG1_1 -// Number of properties: 1 -// Group ID: 0x12 -// Start ID: 0x06 -// Default values: 0x00, -// Descriptions: -// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet. -*/ -#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x40 - -/* -// Set properties: RF_MODEM_MOD_TYPE_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x00 -// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, -// Descriptions: -// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. -// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. -// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. -// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. -// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x03, 0xE8, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x00 - -/* -// Set properties: RF_MODEM_FREQ_DEV_0_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x0C -// Default values: 0xD3, -// Descriptions: -// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x23 - -/* -// Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x18 -// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, -// Descriptions: -// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. -// MODEM_MDM_CTRL - MDM control. -// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. -// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). -// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections. -// MODEM_IFPKD_THRESHOLDS - -// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -*/ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x80, 0x0A, 0x03, 0xC0, 0x00, 0x0A, 0x10, 0x14, 0xF9, 0x0C, 0x35 - -/* -// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x24 -// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, -// Descriptions: -// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GEAR - RX BCR loop gear control. -// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. -// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls. -// MODEM_AFC_GEAR - RX AFC loop gear control. -// MODEM_AFC_WAIT - RX AFC loop wait time control. -// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -*/ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x00, 0x29, 0xF1, 0x00, 0x15, 0x02, 0xC2, 0x08, 0x04, 0x23, 0x00, 0x01 - -/* -// Set properties: RF_MODEM_AFC_LIMITER_1_3_1 -// Number of properties: 3 -// Group ID: 0x20 -// Start ID: 0x30 -// Default values: 0x00, 0x40, 0xA0, -// Descriptions: -// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. -// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. -// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. -*/ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0xA7, 0x9D, 0x80 - -/* -// Set properties: RF_MODEM_AGC_CONTROL_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x35 -// Default values: 0xE0, -// Descriptions: -// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. -*/ -#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0 - -/* -// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x38 -// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, -// Descriptions: -// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. -// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. -// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. -// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. -// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. -// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector. -// MODEM_OOK_CNT1 - OOK control. -// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. -*/ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0xFF, 0xFF, 0x80, 0x02, 0xFF, 0xFF, 0x00, 0x2B, 0x0C, 0xA4, 0x22 - -/* -// Set properties: RF_MODEM_RAW_CONTROL_10 -// Number of properties: 10 -// Group ID: 0x20 -// Start ID: 0x45 -// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, -// Descriptions: -// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. -// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. -// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. -// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. -// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. -// MODEM_RSSI_THRESH - Configures the RSSI threshold. -// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold. -// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). -// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. -// MODEM_RSSI_COMP - RSSI compensation value. -*/ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x81, 0x00, 0x1A, 0x01, 0x00, 0xFF, 0x06, 0x00, 0x10, 0x40 - -/* -// Set properties: RF_MODEM_RAW_SEARCH2_2_1 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x50 -// Default values: 0x00, 0x08, -// Descriptions: -// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. -// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. -*/ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 - -/* -// Set properties: RF_MODEM_SPIKE_DET_2_1 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x54 -// Default values: 0x00, 0x00, -// Descriptions: -// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. -// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. -*/ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 - -/* -// Set properties: RF_MODEM_RSSI_MUTE_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x57 -// Default values: 0x00, -// Descriptions: -// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts. -*/ -#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00 - -/* -// Set properties: RF_MODEM_DSA_CTRL1_5_1 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x5B -// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, -// Descriptions: -// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm. -// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config -// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. -*/ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x0B, 0x78, 0x20 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x00 -// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x0C -// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9 - -/* -// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x18 -// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, -// Descriptions: -// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F - -/* -// Set properties: RF_PA_TC_1_1 -// Number of properties: 1 -// Group ID: 0x22 -// Start ID: 0x03 -// Default values: 0x5D, -// Descriptions: -// PA_TC - Configuration of PA ramping parameters. -*/ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x00 - -/* -// Set properties: RF_SYNTH_PFDCP_CPFF_7_1 -// Number of properties: 7 -// Group ID: 0x23 -// Start ID: 0x00 -// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, -// Descriptions: -// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. -// SYNTH_PFDCP_CPINT - Integration charge pump current selection. -// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. -// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. -// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. -// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. -// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. -*/ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 - -/* -// Set properties: RF_FREQ_CONTROL_INTE_8_1 -// Number of properties: 8 -// Group ID: 0x40 -// Start ID: 0x00 -// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, -// Descriptions: -// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. -// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. -// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. -*/ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x3C, 0x08, 0x00, 0x00, 0x22, 0x22, 0x20, 0xFF - - -// AUTOMATICALLY GENERATED CODE! -// DO NOT EDIT/MODIFY BELOW THIS LINE! -// -------------------------------------------- -// 0x07, RF_POWER_UP, \ - -//#ifndef FIRMWARE_LOAD_COMPILE -#define RADIO_CONFIGURATION_DATA_ARRAY { \ - 0x08, RF_GPIO_PIN_CFG, \ - 0x05, RF_GLOBAL_XO_TUNE_1, \ - 0x05, RF_GLOBAL_CONFIG_1, \ - 0x05, RF_PREAMBLE_CONFIG_1, \ - 0x10, RF_MODEM_MOD_TYPE_12, \ - 0x05, RF_MODEM_FREQ_DEV_0_1, \ - 0x10, RF_MODEM_TX_RAMP_DELAY_12, \ - 0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \ - 0x07, RF_MODEM_AFC_LIMITER_1_3, \ - 0x05, RF_MODEM_AGC_CONTROL_1, \ - 0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \ - 0x09, RF_MODEM_RAW_CONTROL_5, \ - 0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \ - 0x06, RF_MODEM_RAW_SEARCH2_2, \ - 0x06, RF_MODEM_SPIKE_DET_2, \ - 0x05, RF_MODEM_RSSI_MUTE_1, \ - 0x09, RF_MODEM_DSA_CTRL1_5, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \ - 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \ - 0x05, RF_PA_TC_1, \ - 0x0B, RF_SYNTH_PFDCP_CPFF_7, \ - 0x0C, RF_FREQ_CONTROL_INTE_8, \ - 0x08, RF_START_RX, \ - 0x05, RF_IRCAL, \ - 0x05, RF_IRCAL_1, \ - 0x05, RF_GLOBAL_CLK_CFG_1, \ - 0x05, RF_GLOBAL_CONFIG_1_1, \ - 0x05, RF_INT_CTL_ENABLE_1, \ - 0x08, RF_FRR_CTL_A_MODE_4, \ - 0x05, RF_PREAMBLE_CONFIG_STD_1_1, \ - 0x05, RF_PKT_CONFIG1_1, \ - 0x10, RF_MODEM_MOD_TYPE_12_1, \ - 0x05, RF_MODEM_FREQ_DEV_0_1_1, \ - 0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \ - 0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \ - 0x07, RF_MODEM_AFC_LIMITER_1_3_1, \ - 0x05, RF_MODEM_AGC_CONTROL_1_1, \ - 0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \ - 0x0E, RF_MODEM_RAW_CONTROL_10, \ - 0x06, RF_MODEM_RAW_SEARCH2_2_1, \ - 0x06, RF_MODEM_SPIKE_DET_2_1, \ - 0x05, RF_MODEM_RSSI_MUTE_1_1, \ - 0x09, RF_MODEM_DSA_CTRL1_5_1, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \ - 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \ - 0x05, RF_PA_TC_1_1, \ - 0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \ - 0x0C, RF_FREQ_CONTROL_INTE_8_1, \ - 0x00 \ - } -//#else -//#define RADIO_CONFIGURATION_DATA_ARRAY { 0 } -//#endif - -// DEFAULT VALUES FOR CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10 -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01 -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000 - -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { } - -#ifndef RADIO_CONFIGURATION_DATA_ARRAY -#error "This property must be defined!" -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT -#endif - -#define RADIO_CONFIGURATION_DATA { \ - Radio_Configuration_Data_Array, \ - RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \ - RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \ - RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \ - RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \ - } - -//#endif /* RADIO_CONFIG_H_ */ diff --git a/main.c b/main.c index fffc3d0..78dcd24 100644 --- a/main.c +++ b/main.c @@ -2883,7 +2883,7 @@ int main(void) // menu_mode_cb(setting.mode,0); // } redraw_frame(); -#if 1 +#if 0 set_mode(M_HIGH); set_sweep_frequency(ST_STOP, (uint32_t) 30000000); sweep(false); diff --git a/nanovna.h b/nanovna.h index 58fa27d..1b9c988 100644 --- a/nanovna.h +++ b/nanovna.h @@ -45,6 +45,11 @@ //#define __USE_SERIAL_CONSOLE__ // Enable serial I/O connection (need enable HAL_USE_SERIAL as TRUE in halconf.h) #define __SI4463__ #define __SI4468__ + +#define DEFAULT_IF 978000000 +#define DEFAULT_SPUR_IF 978000000 +#define DEFAULT_MAX_FREQ 800000000 + /* * main.c */ diff --git a/radio_config_Si4468_100kHz_fast.h b/radio_config_Si4468_100kHz.h similarity index 98% rename from radio_config_Si4468_100kHz_fast.h rename to radio_config_Si4468_100kHz.h index 2c8f90f..7b7fb7f 100644 --- a/radio_config_Si4468_100kHz_fast.h +++ b/radio_config_Si4468_100kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 200000 Fdev(Hz): 1 RXBW(Hz): 100000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0x00, 0x20, 0x00, 0xF9, 0x00, 0x41 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x20, 0x00, 0xF9, 0x00, 0x41 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xE0, 0x7E, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0F, 0xC1 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0xE0, 0x7E, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x07, 0xE0 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_10kHz_fast.h b/radio_config_Si4468_10kHz.h similarity index 98% rename from radio_config_Si4468_10kHz_fast.h rename to radio_config_Si4468_10kHz.h index 720178f..e0540cc 100644 --- a/radio_config_Si4468_10kHz_fast.h +++ b/radio_config_Si4468_10kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 20000 Fdev(Hz): 1 RXBW(Hz): 10000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0x30, 0x20, 0x00, 0xF9, 0x00, 0x51 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x30, 0x20, 0x00, 0xF9, 0x00, 0x51 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x4D, 0x32, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0xCA +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x06, 0x4D, 0x32, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x65 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_1kHz_fast.h b/radio_config_Si4468_1kHz.h similarity index 98% rename from radio_config_Si4468_1kHz_fast.h rename to radio_config_Si4468_1kHz.h index fef2041..322a513 100644 --- a/radio_config_Si4468_1kHz_fast.h +++ b/radio_config_Si4468_1kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 2000 Fdev(Hz): 1 RXBW(Hz): 1000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xF0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x0A /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_200Hz_fast.h b/radio_config_Si4468_200Hz.h similarity index 97% rename from radio_config_Si4468_200Hz_fast.h rename to radio_config_Si4468_200Hz.h index c20e1c7..f3926c1 100644 --- a/radio_config_Si4468_200Hz_fast.h +++ b/radio_config_Si4468_200Hz.h @@ -20,14 +20,14 @@ // INPUT DATA /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 200 Fdev(Hz): 1 RXBW(Hz): 200 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// MOD_type: 2 Rsymb(sps): 400 Fdev(Hz): 1 RXBW(Hz): 200 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz -// # WB filter 9 (BW = 0.22 kHz); NB-filter 9 (BW = 0.22 kHz) +// # WB filter 15 (BW = 0.23 kHz); NB-filter 15 (BW = 0.23 kHz) // -// Modulation index: 0.01 +// Modulation index: 0.005 */ @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x07, 0xD0, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x0F, 0xA0, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xF0, 0x10, 0x74, 0xF9, 0x00, 0x55 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xF0, 0x10, 0x54, 0xF9, 0x00, 0x55 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0xFC, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0x85, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x13, 0x13, 0x80, 0x02, 0x00, 0xA4, 0x00, 0x28, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x13, 0x13, 0x80, 0x02, 0x00, 0x52, 0x00, 0x28, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x06, 0x10, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x02, 0x01, 0x00, 0xFF, 0x06, 0x10, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F, 0x0C, 0x01, 0xE4, 0xB9, 0x86, 0x55 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA0, 0x97, 0x8A, 0x79, 0x66 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x2B, 0x0B, 0xF8, 0xEF, 0xEF, 0xF2, 0xF8, 0xFC, 0x05, 0x00, 0xFF, 0x0F +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x52, 0x3F, 0x2E, 0x1F, 0x14, 0x0B, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00 /* // Set properties: RF_PA_TC_1_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_300kHz.h b/radio_config_Si4468_300kHz.h index 33891c9..297a4cf 100644 --- a/radio_config_Si4468_300kHz.h +++ b/radio_config_Si4468_300kHz.h @@ -20,14 +20,14 @@ // INPUT DATA /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 100 Fdev(Hz): 1 RXBW(Hz): 300000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// MOD_type: 2 Rsymb(sps): 433333 Fdev(Hz): 1 RXBW(Hz): 300000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // +// # RX IF frequency is -406250 Hz +// # WB filter 10 (BW = 306.11 kHz); NB-filter 10 (BW = 306.11 kHz) // -// -// -// Modulation index: 0.02 +// Modulation index: 0 */ @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -507,7 +507,7 @@ // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x03, 0xE8, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 +#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x42, 0x1F, 0x12, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 /* // Set properties: RF_MODEM_FREQ_DEV_0_1_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xF0, 0x10, 0x74, 0xF9, 0x00, 0xA9 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x03, 0x06, 0x55, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x01 +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x08, 0x89 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x02, 0xAE, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0x91, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -608,7 +608,7 @@ // MODEM_OOK_CNT1 - OOK control. // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. */ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x25, 0x25, 0x80, 0x02, 0x01, 0x48, 0x00, 0x29, 0x0C, 0xA4, 0x23 +#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x21, 0x09, 0x09, 0x80, 0x02, 0x00, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 /* // Set properties: RF_MODEM_RAW_CONTROL_10 @@ -628,7 +628,7 @@ // MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. // MODEM_RSSI_COMP - RSSI compensation value. */ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x06, 0x10, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x06, 0x10, 0x10, 0x40 /* // Set properties: RF_MODEM_RAW_SEARCH2_2_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -678,7 +678,7 @@ // MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config // MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. */ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x02, 0x78, 0x20 +#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x00, 0x78, 0x20 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 @@ -700,7 +700,7 @@ // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0x5B, 0x47, 0x0F, 0xC0, 0x6D, 0x25, 0xF4, 0xDB, 0xD6, 0xDF, 0xEC, 0xF7 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xF9, 0xF0, 0xD7, 0xB1, 0x86, 0x59, 0x33, 0x15, 0x01, 0xF7, 0xF4, 0xF6 /* // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 @@ -722,7 +722,7 @@ // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xFE, 0x01, 0x15, 0xF0, 0xFF, 0x03, 0x5B, 0x47, 0x0F, 0xC0, 0x6D, 0x25 +#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xF9, 0xFC, 0x00, 0x00, 0xFC, 0x0F, 0xF9, 0xF0, 0xD7, 0xB1, 0x86, 0x59 /* // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 @@ -744,7 +744,7 @@ // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. */ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0xF4, 0xDB, 0xD6, 0xDF, 0xEC, 0xF7, 0xFE, 0x01, 0x15, 0xF0, 0xFF, 0x03 +#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x33, 0x15, 0x01, 0xF7, 0xF4, 0xF6, 0xF9, 0xFC, 0x00, 0x00, 0xFC, 0x0F /* // Set properties: RF_PA_TC_1_1 @@ -755,7 +755,7 @@ // Descriptions: // PA_TC - Configuration of PA ramping parameters. */ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x1D +#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5D /* // Set properties: RF_SYNTH_PFDCP_CPFF_7_1 @@ -772,7 +772,7 @@ // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. */ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 +#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03 /* // Set properties: RF_FREQ_CONTROL_INTE_8_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_300kHz_fast.h b/radio_config_Si4468_300kHz_fast.h deleted file mode 100644 index 079a4a7..0000000 --- a/radio_config_Si4468_300kHz_fast.h +++ /dev/null @@ -1,902 +0,0 @@ -/*! @file radio_config.h - * @brief This file contains the automatically generated - * configurations. - * - * @n WDS GUI Version: 3.2.11.0 - * @n Device: Si4468 Rev.: A2 - * - * @b COPYRIGHT - * @n Silicon Laboratories Confidential - * @n Copyright 2017 Silicon Laboratories, Inc. - * @n http://www.silabs.com - */ - -#ifndef RADIO_CONFIG_H_ -#define RADIO_CONFIG_H_ - -// USER DEFINED PARAMETERS -// Define your own parameters here - -// INPUT DATA -/* -// Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 -// MOD_type: 2 Rsymb(sps): 433333 Fdev(Hz): 1 RXBW(Hz): 300000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 -// API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 -// -// # RX IF frequency is -406250 Hz -// # WB filter 10 (BW = 306.11 kHz); NB-filter 10 (BW = 306.11 kHz) -// -// Modulation index: 0 -*/ - - -// CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 26000000L -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03 -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000 - - -// CONFIGURATION COMMANDS - -/* -// Command: RF_POWER_UP -// Description: Command to power-up the device and select the operational mode and functionality. -*/ -#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80 - -/* -// Command: RF_GPIO_PIN_CFG -// Description: Configures the GPIO pins. -*/ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 - -/* -// Set properties: RF_GLOBAL_XO_TUNE_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x00 -// Default values: 0x40, -// Descriptions: -// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator. -*/ -#define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52 - -/* -// Set properties: RF_GLOBAL_CONFIG_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x03 -// Default values: 0x20, -// Descriptions: -// GLOBAL_CONFIG - Global configuration settings. -*/ -#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x20 - -/* -// Set properties: RF_PREAMBLE_CONFIG_1 -// Number of properties: 1 -// Group ID: 0x10 -// Start ID: 0x04 -// Default values: 0x21, -// Descriptions: -// PREAMBLE_CONFIG - General configuration bits for the Preamble field. -*/ -#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x21 - -/* -// Set properties: RF_MODEM_MOD_TYPE_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x00 -// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, -// Descriptions: -// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. -// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. -// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. -// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. -// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x0B, 0x00, 0x07, 0x02, 0x71, 0x00, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x00 - -/* -// Set properties: RF_MODEM_FREQ_DEV_0_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x0C -// Default values: 0xD3, -// Descriptions: -// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 - -/* -// Set properties: RF_MODEM_TX_RAMP_DELAY_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x18 -// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, -// Descriptions: -// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. -// MODEM_MDM_CTRL - MDM control. -// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. -// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). -// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections. -// MODEM_IFPKD_THRESHOLDS - -// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -*/ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 - -/* -// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x24 -// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, -// Descriptions: -// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GEAR - RX BCR loop gear control. -// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. -// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls. -// MODEM_AFC_GEAR - RX AFC loop gear control. -// MODEM_AFC_WAIT - RX AFC loop wait time control. -// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -*/ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 - -/* -// Set properties: RF_MODEM_AFC_LIMITER_1_3 -// Number of properties: 3 -// Group ID: 0x20 -// Start ID: 0x30 -// Default values: 0x00, 0x40, 0xA0, -// Descriptions: -// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. -// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. -// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. -*/ -#define RF_MODEM_AFC_LIMITER_1_3 0x11, 0x20, 0x03, 0x30, 0x01, 0x7C, 0xA0 - -/* -// Set properties: RF_MODEM_AGC_CONTROL_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x35 -// Default values: 0xE0, -// Descriptions: -// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. -*/ -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE0 - -/* -// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x38 -// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, -// Descriptions: -// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. -// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. -// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. -// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. -// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. -// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector. -// MODEM_OOK_CNT1 - OOK control. -// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. -*/ -#define RF_MODEM_AGC_WINDOW_SIZE_12 0x11, 0x20, 0x0C, 0x38, 0x11, 0x0F, 0x0F, 0x80, 0x1A, 0x20, 0x00, 0x00, 0x28, 0x0C, 0xA4, 0x23 - -/* -// Set properties: RF_MODEM_RAW_CONTROL_5 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x45 -// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, -// Descriptions: -// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. -// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. -// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. -// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. -// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. -*/ -#define RF_MODEM_RAW_CONTROL_5 0x11, 0x20, 0x05, 0x45, 0x03, 0x00, 0x99, 0x01, 0x00 - -/* -// Set properties: RF_MODEM_RSSI_JUMP_THRESH_4 -// Number of properties: 4 -// Group ID: 0x20 -// Start ID: 0x4B -// Default values: 0x0C, 0x01, 0x00, 0x40, -// Descriptions: -// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold. -// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). -// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. -// MODEM_RSSI_COMP - RSSI compensation value. -*/ -#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x40 - -/* -// Set properties: RF_MODEM_RAW_SEARCH2_2 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x50 -// Default values: 0x00, 0x08, -// Descriptions: -// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. -// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. -*/ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A - -/* -// Set properties: RF_MODEM_SPIKE_DET_2 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x54 -// Default values: 0x00, 0x00, -// Descriptions: -// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. -// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. -*/ -#define RF_MODEM_SPIKE_DET_2 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 - -/* -// Set properties: RF_MODEM_RSSI_MUTE_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x57 -// Default values: 0x00, -// Descriptions: -// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts. -*/ -#define RF_MODEM_RSSI_MUTE_1 0x11, 0x20, 0x01, 0x57, 0x00 - -/* -// Set properties: RF_MODEM_DSA_CTRL1_5 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x5B -// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, -// Descriptions: -// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm. -// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config -// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. -*/ -#define RF_MODEM_DSA_CTRL1_5 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x04, 0x78, 0x20 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x00 -// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x0C -// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1 - -/* -// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x18 -// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, -// Descriptions: -// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00 - -/* -// Set properties: RF_PA_TC_1 -// Number of properties: 1 -// Group ID: 0x22 -// Start ID: 0x03 -// Default values: 0x5D, -// Descriptions: -// PA_TC - Configuration of PA ramping parameters. -*/ -#define RF_PA_TC_1 0x11, 0x22, 0x01, 0x03, 0x1D - -/* -// Set properties: RF_SYNTH_PFDCP_CPFF_7 -// Number of properties: 7 -// Group ID: 0x23 -// Start ID: 0x00 -// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, -// Descriptions: -// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. -// SYNTH_PFDCP_CPINT - Integration charge pump current selection. -// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. -// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. -// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. -// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. -// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. -*/ -#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 - -/* -// Set properties: RF_FREQ_CONTROL_INTE_8 -// Number of properties: 8 -// Group ID: 0x40 -// Start ID: 0x00 -// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, -// Descriptions: -// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. -// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. -// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. -*/ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE - -/* -// Command: RF_START_RX -// Description: Switches to RX state and starts reception of a packet. -*/ -#define RF_START_RX 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 - -/* -// Command: RF_IRCAL -// Description: Image rejection calibration. -*/ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 - -/* -// Command: RF_IRCAL_1 -// Description: Image rejection calibration. -*/ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 - -/* -// Set properties: RF_GLOBAL_CLK_CFG_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x01 -// Default values: 0x00, -// Descriptions: -// GLOBAL_CLK_CFG - Clock configuration options. -*/ -#define RF_GLOBAL_CLK_CFG_1 0x11, 0x00, 0x01, 0x01, 0x00 - -/* -// Set properties: RF_GLOBAL_CONFIG_1_1 -// Number of properties: 1 -// Group ID: 0x00 -// Start ID: 0x03 -// Default values: 0x20, -// Descriptions: -// GLOBAL_CONFIG - Global configuration settings. -*/ -#define RF_GLOBAL_CONFIG_1_1 0x11, 0x00, 0x01, 0x03, 0x20 - -/* -// Set properties: RF_INT_CTL_ENABLE_1 -// Number of properties: 1 -// Group ID: 0x01 -// Start ID: 0x00 -// Default values: 0x04, -// Descriptions: -// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. -*/ -#define RF_INT_CTL_ENABLE_1 0x11, 0x01, 0x01, 0x00, 0x00 - -/* -// Set properties: RF_FRR_CTL_A_MODE_4 -// Number of properties: 4 -// Group ID: 0x02 -// Start ID: 0x00 -// Default values: 0x01, 0x02, 0x09, 0x00, -// Descriptions: -// FRR_CTL_A_MODE - Fast Response Register A Configuration. -// FRR_CTL_B_MODE - Fast Response Register B Configuration. -// FRR_CTL_C_MODE - Fast Response Register C Configuration. -// FRR_CTL_D_MODE - Fast Response Register D Configuration. -*/ -#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x05, 0x01, 0x07, 0x09 - -/* -// Set properties: RF_PREAMBLE_CONFIG_STD_1_1 -// Number of properties: 1 -// Group ID: 0x10 -// Start ID: 0x01 -// Default values: 0x14, -// Descriptions: -// PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. -*/ -#define RF_PREAMBLE_CONFIG_STD_1_1 0x11, 0x10, 0x01, 0x01, 0x88 - -/* -// Set properties: RF_PKT_CONFIG1_1 -// Number of properties: 1 -// Group ID: 0x12 -// Start ID: 0x06 -// Default values: 0x00, -// Descriptions: -// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet. -*/ -#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x40 - -/* -// Set properties: RF_MODEM_MOD_TYPE_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x00 -// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, -// Descriptions: -// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. -// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. -// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. -// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate -// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. -// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. -// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_MOD_TYPE_12_1 0x11, 0x20, 0x0C, 0x00, 0x0A, 0x00, 0x07, 0x42, 0x1F, 0x12, 0x01, 0x8C, 0xBA, 0x80, 0x00, 0x00 - -/* -// Set properties: RF_MODEM_FREQ_DEV_0_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x0C -// Default values: 0xD3, -// Descriptions: -// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. -*/ -#define RF_MODEM_FREQ_DEV_0_1_1 0x11, 0x20, 0x01, 0x0C, 0x00 - -/* -// Set properties: RF_MODEM_TX_RAMP_DELAY_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x18 -// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 0x00, 0x00, 0x00, 0x4B, -// Descriptions: -// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. -// MODEM_MDM_CTRL - MDM control. -// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. -// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). -// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). -// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. -// MODEM_DECIMATION_CFG2 - Specifies miscellaneous decimator filter selections. -// MODEM_IFPKD_THRESHOLDS - -// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). -*/ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C - -/* -// Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x24 -// Default values: 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 0x00, 0x00, 0x23, 0x83, 0x69, -// Descriptions: -// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). -// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. -// MODEM_BCR_GEAR - RX BCR loop gear control. -// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. -// MODEM_BCR_MISC0 - Miscellaneous RX BCR loop controls. -// MODEM_AFC_GEAR - RX AFC loop gear control. -// MODEM_AFC_WAIT - RX AFC loop wait time control. -// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. -*/ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0F, 0xFF - -/* -// Set properties: RF_MODEM_AFC_LIMITER_1_3_1 -// Number of properties: 3 -// Group ID: 0x20 -// Start ID: 0x30 -// Default values: 0x00, 0x40, 0xA0, -// Descriptions: -// MODEM_AFC_LIMITER_1 - Set the AFC limiter value. -// MODEM_AFC_LIMITER_0 - Set the AFC limiter value. -// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. -*/ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0x93, 0xA0 - -/* -// Set properties: RF_MODEM_AGC_CONTROL_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x35 -// Default values: 0xE0, -// Descriptions: -// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. -*/ -#define RF_MODEM_AGC_CONTROL_1_1 0x11, 0x20, 0x01, 0x35, 0xE0 - -/* -// Set properties: RF_MODEM_AGC_WINDOW_SIZE_12_1 -// Number of properties: 12 -// Group ID: 0x20 -// Start ID: 0x38 -// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 0x0C, 0xA4, 0x03, -// Descriptions: -// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. -// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. -// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. -// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. -// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. -// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. -// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. -// MODEM_OOK_BLOPK - Configures the slicing reference level of the OOK Peak Detector. -// MODEM_OOK_CNT1 - OOK control. -// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. -*/ -#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x21, 0x09, 0x09, 0x80, 0x02, 0x00, 0x00, 0x00, 0x27, 0x0C, 0xA4, 0x23 - -/* -// Set properties: RF_MODEM_RAW_CONTROL_10 -// Number of properties: 10 -// Group ID: 0x20 -// Start ID: 0x45 -// Default values: 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 0x00, 0x40, -// Descriptions: -// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. -// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. -// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. -// MODEM_ANT_DIV_MODE - Antenna diversity mode settings. -// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. -// MODEM_RSSI_THRESH - Configures the RSSI threshold. -// MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold. -// MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). -// MODEM_RSSI_CONTROL2 - RSSI Jump Detection control. -// MODEM_RSSI_COMP - RSSI compensation value. -*/ -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x06, 0x10, 0x10, 0x40 - -/* -// Set properties: RF_MODEM_RAW_SEARCH2_2_1 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x50 -// Default values: 0x00, 0x08, -// Descriptions: -// MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. -// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. -*/ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A - -/* -// Set properties: RF_MODEM_SPIKE_DET_2_1 -// Number of properties: 2 -// Group ID: 0x20 -// Start ID: 0x54 -// Default values: 0x00, 0x00, -// Descriptions: -// MODEM_SPIKE_DET - Configures the threshold for (G)FSK Spike Detection. -// MODEM_ONE_SHOT_AFC - Configures parameters for th e One Shot AFC function and for BCR timing/acquisition. -*/ -#define RF_MODEM_SPIKE_DET_2_1 0x11, 0x20, 0x02, 0x54, 0x03, 0x07 - -/* -// Set properties: RF_MODEM_RSSI_MUTE_1_1 -// Number of properties: 1 -// Group ID: 0x20 -// Start ID: 0x57 -// Default values: 0x00, -// Descriptions: -// MODEM_RSSI_MUTE - Configures muting of the RSSI to avoid false RSSI interrupts. -*/ -#define RF_MODEM_RSSI_MUTE_1_1 0x11, 0x20, 0x01, 0x57, 0x00 - -/* -// Set properties: RF_MODEM_DSA_CTRL1_5_1 -// Number of properties: 5 -// Group ID: 0x20 -// Start ID: 0x5B -// Default values: 0x00, 0x00, 0x00, 0x00, 0x00, -// Descriptions: -// MODEM_DSA_CTRL1 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_CTRL2 - Configures parameters for the Signal Arrival Detection circuit block and algorithm. -// MODEM_DSA_QUAL - Configures parameters for the Eye Opening qualification m ethod of the Signal Arrival Detection algorithm. -// MODEM_DSA_RSSI - Signal Arrival Detect RSSI Qualifier Config -// MODEM_DSA_MISC - Miscellaneous detection of signal arrival bits. -*/ -#define RF_MODEM_DSA_CTRL1_5_1 0x11, 0x20, 0x05, 0x5B, 0x40, 0x04, 0x00, 0x78, 0x20 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x00 -// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1 0x11, 0x21, 0x0C, 0x00, 0xF9, 0xF0, 0xD7, 0xB1, 0x86, 0x59, 0x33, 0x15, 0x01, 0xF7, 0xF4, 0xF6 - -/* -// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x0C -// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, -// Descriptions: -// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1 0x11, 0x21, 0x0C, 0x0C, 0xF9, 0xFC, 0x00, 0x00, 0xFC, 0x0F, 0xF9, 0xF0, 0xD7, 0xB1, 0x86, 0x59 - -/* -// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 -// Number of properties: 12 -// Group ID: 0x21 -// Start ID: 0x18 -// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, -// Descriptions: -// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. -// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. -*/ -#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1 0x11, 0x21, 0x0C, 0x18, 0x33, 0x15, 0x01, 0xF7, 0xF4, 0xF6, 0xF9, 0xFC, 0x00, 0x00, 0xFC, 0x0F - -/* -// Set properties: RF_PA_TC_1_1 -// Number of properties: 1 -// Group ID: 0x22 -// Start ID: 0x03 -// Default values: 0x5D, -// Descriptions: -// PA_TC - Configuration of PA ramping parameters. -*/ -#define RF_PA_TC_1_1 0x11, 0x22, 0x01, 0x03, 0x5D - -/* -// Set properties: RF_SYNTH_PFDCP_CPFF_7_1 -// Number of properties: 7 -// Group ID: 0x23 -// Start ID: 0x00 -// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, -// Descriptions: -// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. -// SYNTH_PFDCP_CPINT - Integration charge pump current selection. -// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. -// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. -// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. -// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. -// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. -*/ -#define RF_SYNTH_PFDCP_CPFF_7_1 0x11, 0x23, 0x07, 0x00, 0x01, 0x05, 0x0B, 0x05, 0x02, 0x00, 0x03 - -/* -// Set properties: RF_FREQ_CONTROL_INTE_8_1 -// Number of properties: 8 -// Group ID: 0x40 -// Start ID: 0x00 -// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, -// Descriptions: -// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. -// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. -// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. -// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. -// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. -*/ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE - - -// AUTOMATICALLY GENERATED CODE! -// DO NOT EDIT/MODIFY BELOW THIS LINE! -// -------------------------------------------- - -#ifndef FIRMWARE_LOAD_COMPILE -#define RADIO_CONFIGURATION_DATA_ARRAY { \ - 0x07, RF_POWER_UP, \ - 0x08, RF_GPIO_PIN_CFG, \ - 0x05, RF_GLOBAL_XO_TUNE_1, \ - 0x05, RF_GLOBAL_CONFIG_1, \ - 0x05, RF_PREAMBLE_CONFIG_1, \ - 0x10, RF_MODEM_MOD_TYPE_12, \ - 0x05, RF_MODEM_FREQ_DEV_0_1, \ - 0x10, RF_MODEM_TX_RAMP_DELAY_12, \ - 0x10, RF_MODEM_BCR_NCO_OFFSET_2_12, \ - 0x07, RF_MODEM_AFC_LIMITER_1_3, \ - 0x05, RF_MODEM_AGC_CONTROL_1, \ - 0x10, RF_MODEM_AGC_WINDOW_SIZE_12, \ - 0x09, RF_MODEM_RAW_CONTROL_5, \ - 0x08, RF_MODEM_RSSI_JUMP_THRESH_4, \ - 0x06, RF_MODEM_RAW_SEARCH2_2, \ - 0x06, RF_MODEM_SPIKE_DET_2, \ - 0x05, RF_MODEM_RSSI_MUTE_1, \ - 0x09, RF_MODEM_DSA_CTRL1_5, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \ - 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \ - 0x05, RF_PA_TC_1, \ - 0x0B, RF_SYNTH_PFDCP_CPFF_7, \ - 0x0C, RF_FREQ_CONTROL_INTE_8, \ - 0x08, RF_START_RX, \ - 0x05, RF_IRCAL, \ - 0x05, RF_IRCAL_1, \ - 0x05, RF_GLOBAL_CLK_CFG_1, \ - 0x05, RF_GLOBAL_CONFIG_1_1, \ - 0x05, RF_INT_CTL_ENABLE_1, \ - 0x08, RF_FRR_CTL_A_MODE_4, \ - 0x05, RF_PREAMBLE_CONFIG_STD_1_1, \ - 0x05, RF_PKT_CONFIG1_1, \ - 0x10, RF_MODEM_MOD_TYPE_12_1, \ - 0x05, RF_MODEM_FREQ_DEV_0_1_1, \ - 0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \ - 0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1, \ - 0x07, RF_MODEM_AFC_LIMITER_1_3_1, \ - 0x05, RF_MODEM_AGC_CONTROL_1_1, \ - 0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1, \ - 0x0E, RF_MODEM_RAW_CONTROL_10, \ - 0x06, RF_MODEM_RAW_SEARCH2_2_1, \ - 0x06, RF_MODEM_SPIKE_DET_2_1, \ - 0x05, RF_MODEM_RSSI_MUTE_1_1, \ - 0x09, RF_MODEM_DSA_CTRL1_5_1, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \ - 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \ - 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \ - 0x05, RF_PA_TC_1_1, \ - 0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \ - 0x0C, RF_FREQ_CONTROL_INTE_8_1, \ - 0x00 \ - } -#else -#define RADIO_CONFIGURATION_DATA_ARRAY { 0 } -#endif - -// DEFAULT VALUES FOR CONFIGURATION PARAMETERS -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10 -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01 -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000 - -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00 -#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { } - -#ifndef RADIO_CONFIGURATION_DATA_ARRAY -#error "This property must be defined!" -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ -#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER -#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH -#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP -#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT -#endif - -#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET -#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT -#endif - -#define RADIO_CONFIGURATION_DATA { \ - Radio_Configuration_Data_Array, \ - RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \ - RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \ - RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \ - RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \ - } - -#endif /* RADIO_CONFIG_H_ */ diff --git a/radio_config_Si4468_30kHz_fast.h b/radio_config_Si4468_30kHz.h similarity index 98% rename from radio_config_Si4468_30kHz_fast.h rename to radio_config_Si4468_30kHz.h index 2eebf3d..4c0bd2c 100644 --- a/radio_config_Si4468_30kHz_fast.h +++ b/radio_config_Si4468_30kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 60000 Fdev(Hz): 1 RXBW(Hz): 30000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0x10, 0x10, 0x00, 0xF9, 0x00, 0x48 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x10, 0x10, 0x00, 0xF9, 0x00, 0x48 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x16, 0xD8, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x02, 0x5D +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x16, 0xD8, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x01, 0x2E /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0x7C, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x00, 0x7D, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_3kHz_fast.h b/radio_config_Si4468_3kHz.h similarity index 98% rename from radio_config_Si4468_3kHz_fast.h rename to radio_config_Si4468_3kHz.h index 4f16155..27d0fe9 100644 --- a/radio_config_Si4468_3kHz_fast.h +++ b/radio_config_Si4468_3kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 6000 Fdev(Hz): 1 RXBW(Hz): 3000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x20, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x20, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x3C +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x1E /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_850kHz_fast.h b/radio_config_Si4468_850kHz.h similarity index 98% rename from radio_config_Si4468_850kHz_fast.h rename to radio_config_Si4468_850kHz.h index aecc831..6e9823d 100644 --- a/radio_config_Si4468_850kHz_fast.h +++ b/radio_config_Si4468_850kHz.h @@ -21,7 +21,7 @@ /* // Crys_freq(Hz): 26000000 Crys_tol(ppm): 1 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 // MOD_type: 2 Rsymb(sps): 433333 Fdev(Hz): 1 RXBW(Hz): 850000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 -// RF Freq.(MHz): 433.6 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 +// RF Freq.(MHz): 978 API_TC: 29 fhst: 250000 inputBW: 1 BERT: 1 RAW_dout: 0 D_source: 1 Hi_pfm_div: 1 // API_ARR_Det_en: 0 Fdev_error: 0 API_ETSI: 2 // // # RX IF frequency is -406250 Hz @@ -51,7 +51,7 @@ // Command: RF_GPIO_PIN_CFG // Description: Configures the GPIO pins. */ -#define RF_GPIO_PIN_CFG 0x13, 0x21, 0x0C, 0x0A, 0x08, 0x00, 0x00, 0x00 +#define RF_GPIO_PIN_CFG 0x13, 0x08, 0x08, 0x0A, 0x21, 0x00, 0x00, 0x00 /* // Set properties: RF_GLOBAL_XO_TUNE_1 @@ -117,7 +117,7 @@ // Descriptions: // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. */ -#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x51 +#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x28 /* // Set properties: RF_MODEM_TX_RAMP_DELAY_12 @@ -139,7 +139,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 +#define RF_MODEM_TX_RAMP_DELAY_12 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0xB0, 0x10, 0x0C, 0xF9, 0x00, 0x44 /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12 @@ -161,7 +161,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x28 +#define RF_MODEM_BCR_NCO_OFFSET_2_12 0x11, 0x20, 0x0C, 0x24, 0x07, 0x8F, 0xD5, 0x00, 0x00, 0x02, 0xC0, 0x08, 0x00, 0x12, 0x00, 0x14 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3 @@ -248,7 +248,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2 @@ -398,7 +398,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x43, 0x09, 0x00, 0x00, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x80, 0x00, 0x27, 0x62, 0x20, 0xFF /* // Command: RF_START_RX @@ -410,13 +410,13 @@ // Command: RF_IRCAL // Description: Image rejection calibration. */ -#define RF_IRCAL 0x17, 0x56, 0x10, 0xCA, 0xF0 +#define RF_IRCAL 0x17, 0x56, 0x10, 0xFA, 0xF0 /* // Command: RF_IRCAL_1 // Description: Image rejection calibration. */ -#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xCA, 0xF0 +#define RF_IRCAL_1 0x17, 0x13, 0x10, 0xFA, 0xF0 /* // Set properties: RF_GLOBAL_CLK_CFG_1 @@ -540,7 +540,7 @@ // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). */ -#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0x80, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C +#define RF_MODEM_TX_RAMP_DELAY_12_1 0x11, 0x20, 0x0C, 0x18, 0x01, 0x00, 0x0A, 0x03, 0xC0, 0x00, 0x00, 0x30, 0x00, 0xF9, 0x00, 0x3C /* // Set properties: RF_MODEM_BCR_NCO_OFFSET_2_12_1 @@ -562,7 +562,7 @@ // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. */ -#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x0F, 0xFF +#define RF_MODEM_BCR_NCO_OFFSET_2_12_1 0x11, 0x20, 0x0C, 0x24, 0x08, 0x88, 0x88, 0x07, 0xFF, 0x02, 0xC0, 0x08, 0x00, 0x23, 0x08, 0x89 /* // Set properties: RF_MODEM_AFC_LIMITER_1_3_1 @@ -575,7 +575,7 @@ // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. */ -#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x97, 0xA0 +#define RF_MODEM_AFC_LIMITER_1_3_1 0x11, 0x20, 0x03, 0x30, 0x01, 0x92, 0xA0 /* // Set properties: RF_MODEM_AGC_CONTROL_1_1 @@ -640,7 +640,7 @@ // MODEM_RAW_SEARCH2 - Defines and controls the search period length for the Moving Average and Min-Max detectors. // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ -#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x0A +#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x08 /* // Set properties: RF_MODEM_SPIKE_DET_2_1 @@ -790,7 +790,7 @@ // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ -#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE +#define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x4A, 0x09, 0xD8, 0x9D, 0x27, 0x62, 0x20, 0xFF // AUTOMATICALLY GENERATED CODE! diff --git a/radio_config_Si4468_short.h b/radio_config_Si4468_short.h index d9e7a01..286b42c 100644 --- a/radio_config_Si4468_short.h +++ b/radio_config_Si4468_short.h @@ -1,5 +1,7 @@ +#if 1 #undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 +#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x06, 0x18, 0x10, 0x40 + #undef RF_MODEM_AGC_CONTROL_1 #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase @@ -25,4 +27,6 @@ 0x0B, RF_SYNTH_PFDCP_CPFF_7_1, \ /* 0x0C, RF_FREQ_CONTROL_INTE_8_1, */ \ 0x00 \ - } \ No newline at end of file + } + #endif + \ No newline at end of file diff --git a/sa_core.c b/sa_core.c index 70813c9..5c5ed40 100644 --- a/sa_core.c +++ b/sa_core.c @@ -68,7 +68,7 @@ void update_min_max_freq(void) case M_LOW: minFreq = 0; if (config.frequency_IF2 == 0) - maxFreq = 350000000; + maxFreq = DEFAULT_MAX_FREQ; else maxFreq = config.frequency_IF2; break; @@ -80,7 +80,7 @@ void update_min_max_freq(void) #endif case M_GENLOW: minFreq = 0; - maxFreq = 350000000; + maxFreq = DEFAULT_MAX_FREQ; break; case M_HIGH: #ifdef __ULTRA_SA__ @@ -135,7 +135,7 @@ void reset_settings(int m) setting.repeat = 1; setting.tracking_output = false; setting.measurement = M_OFF; - setting.frequency_IF = 433600000; + setting.frequency_IF = DEFAULT_IF; setting.auto_IF = true; setting.offset = 0.0; setting.trigger = T_AUTO; @@ -158,7 +158,7 @@ void reset_settings(int m) minFreq = 0; maxFreq = 4000000000; set_sweep_frequency(ST_START, (uint32_t) 0); - set_sweep_frequency(ST_STOP, (uint32_t) 350000000); + set_sweep_frequency(ST_STOP, (uint32_t) DEFAULT_MAX_FREQ); setting.attenuate = 0.0; // <---------------- WARNING ----------------- setting.auto_attenuation = false; // <---------------- WARNING ----------------- setting.sweep_time_us = 0; @@ -182,8 +182,8 @@ void reset_settings(int m) minFreq = 00000000; maxFreq = 2000000000; #else - minFreq = 10*config.setting_frequency_10mhz; - maxFreq = 1200*config.setting_frequency_10mhz; + minFreq = 136*config.setting_frequency_10mhz; + maxFreq = 1150*config.setting_frequency_10mhz; #endif set_sweep_frequency(ST_START, minFreq); set_sweep_frequency(ST_STOP, maxFreq); @@ -937,7 +937,7 @@ void calculate_step_delay(void) if (actual_rbw_x10 >= 2700) { SI4432_step_delay = 400; SI4432_offset_delay = 100; } else if (actual_rbw_x10 >= 800) { SI4432_step_delay = 500; SI4432_offset_delay = 100; } else if (actual_rbw_x10 >= 250) { SI4432_step_delay = 1000; SI4432_offset_delay = 100; } - else if (actual_rbw_x10 >= 30) { SI4432_step_delay = 5000; SI4432_offset_delay = 100; } + else if (actual_rbw_x10 >= 30) { SI4432_step_delay = 15000; SI4432_offset_delay = 100; } else { SI4432_step_delay = 20000; SI4432_offset_delay =1600; } #endif if (setting.step_delay_mode == SD_PRECISE) // In precise mode wait twice as long for RSSI to stabalize @@ -1448,8 +1448,8 @@ search_maximum(int m, int center, int span) } //static int spur_old_stepdelay = 0; -static const unsigned int spur_IF = 433600000; // The IF frequency for which the spur table is value -static const unsigned int spur_alternate_IF = 434100000; // if the frequency is found in the spur table use this IF frequency +static const unsigned int spur_IF = DEFAULT_IF; // The IF frequency for which the spur table is value +static const unsigned int spur_alternate_IF = DEFAULT_SPUR_IF; // if the frequency is found in the spur table use this IF frequency static const int spur_table[] = // Frequencies to avoid { 117716000, @@ -1706,7 +1706,7 @@ pureRSSI_t perform(bool break_on_operation, int i, uint32_t f, int tracking) modulation_delay += config.cor_nfm; // -17 default // modulation_index = 0; // default value } - if ((setting.mode == M_GENLOW && f > 480000000 - 433000000) || + if ((setting.mode == M_GENLOW && f > 480000000 - DEFAULT_IF) || (setting.mode == M_GENHIGH && f > 480000000) ) modulation_index += 2; current_fm_modulation = (int *)fm_modulation[modulation_index]; @@ -1772,7 +1772,7 @@ modulation_again: local_IF = 0; else { if (setting.auto_IF) - local_IF = setting.spur_removal ? 433600000 : spur_IF; + local_IF = setting.spur_removal ? DEFAULT_IF : spur_IF; else local_IF = setting.frequency_IF; } @@ -1868,8 +1868,8 @@ modulation_again: #define IF_2 config.frequency_IF2 // First IF in Ultra SA mode set_freq (2, config.frequency_IF2 + lf); // Scanning LO up to IF2 - set_freq (3, config.frequency_IF2 - 433800000); // Down from IF2 to fixed second IF in Ultra SA mode - set_freq (SI4432_LO, 433800000); // Second IF fixed in Ultra SA mode + set_freq (3, config.frequency_IF2 - DEFAULT_IF); // Down from IF2 to fixed second IF in Ultra SA mode + set_freq (SI4432_LO, DEFAULT_IF); // Second IF fixed in Ultra SA mode #else #ifdef __SI4432__ if (setting.mode == M_LOW && !setting.tracking && S_STATE(setting.below_IF)) // if in low input mode and below IF @@ -1880,23 +1880,26 @@ modulation_again: #ifdef __ADF4351__ // START_PROFILE; if (setting.mode == M_LOW) { - if (i > 0 && setting.frequency_step < 1000) { - set_freq (SI4463_RX, setting.frequency_IF - setting.frequency_step*i); // sweep RX, local_IF = 0 in high mode - } else { - uint32_t extra_IF = local_IF; - if (config.frequency_IF2 != 0) { - extra_IF = config.frequency_IF2; - set_freq (ADF4351_LO2, config.frequency_IF2 - local_IF); // Down from IF2 to fixed second IF in Ultra SA mode - } - if (!setting.tracking && S_STATE(setting.below_IF)) { // if in low input mode and below IF - if (lf > extra_IF) - set_freq (ADF4351_LO, lf - extra_IF); // set LO SI4432 to below IF frequency + if (i > 0 && setting.frequency_step < 3500) { + if (S_STATE(setting.below_IF)) + set_freq (SI4463_RX, setting.frequency_IF + setting.frequency_step*i); // sweep RX, local_IF = 0 in high mode else - set_freq (ADF4351_LO, extra_IF-lf); // set LO SI4432 to below IF frequency - } else - set_freq (ADF4351_LO, extra_IF+lf); // otherwise to above IF + set_freq (SI4463_RX, setting.frequency_IF - setting.frequency_step*i); // sweep RX, local_IF = 0 in high mode + } else { + uint32_t extra_IF = local_IF; + if (config.frequency_IF2 != 0) { + extra_IF = config.frequency_IF2; + set_freq (ADF4351_LO2, config.frequency_IF2 - local_IF); // Down from IF2 to fixed second IF in Ultra SA mode + } + if (!setting.tracking && S_STATE(setting.below_IF)) { // if in low input mode and below IF + if (lf > extra_IF) + set_freq (ADF4351_LO, lf - extra_IF); // set LO SI4432 to below IF frequency + else + set_freq (ADF4351_LO, extra_IF-lf); // set LO SI4432 to below IF frequency + } else + set_freq (ADF4351_LO, extra_IF+lf); // otherwise to above IF } - } else if (setting.mode == M_HIGH) { + } else if (setting.mode == M_HIGH) { set_freq (SI4463_RX, lf); // sweep RX, local_IF = 0 in high mode } // STOP_PROFILE; @@ -3347,7 +3350,7 @@ void test_prepare(int i) { setting.tracking = false; //Default test setup setting.atten_step = false; - setting.frequency_IF = 433600000; // Default frequency + setting.frequency_IF = DEFAULT_IF; // Default frequency setting.auto_IF = true; setting.auto_attenuation = false; switch(test_case[i].setup) { // Prepare test conditions @@ -3369,7 +3372,7 @@ common_silent: set_mode(M_LOW); setting.tracking = true; //Sweep BPF setting.auto_IF = false; - setting.frequency_IF = 433900000; // Center on SAW filters + setting.frequency_IF = DEFAULT_IF; // Center on SAW filters set_refer_output(2); goto common; case TP_10MHZ: // 10MHz input @@ -3499,7 +3502,7 @@ void self_test(int test) reset_settings(M_LOW); test_prepare(TEST_SILENCE); setting.auto_IF = false; - setting.frequency_IF=433600000; + setting.frequency_IF=DEFAULT_IF; setting.frequency_step = 30000; if (setting.test_argument > 0) setting.frequency_step=setting.test_argument; @@ -3516,7 +3519,7 @@ void self_test(int test) f += setting.frequency_step; shell_printf("\n\rStarting with %4.2f, %4.2f and IF at %d and step of %d\n\r", p2, p1, setting.frequency_IF, setting.frequency_step ); f = 400000; - while (f < 350000000) { + while (f < DEFAULT_MAX_FREQ) { p = PURE_TO_float(perform(false, 1, f, false)); #define SPUR_DELTA 6 if ( p2 < p1 - SPUR_DELTA && p < p1 - SPUR_DELTA) { @@ -3559,7 +3562,7 @@ void self_test(int test) in_selftest = true; // reset_settings(M_LOW); setting.auto_IF = false; - setting.frequency_IF=433600000; + setting.frequency_IF=DEFAULT_IF; ui_mode_normal(); test_prepare(TEST_RBW); setting.step_delay = 8000; @@ -3672,12 +3675,12 @@ void self_test(int test) case 2: reset_settings(M_LOW); set_sweep_frequency(ST_START, 300000000); - set_sweep_frequency(ST_STOP, 350000000); + set_sweep_frequency(ST_STOP, DEFAULT_MAX_FREQ); break; case 3: reset_settings(M_HIGH); set_sweep_frequency(ST_START, 300000000); - set_sweep_frequency(ST_STOP, 350000000); + set_sweep_frequency(ST_STOP, DEFAULT_MAX_FREQ); break; case 4: reset_settings(M_GENLOW); diff --git a/si4432.c b/si4432.c index ee40243..88fb5aa 100644 --- a/si4432.c +++ b/si4432.c @@ -1090,7 +1090,7 @@ void ADF4351_prep_frequency(int channel, unsigned long freq, int drive) // freq // if (channel == 0) RFout=freq/config.setting_frequency_10mhz; // To MHz // else - // RFout=freq/1000002.764; // To MHz +// RFout=freq/1000210; // To MHz if (RFout >= 2200) { OutputDivider = 1; @@ -1243,6 +1243,21 @@ int SI4463_frequency_changed = false; #include +#define SI4463_READ_CTS ((palReadPort(GPIOC)>>14)&1) + +int SI4463_wait_for_cts(void) +{ + if (SI4463_READ_CTS) + return 1; + while (!SI4463_READ_CTS) { +// ili9341_drawstring_7x13("Waiting ", 50, 200); + my_microsecond_delay(10); + } +// ili9341_drawstring_7x13("Proceed ", 50, 200); + return 1; +} + + void SI4463_write_byte(uint8_t ADR, uint8_t DATA) { set_SPI_mode(SPI_MODE_SI); @@ -1307,6 +1322,14 @@ uint8_t SI4463_read_byte( uint8_t ADR ) uint8_t SI4463_get_response(void* buff, uint8_t len) { uint8_t cts = 0; +#if 1 + cts = SI4463_READ_CTS; + if (!cts) { + return false; + } +// if (len == 0) +// return true; +#endif set_SPI_mode(SPI_MODE_SI); // if (SI4432_guard) // while(1) ; @@ -1348,8 +1371,12 @@ uint8_t SI4463_wait_response(void* buff, uint8_t len, uint8_t use_timeout) void SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen) { +#if 0 if(SI4463_wait_response(NULL, 0, true)) // Make sure it's ok to send a command - { +#else + if (SI4463_wait_for_cts()) +#endif + { // set_SPI_mode(SPI_MODE_SI); palClearPad(GPIOB, GPIOB_RX_SEL); my_microsecond_delay(MIN_DELAY); @@ -1360,11 +1387,21 @@ void SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen) // my_microsecond_delay(MIN_DELAY); palSetPad(GPIOB, GPIOB_RX_SEL); my_microsecond_delay(MIN_DELAY); +#if 0 if(((uint8_t*)data)[0] == SI446X_CMD_IRCAL) // If we're doing an IRCAL then wait for its completion without a timeout since it can sometimes take a few seconds +#if 0 SI4463_wait_response(NULL, 0, false); - else if(out != NULL) { // If we have an output buffer then read command response into it - if (((uint8_t*)data)[0] == SI446X_CMD_GET_MODEM_STATUS) - my_microsecond_delay(18); // Prevent extra wait cycles +#else + SI4463_wait_for_cts(); +#endif + else +#endif +#if 1 + SI4463_wait_for_cts(); +#endif + if(out != NULL) { // If we have an output buffer then read command response into it +// if (((uint8_t*)data)[0] == SI446X_CMD_GET_MODEM_STATUS) +// my_microsecond_delay(18); // Prevent extra wait cycles SI4463_wait_response(out, outLen, true); } } @@ -1397,14 +1434,15 @@ static const uint8_t SI4463_config[] = RADIO_CONFIGURATION_DATA_ARRAY; #ifdef __SI4468__ #undef RADIO_CONFIG_H_ #undef RADIO_CONFIGURATION_DATA_ARRAY -#include "radio_config_Si4468_850kHz_fast.h" +#include "radio_config_Si4468_850kHz.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#undef RF_MODEM_AGC_CONTROL_1 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase -#undef RF_MODEM_RSSI_JUMP_THRESH_4 -#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x45 // Increase RSSI reported value with 2.5dB +//#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging +//#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x06, 0x18, 0x10, 0x40 + +//#undef RF_MODEM_AGC_CONTROL_1 +//#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase +//#undef RF_MODEM_RSSI_JUMP_THRESH_4 +//#define RF_MODEM_RSSI_JUMP_THRESH_4 0x11, 0x20, 0x04, 0x4B, 0x06, 0x09, 0x10, 0x45 // Increase RSSI reported value with 2.5dB static const uint8_t SI4468_config[] = RADIO_CONFIGURATION_DATA_ARRAY; #endif @@ -1437,7 +1475,7 @@ void SI4463_start_rx(uint8_t CHANNEL) 0, 0, 0, - SI446X_CMD_START_RX_ARG_NEXT_STATE1_RXTIMEOUT_STATE_ENUM_NOCHANGE, + 8, SI446X_CMD_START_RX_ARG_NEXT_STATE2_RXVALID_STATE_ENUM_RX, SI446X_CMD_START_RX_ARG_NEXT_STATE3_RXINVALID_STATE_ENUM_RX }; @@ -1491,6 +1529,16 @@ void Si446x_getInfo(si446x_info_t* info) info->func = data[5]; } +uint8_t SI4463_get_device_status() +{ + uint8_t data[2] = + { + SI446X_CMD_ID_REQUEST_DEVICE_STATE, 0, 0 + }; + SI4463_do_api(data, 1, data, SI446X_CMD_REPLY_COUNT_REQUEST_DEVICE_STATE); + return(data[0]); +} + // Read a fast response register @@ -1503,7 +1551,8 @@ uint8_t getFRR(uint8_t reg) // Get current radio state si446x_state_t getState(void) { - uint8_t state = getFRR(SI446X_CMD_READ_FRR_B); + SI4463_wait_for_cts(); + uint8_t state = getFRR(SI446X_CMD_READ_FRR_B); if(state == SI446X_STATE_TX_TUNE) state = SI446X_STATE_TX; else if(state == SI446X_STATE_RX_TUNE) @@ -1538,9 +1587,10 @@ int16_t Si446x_RSSI(void) }; // volatile si446x_state_t s = getState(); //START_PROFILE; - if (SI4432_step_delay /* && ADF4351_frequency_changed */) { + if (SI4432_step_delay && (ADF4351_frequency_changed || SI4463_frequency_changed) ) { my_microsecond_delay(SI4432_step_delay); ADF4351_frequency_changed = false; + SI4463_frequency_changed = false; } int i = 3; //setting.repeat; @@ -1793,8 +1843,7 @@ uint8_t SI4463_RBW_850kHz[] = // -------------- 0.2 kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_200Hz_fast.h" - +#include "radio_config_Si4468_200Hz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_02kHz[] = @@ -1803,11 +1852,7 @@ static const uint8_t SI4463_RBW_02kHz[] = // -------------- 1kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_1kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_1kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_1kHz[] = @@ -1815,11 +1860,7 @@ static const uint8_t SI4463_RBW_1kHz[] = // -------------- 3 kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_3kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_3kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_3kHz[] = @@ -1827,11 +1868,7 @@ static const uint8_t SI4463_RBW_3kHz[] = // -------------- 10 kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_10kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_10kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_10kHz[] = @@ -1839,11 +1876,7 @@ static const uint8_t SI4463_RBW_10kHz[] = // -------------- 30 kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_30kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_30kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_30kHz[] = @@ -1851,11 +1884,7 @@ static const uint8_t SI4463_RBW_30kHz[] = // -------------- 100kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_100kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_100kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_100kHz[] = @@ -1864,11 +1893,7 @@ static const uint8_t SI4463_RBW_100kHz[] = // -------------- 300kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_300kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_300kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_300kHz[] = @@ -1877,11 +1902,7 @@ static const uint8_t SI4463_RBW_300kHz[] = // -------------- 850kHz ---------------------------- #undef RADIO_CONFIG_H_ -#include "radio_config_Si4468_850kHz_fast.h" -#undef RF_MODEM_RAW_CONTROL_10 // Override RSSI averaging -#define RF_MODEM_RAW_CONTROL_10 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x04, 0x01, 0x00, 0xFF, 0x08, 0x18, 0x10, 0x40 -#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0x92 // Override AGC gain increase - +#include "radio_config_Si4468_850kHz.h" #include "radio_config_Si4468_short.h" static const uint8_t SI4463_RBW_850kHz[] = @@ -1917,20 +1938,42 @@ static pureRSSI_t SI4463_RSSI_correction = float_TO_PURE_RSSI(-120); uint16_t SI4463_force_RBW(int f) { +#if 0 + SI_SDN_LOW; + my_microsecond_delay(1000); + SI_SDN_HIGH; + my_microsecond_delay(1000); + SI_SDN_LOW; + my_microsecond_delay(14000); +#else setState(SI446X_STATE_READY); my_microsecond_delay(200); - +#endif uint8_t *config = RBW_choices[f].reg; uint16_t i=0; while(config[i] != 0) { SI4463_do_api((void *)&config[i+1], config[i], NULL, 0); i += config[i]+1; - my_microsecond_delay(100); + my_microsecond_delay(200); } SI4463_clear_int_status(); +retry: SI4463_start_rx(0); - my_microsecond_delay(1000); + my_microsecond_delay(15000); + si446x_state_t s = getState(); + if (s != SI446X_STATE_RX) { + + SI4463_start_rx(0); + my_microsecond_delay(1000000); + si446x_state_t s = getState(); + if (s != SI446X_STATE_RX) { + ili9341_drawstring_7x13("Waiting for RX", 50, 200); + my_microsecond_delay(3000000); + goto retry; + } + ili9341_drawstring_7x13("Waiting done ", 50, 200); + } SI4463_RSSI_correction = float_TO_PURE_RSSI(RBW_choices[f].RSSI_correction_x_10 - 1200)/10; // Set RSSI correction return RBW_choices[f].RBWx10; // RBW achieved by SI4463 in kHz * 10 } @@ -1947,41 +1990,45 @@ uint16_t SI4463_SET_RBW(uint16_t WISH) { #define Npresc 1 // 0=low / 1=High performance mode - +static int prev_band = -1; void SI4463_set_freq(uint32_t freq, uint32_t step_size) { - int band; + int band = -1; int outdiv; uint32_t offs = ((freq / 1000)* 0) / 1000; float RFout=(freq+offs)/1000000.0; // To MHz - if (RFout >= 822) { // till 1140MHz + if (RFout >= 822 && RFout <= 1140) { // till 1140MHz band = 0; outdiv = 4; -#if 1 // band 4 does not function - } else if (RFout >= 568) { // works till 758MHz - band = 6; +#if 0 // band 4 does not function + } else if (RFout >= 568 && RFout <= 758 ) { // works till 758MHz + band = 4; outdiv = 6; #endif - } else if (RFout >= 420) { // works till 568MHz + } else if (RFout >= 420 && RFout <= 568) { // works till 568MHz band = 2; outdiv = 8; - } else if (RFout >= 329) { // works till 454MHz + } else if (RFout >= 329 && RFout <= 454) { // works till 454MHz band = 1; outdiv = 10; - } else if (RFout >= 274) { // to 339 + } else if (RFout >= 274 && RFout <= 339) { // to 339 band = 3; outdiv = 12; - } else { // 136 { // To 190 + } else if (RFout >= 136 && RFout <= 190){ // 136 { // To 190 band = 5; outdiv = 24; } - int32_t R = (RFout * outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco) - 1; + if (band == -1) + return; + int32_t R = (RFout * outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco) - 1; // R between 0x00 and 0x7f (127) float MOD = 520251.0; int32_t F = (((RFout * outdiv) / (Npresc ? 2*freq_xco : 4*freq_xco)) - R) * MOD; int S = (int)(step_size / 14.305); if (S == 0) S = 1; + setState(SI446X_STATE_READY); + my_microsecond_delay(100); /* // Set properties: RF_FREQ_CONTROL_INTE_8 @@ -1999,8 +2046,7 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size) // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. */ - // #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x4B, 0x08, 0x00, 0x00, 0x00, 0x51, 0x20, 0xFE - + // #define RF_FREQ_CONTROL_INTE_8_1 0x11, 0x40, 0x08, 0x00, 0x41, 0x0D, 0xA9, 0x5A, 0x4E, 0xC5, 0x20, 0xFE uint8_t data[] = { 0x11, 0x40, 0x08, 0x00, (uint8_t) R, // R data[4] @@ -2010,11 +2056,14 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size) (uint8_t) ((S>> 8) & 255), // Step size data[8] .. data[9] (uint8_t) ((S ) & 255), // Step size data[8] .. data[9] 0x20, // Window gate - 0xFE // Adj count + 0xFF // Adj count }; -// setState(SI446X_STATE_TX_TUNE); -// my_microsecond_delay(200); + + + SI4463_do_api(data, sizeof(data), NULL, 0); + + if (band != prev_band) { /* // Set properties: RF_MODEM_CLKGEN_BAND_1 // Number of properties: 1 @@ -2024,34 +2073,49 @@ void SI4463_set_freq(uint32_t freq, uint32_t step_size) // Descriptions: // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. */ - #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A + // #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A uint8_t data2[] = { 0x11, 0x20, 0x01, 0x51, - (uint8_t)(band + (Npresc ? 0x08 : 0)) // 0x08 for high performance mode + 0x10 + (uint8_t)(band + (Npresc ? 0x08 : 0)) // 0x08 for high performance mode, 0x10 to skip recal }; - SI4463_do_api(data2, sizeof(data2), NULL, 0); + SI4463_do_api(data2, sizeof(data2), NULL, 0); + my_microsecond_delay(30000); + prev_band = band; + } + // SI4463_clear_int_status(); retry: SI4463_start_rx(0); - my_microsecond_delay(2000); + my_microsecond_delay(200); si446x_state_t s = getState(); if (s != SI446X_STATE_RX) { + SI4463_start_rx(0); my_microsecond_delay(1000000); - goto retry; + si446x_state_t s = getState(); + if (s != SI446X_STATE_RX) { + my_microsecond_delay(3000000); + goto retry; + } } + SI4463_frequency_changed = true; } void SI4463_init(void) { - volatile int16_t RSSI; reset: SI_SDN_LOW; - my_microsecond_delay(1000); + my_microsecond_delay(100); SI_SDN_HIGH; my_microsecond_delay(1000); SI_SDN_LOW; - my_microsecond_delay(6000); + my_microsecond_delay(1000); + ili9341_set_foreground(BRIGHT_COLOR_GREEN); + while (!SI4463_READ_CTS) { + ili9341_drawstring_7x13("Waiting", 50, 200); + my_microsecond_delay(100); + } + ili9341_drawstring_7x13("Proceed", 50, 200); #if 0 @@ -2064,12 +2128,23 @@ for(uint16_t i=0;iparam_1.f = rbwsel_x10[data]*100.0; + b->param_1.u = rbwsel_x10[data]*100; b->icon = setting.rbw_x10 == rbwsel_x10[data] ? BUTTON_ICON_GROUP_CHECKED : BUTTON_ICON_GROUP; return; } @@ -1440,13 +1440,13 @@ static const menuitem_t menu_average[] = { static const menuitem_t menu_rbw[] = { { MT_ADV_CALLBACK, 0, " AUTO", menu_rbw_acb}, - { MT_ADV_CALLBACK, 1, "%3FkHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 2, "%3FkHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 3, "%4.0qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 4, "%4.0qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 5, "%4.0qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 6, "%4.0qHz", menu_rbw_acb}, - { MT_ADV_CALLBACK, 7, "%3FkHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 1, "%3.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 2, "%3.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 3, "%4.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 4, "%4.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 5, "%4.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 6, "%4.1qHz", menu_rbw_acb}, + { MT_ADV_CALLBACK, 7, "%3.1qHz", menu_rbw_acb}, { MT_CANCEL, 0, S_LARROW" BACK", NULL }, { MT_NONE, 0, NULL, NULL } // sentinel };