#undef RF_MODEM_RAW_CONTROL_10
#define RF_MODEM_RAW_CONTROL_10 GLOBAL_RF_MODEM_RAW_CONTROL

#undef RF_MODEM_AGC_CONTROL_1
#define RF_MODEM_AGC_CONTROL_1 GLOBAL_RF_MODEM_AGC_CONTROL

#undef RF_GPIO_PIN_CFG
#define RF_GPIO_PIN_CFG GLOBAL_GPIO_PIN_CFG

#undef RF_GLOBAL_CLK_CFG_1
#define RF_GLOBAL_CLK_CFG_1 GLOBAL_CLK_CFG

//#undef RF_MODEM_RAW_SEARCH2_2_1
//#define RF_MODEM_RAW_SEARCH2_2_1 0x11, 0x20, 0x02, 0x50, 0x94, 0x18
#if 1

#undef RADIO_CONFIGURATION_DATA_ARRAY
#define RADIO_CONFIGURATION_DATA_ARRAY { \
		0x10, RF_MODEM_MOD_TYPE_12_1,  \
/*      0x05, RF_MODEM_FREQ_DEV_0_1_1, */ \
      0x10, RF_MODEM_TX_RAMP_DELAY_12_1, \
/*        0x10, RF_MODEM_BCR_NCO_OFFSET_2_12_1,*/ \
/*        0x07, RF_MODEM_AFC_LIMITER_1_3_1,*/ \
/*        0x05, RF_MODEM_AGC_CONTROL_1_1,*/ \
/*        0x10, RF_MODEM_AGC_WINDOW_SIZE_12_1,*/ \
        0x0E, RF_MODEM_RAW_CONTROL_10, \
 /*     0x06, RF_MODEM_RAW_SEARCH2_2_1, */ \
 /*       0x06, RF_MODEM_SPIKE_DET_2_1, */ \
 /*       0x05, RF_MODEM_RSSI_MUTE_1_1, */ \
 /*       0x09, RF_MODEM_DSA_CTRL1_5_1, */ \
        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12_1, \
        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12_1, \
        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12_1, \
/*        0x05, RF_PA_TC_1_1, */ \
/*        0x0B, RF_SYNTH_PFDCP_CPFF_7_1, */ \
/*        0x0C, RF_FREQ_CONTROL_INTE_8_1, */ \
        0x00 \
 }
 #endif
 
