mirror of https://github.com/ttrftech/NanoVNA.git
For enable use external (LSE) clock generator need un comment in Makefile #UDEFS+= -DVNA_USE_LSE By default use internal (LSI) clock generator, but it stop then VNA power off For enable use external (LSE) clock generator, need install 32.768kHz clock quartz on PC14 and PC15 pins, it allow clock run while power off For enable use RTC in code uncomment in nanovna.h #define __USE_RTC__ This enable command 'time' usage: time [y|m|d|h|min|sec] 0-99 Example set 2020 year run 'time y 20' Add show current time in version screen Better use font size constants for all screen sizepull/130/head
DiSlord
6 years ago
parent
3491ba2fbe
commit
a8f36a4c5d
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/*
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* Copyright (c) 2014-2020, Dmitry (DiSlord) dislordlive@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "ch.h"
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#include "hal.h"
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#include "nanovna.h"
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#ifdef __USE_RTC__
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// Compact STM32 RTC time library
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#if HAL_USE_RTC == TRUE
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#error "Error VNA use self RTC lib, define HAL_USE_RTC = FALSE in halconf.h"
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#endif
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// Get RTC time as binary structure in 0x00HHMMSS
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uint32_t rtc_get_tr_bin(void){
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uint32_t tr = RTC->TR;
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uint32_t v = (tr&0x0F0F0F) + ((tr&0x707070)>>1) + ((tr&0x707070)>>3);
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return v;
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}
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// Get RTC time as binary structure in 0x00YYMMDD
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uint32_t rtc_get_dr_bin(void){
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uint32_t dr = RTC->DR;
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uint32_t v = (dr&0x000F0F0F) + ((dr&0x00F01030)>>1) + ((dr&0x00F01030)>>3);
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return v;// | ((dr&0xE000)<<15); // day of week at end
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}
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uint32_t rtc_get_FAT(void) {
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uint32_t fattime;
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uint32_t tr = rtc_get_tr_bin();
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uint32_t dr = rtc_get_dr_bin();
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fattime = ((tr>> 0)&0xFF) >> 1U; // Seconds / 2
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fattime |= ((tr>> 8)&0xFF) << 5U; // Minutes
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fattime |= ((tr>>16)&0xFF) << 11U; // Hour
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fattime |= ((dr>> 0)&0xFF) << 16U; // Day
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fattime |= ((dr>> 8)&0xFF) << 21U; // Month
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fattime |= (((dr>>16)&0xFF) + RTC_START_YEAR - 1980) << 25U; // Local year begin from 2000, fat from 1980
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return fattime;
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}
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void rtc_set_time(uint32_t dr, uint32_t tr) {
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// Beginning of configuration procedure.
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RTC->ISR |= RTC_ISR_INIT;
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while ((RTC->ISR & RTC_ISR_INITF) == 0)
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;
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// Writing the registers.
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RTC->TR = tr;
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RTC->DR = dr;
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RTC->ISR &= ~RTC_ISR_INIT;
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}
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#define RTC_PRER(a, s) ((((a) - 1) << 16) | ((s) - 1))
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// Initiate RTC clock, LSE or LSI generators initiate by ChibiOS !!!
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void rtc_init(void){
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// Disable write protection.
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RTC->WPR = 0xCA;
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RTC->WPR = 0x53;
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// If calendar has not been initialized yet then proceed with the initial setup.
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if (!(RTC->ISR & RTC_ISR_INITS)) {
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// Beginning of configuration procedure.
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RTC->ISR |= RTC_ISR_INIT;
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while ((RTC->ISR & RTC_ISR_INITF) == 0)
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;
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RTC->CR = 0;
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RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT.
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RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE);
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RTC->PRER = RTC_PRER(STM32_RTC_PRESA_VALUE, STM32_RTC_PRESS_VALUE);
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RTC->ISR &= ~RTC_ISR_INIT;
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}
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else
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RTC->ISR &= ~RTC_ISR_RSF;
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#if 0
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// ChibiOS init BDCR by self!!
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// For add auto select RTC source need rewrite it
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// see hal_lld_backup_domain_init() in hal_lld.c for every CPU
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// Default RTC clock is LSE, but it possible not launch if no quartz installed
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uint32_t rtc_drv = STM32_RTCSEL_LSI;
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uint32_t rtc_prer = RTC_PRER(40, 1000);
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// If LSE off try launch it
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if ((RCC->BDCR & RCC_BDCR_LSEON) == 0){
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// Try start LSE
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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uint32_t count = 65535;
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do{
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if (RCC->BDCR & RCC_BDCR_LSERDY) break;
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}while (--count);// Waits until LSE is stable. or count == 0
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}
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// Check, if LSE ready, then prepare it data
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if (RCC->BDCR & RCC_BDCR_LSERDY){
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rtc_drv = STM32_RTCSEL_LSE;
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rtc_prer = RTC_PRER(32, 1024);
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} else{
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// Try start LSI
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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;
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}
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PWR->CR |= PWR_CR_DBP;
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// If the backup domain hasn't been initialized yet then proceed with initialization or source different
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0 || (RCC->BDCR & STM32_RTCSEL_MASK)!=rtc_drv) {
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// Backup domain reset.
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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// Selects clock source.
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RCC->BDCR |= rtc_drv;
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// Disable write protection.
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RTC->WPR = 0xCA;
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RTC->WPR = 0x53;
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// Beginning of configuration procedure.
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RTC->ISR |= RTC_ISR_INIT;
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while ((RTC->ISR & RTC_ISR_INITF) == 0)
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;
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// Prescaler value loaded in registers.
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RTC->CR = 0;
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RTC->ISR = RTC_ISR_INIT; // Clearing all but RTC_ISR_INIT.
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RTC->PRER = rtc_prer;
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RTC->PRER = rtc_prer;
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// Finalizing of configuration procedure.
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RTC->ISR &= ~RTC_ISR_INIT;
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RCC->BDCR |= RCC_BDCR_RTCEN; // RTC clock enabled.
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}
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#endif
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}
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#endif
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