diff --git a/ADF7021.cpp b/ADF7021.cpp
index d5ebf54..a09fb64 100644
--- a/ADF7021.cpp
+++ b/ADF7021.cpp
@@ -1,6 +1,6 @@
 /*
  *   Copyright (C) 2016 by Jim McLaughlin KI6ZUM
- *   Copyright (C) 2016,2017 by Andy Uribe CA6JAU
+ *   Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
  *   Copyright (C) 2017 by Danilo DB4PLE 
  * 
  *   Some of the code is based on work of Guus Van Dooren PE1PLM:
@@ -232,6 +232,9 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
     case STATE_P25:
       AFC_OFFSET = AFC_OFFSET_P25;
       break;
+    case STATE_NXDN:
+      AFC_OFFSET = AFC_OFFSET_NXDN;
+      break;
     default:
       break;
   }
@@ -409,6 +412,33 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
 #endif
       break;
       
+    case STATE_NXDN:
+      // Dev: +1 symb 600 Hz, symb rate = 4800
+
+      ADF7021_REG3 = ADF7021_REG3_NXDN;
+      ADF7021_REG10 = ADF7021_REG10_NXDN;
+
+      // K=32
+      ADF7021_REG4  = (uint32_t) 0b0100                    << 0;   // register 4
+      ADF7021_REG4 |= (uint32_t) 0b011                     << 4;   // mode, 4FSK
+      ADF7021_REG4 |= (uint32_t) 0b0                       << 7;
+      ADF7021_REG4 |= (uint32_t) 0b11                      << 8;
+      ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_NXDN      << 10;  // Disc BW
+      ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_NXDN      << 20;  // Post dem BW
+      ADF7021_REG4 |= (uint32_t) 0b00                      << 30;  // IF filter (12.5 kHz)
+
+      ADF7021_REG13 = (uint32_t) 0b1101                    << 0;   // register 13
+      ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_NXDN   << 4;   // slicer threshold
+
+      ADF7021_REG2 = (uint32_t) 0b10                       << 28;  // invert data (and RC alpha = 0.5)
+      ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_NXDN / div2) << 19;  // deviation
+#if defined(ADF7021_DISABLE_RC_4FSK)
+      ADF7021_REG2 |= (uint32_t) 0b011                     << 4;   // modulation (4FSK)
+#else
+      ADF7021_REG2 |= (uint32_t) 0b111                     << 4;   // modulation (RC 4FSK)
+#endif
+      break;
+      
     default:
       break;
   }
@@ -593,7 +623,30 @@ void CIO::ifConf2(MMDVM_STATE modemState)
       ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2)  << 19;  // deviation
       ADF7021_REG2 |= (uint32_t) 0b111                     << 4;   // modulation (RC 4FSK)
       break;
-      
+
+    case STATE_NXDN:
+      // Dev: +1 symb 600 Hz, symb rate = 4800
+
+      ADF7021_REG3 = ADF7021_REG3_NXDN;
+      ADF7021_REG10 = ADF7021_REG10_NXDN;
+
+      // K=32
+      ADF7021_REG4  = (uint32_t) 0b0100                    << 0;   // register 4
+      ADF7021_REG4 |= (uint32_t) 0b011                     << 4;   // mode, 4FSK
+      ADF7021_REG4 |= (uint32_t) 0b0                       << 7;
+      ADF7021_REG4 |= (uint32_t) 0b11                      << 8;
+      ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_NXDN      << 10;  // Disc BW
+      ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_NXDN      << 20;  // Post dem BW
+      ADF7021_REG4 |= (uint32_t) 0b00                      << 30;  // IF filter (12.5 kHz)
+
+      ADF7021_REG13 = (uint32_t) 0b1101                    << 0;   // register 13
+      ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_NXDN   << 4;   // slicer threshold
+
+      ADF7021_REG2 = (uint32_t) 0b10                       << 28;  // invert data (and RC alpha = 0.5)
+      ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_NXDN / div2) << 19;  // deviation
+      ADF7021_REG2 |= (uint32_t) 0b111                     << 4;   // modulation (RC 4FSK)
+      break;
+
     default:
       break;
   }
diff --git a/IO.cpp b/IO.cpp
index ea0f491..c428392 100644
--- a/IO.cpp
+++ b/IO.cpp
@@ -1,6 +1,6 @@
 /*
  *   Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
- *   Copyright (C) 2016,2017 by Andy Uribe CA6JAU
+ *   Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
  *   Copyright (C) 2017 by Danilo DB4PLE 
  
  *   This program is free software; you can redistribute it and/or modify
@@ -47,6 +47,7 @@ m_watchdog(0U)
   DMR_pin(LOW);
   YSF_pin(LOW);
   P25_pin(LOW);
+  NXDN_pin(LOW);
   COS_pin(LOW);
   DEB_pin(LOW);
 
@@ -83,6 +84,7 @@ void CIO::selfTest()
       DMR_pin(ledValue);
       YSF_pin(ledValue);
       P25_pin(ledValue);
+      NXDN_pin(ledValue);
       COS_pin(ledValue);
 
       blinks++;
@@ -104,7 +106,7 @@ void CIO::process()
   if (m_started) {
     // Two seconds timeout
     if (m_watchdog >= 19200U) {
-      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF ||  m_modemState == STATE_P25) {
+      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF ||  m_modemState == STATE_P25 ||  m_modemState == STATE_NXDN) {
         m_modemState = STATE_IDLE;
         setMode(m_modemState);
       }
@@ -144,6 +146,8 @@ void CIO::process()
     scantime = SCAN_TIME;
   else if(m_modemState_prev == STATE_P25)
     scantime = SCAN_TIME;
+  else if(m_modemState_prev == STATE_NXDN)
+    scantime = SCAN_TIME;
   else
     scantime = SCAN_TIME;
 
@@ -184,6 +188,9 @@ void CIO::process()
       case STATE_P25:
         p25RX.databit(bit);
         break;
+      case STATE_NXDN:
+        nxdnRX.databit(bit);
+        break;
       default:
         break;
     }
@@ -211,6 +218,10 @@ void CIO::start()
     m_Modes[m_TotalModes] = STATE_P25;
     m_TotalModes++;
   }
+  if(m_nxdnEnable) {
+    m_Modes[m_TotalModes] = STATE_NXDN;
+    m_TotalModes++;
+  }
   
 #if defined(ENABLE_SCAN_MODE)
   if(m_TotalModes > 1)
@@ -291,6 +302,7 @@ void CIO::setMode(MMDVM_STATE modemState)
   DMR_pin(modemState   == STATE_DMR);
   YSF_pin(modemState   == STATE_YSF);
   P25_pin(modemState   == STATE_P25);
+  NXDN_pin(modemState   == STATE_NXDN);
 }
 
 void CIO::setDecode(bool dcd)