From 7908b0f9581ee1b1576c3cb95a8ddacccedb0f2c Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Fri, 24 Mar 2017 01:11:50 -0300 Subject: [PATCH] Preparing for scan mode --- ADF7021.cpp | 214 +++++++++++++++++++++++++++---------------------- Globals.h | 1 + IO.cpp | 28 ++++--- IO.h | 2 +- MMDVM_HS.cpp | 1 + MMDVM_HS.ino | 1 + SerialPort.cpp | 21 ++++- 7 files changed, 157 insertions(+), 111 deletions(-) diff --git a/ADF7021.cpp b/ADF7021.cpp index 52240df..4fb6348 100644 --- a/ADF7021.cpp +++ b/ADF7021.cpp @@ -129,7 +129,7 @@ uint16_t CIO::readRSSI() } #endif -void CIO::ifConf() +void CIO::ifConf(MMDVM_STATE modemState, bool reset) { float divider; uint8_t N_divider; @@ -145,10 +145,12 @@ void CIO::ifConf() uint32_t AFC_OFFSET = 0; // Toggle CE pin for ADF7021 reset - CE_pin(LOW); - delay_rx(); - CE_pin(HIGH); - delay_rx(); + if(reset) { + CE_pin(LOW); + delay_rx(); + CE_pin(HIGH); + delay_rx(); + } // Check frequency band if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) { @@ -172,14 +174,22 @@ void CIO::ifConf() div2 = 1U; } - if(m_dstarEnable) - AFC_OFFSET = 0; - else if(m_dmrEnable) - AFC_OFFSET = AFC_OFFSET_DMR; - else if(m_ysfEnable) - AFC_OFFSET = AFC_OFFSET_YSF; - else if(m_p25Enable) - AFC_OFFSET = AFC_OFFSET_P25; + switch (modemState) { + case STATE_DSTAR: + AFC_OFFSET = 0; + break; + case STATE_DMR: + AFC_OFFSET = AFC_OFFSET_DMR; + break; + case STATE_YSF: + AFC_OFFSET = AFC_OFFSET_YSF; + break; + case STATE_P25: + AFC_OFFSET = AFC_OFFSET_P25; + break; + default: + break; + } if( div2 == 1U ) divider = (m_frequency_rx - 100000 + AFC_OFFSET) / (ADF7021_PFD / 2U); @@ -221,93 +231,101 @@ void CIO::ifConf() ADF7021_TX_REG0 |= (uint32_t) N_divider << 19; // frequency; ADF7021_TX_REG0 |= (uint32_t) F_divider << 4; // frequency; - if (m_dstarEnable) { - // Dev: 1200 Hz, symb rate = 4800 + switch (modemState) { + case STATE_DSTAR: + // Dev: 1200 Hz, symb rate = 4800 - ADF7021_REG3 = ADF7021_REG3_DSTAR; - ADF7021_REG10 = ADF7021_REG10_DSTAR; + ADF7021_REG3 = ADF7021_REG3_DSTAR; + ADF7021_REG10 = ADF7021_REG10_DSTAR; - // K=32 - ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 - ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK - ADF7021_REG4 |= (uint32_t) 0b1 << 7; - ADF7021_REG4 |= (uint32_t) 0b10 << 8; - ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW - ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW - ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter - - ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 - ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold - - ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal - ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DSTAR / div2)<< 19; // deviation - ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK) - } - else if (m_dmrEnable) { - // Dev: +1 symb 648 Hz, symb rate = 4800 + // K=32 + ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 + ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK + ADF7021_REG4 |= (uint32_t) 0b1 << 7; + ADF7021_REG4 |= (uint32_t) 0b10 << 8; + ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW + ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW + ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter + + ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 + ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold + + ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal + ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DSTAR / div2)<< 19; // deviation + ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK) + break; + + case STATE_DMR: + // Dev: +1 symb 648 Hz, symb rate = 4800 - ADF7021_REG3 = ADF7021_REG3_DMR; - ADF7021_REG10 = ADF7021_REG10_DMR; - - // K=32 - ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 - ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK - ADF7021_REG4 |= (uint32_t) 0b0 << 7; - ADF7021_REG4 |= (uint32_t) 0b11 << 8; - ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW - ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW - ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter - - ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 - ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold - - ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data - ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DMR / div2) << 19; // deviation - ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) - } - else if (m_ysfEnable) { - // Dev: +1 symb 900 Hz, symb rate = 4800 - - ADF7021_REG3 = ADF7021_REG3_YSF; - ADF7021_REG10 = ADF7021_REG10_YSF; - - // K=28 - ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 - ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK - ADF7021_REG4 |= (uint32_t) 0b0 << 7; - ADF7021_REG4 |= (uint32_t) 0b11 << 8; - ADF7021_REG4 |= (uint32_t) (m_LoDevYSF ? ADF7021_DISC_BW_YSF_L : ADF7021_DISC_BW_YSF_H) << 10; // Disc BW - ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW - ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter - - ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 - ADF7021_REG13 |= (uint32_t) (m_LoDevYSF ? ADF7021_SLICER_TH_YSF_L : ADF7021_SLICER_TH_YSF_H) << 4; // slicer threshold - - ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data - ADF7021_REG2 |= (uint32_t) ((m_LoDevYSF ? ADF7021_DEV_YSF_L : ADF7021_DEV_YSF_H) / div2) << 19; // deviation - ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) - } - else if (m_p25Enable) { - // Dev: +1 symb 600 Hz, symb rate = 4800 - - ADF7021_REG3 = ADF7021_REG3_P25; - ADF7021_REG10 = ADF7021_REG10_P25; - - // K=32 - ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 - ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK - ADF7021_REG4 |= (uint32_t) 0b0 << 7; - ADF7021_REG4 |= (uint32_t) 0b11 << 8; - ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW - ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW - ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter - - ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 - ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold - - ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data - ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation - ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) + ADF7021_REG3 = ADF7021_REG3_DMR; + ADF7021_REG10 = ADF7021_REG10_DMR; + + // K=32 + ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 + ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK + ADF7021_REG4 |= (uint32_t) 0b0 << 7; + ADF7021_REG4 |= (uint32_t) 0b11 << 8; + ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW + ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW + ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter + + ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 + ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold + + ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data + ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DMR / div2) << 19; // deviation + ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) + break; + + case STATE_YSF: + // Dev: +1 symb 900 Hz, symb rate = 4800 + + ADF7021_REG3 = ADF7021_REG3_YSF; + ADF7021_REG10 = ADF7021_REG10_YSF; + + // K=28 + ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 + ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK + ADF7021_REG4 |= (uint32_t) 0b0 << 7; + ADF7021_REG4 |= (uint32_t) 0b11 << 8; + ADF7021_REG4 |= (uint32_t) (m_LoDevYSF ? ADF7021_DISC_BW_YSF_L : ADF7021_DISC_BW_YSF_H) << 10; // Disc BW + ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW + ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter + + ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 + ADF7021_REG13 |= (uint32_t) (m_LoDevYSF ? ADF7021_SLICER_TH_YSF_L : ADF7021_SLICER_TH_YSF_H) << 4; // slicer threshold + + ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data + ADF7021_REG2 |= (uint32_t) ((m_LoDevYSF ? ADF7021_DEV_YSF_L : ADF7021_DEV_YSF_H) / div2) << 19; // deviation + ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) + break; + + case STATE_P25: + // Dev: +1 symb 600 Hz, symb rate = 4800 + + ADF7021_REG3 = ADF7021_REG3_P25; + ADF7021_REG10 = ADF7021_REG10_P25; + + // K=32 + ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4 + ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK + ADF7021_REG4 |= (uint32_t) 0b0 << 7; + ADF7021_REG4 |= (uint32_t) 0b11 << 8; + ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW + ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW + ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter + + ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 + ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold + + ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data + ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation + ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) + break; + + default: + break; } // VCO/OSCILLATOR (REG1) @@ -363,6 +381,8 @@ void CIO::ifConf() // 3FSK/4FSK DEMOD (13) AD7021_control_word = ADF7021_REG13; Send_AD7021_control(); + + m_modemState_prev = modemState; } //====================================================================================================================== diff --git a/Globals.h b/Globals.h index 691931f..5b4fcc6 100644 --- a/Globals.h +++ b/Globals.h @@ -51,6 +51,7 @@ const uint16_t TX_RINGBUFFER_SIZE = 100U; const uint16_t RX_RINGBUFFER_SIZE = 120U; extern MMDVM_STATE m_modemState; +extern MMDVM_STATE m_modemState_prev; extern bool m_dstarEnable; extern bool m_dmrEnable; diff --git a/IO.cpp b/IO.cpp index 2ff9e3e..cf5c04e 100644 --- a/IO.cpp +++ b/IO.cpp @@ -98,16 +98,26 @@ void CIO::process() if (m_rxBuffer.getData() >= 1U) { m_rxBuffer.get(bit); + + switch (m_modemState_prev) { + case STATE_DSTAR: + dstarRX.databit(bit); + break; + case STATE_DMR: + dmrDMORX.databit(bit); + break; + case STATE_YSF: + ysfRX.databit(bit); + break; + case STATE_P25: + ysfRX.databit(bit); + break; + default: + break; + } - if(m_dstarEnable) - dstarRX.databit(bit); - else if(m_dmrEnable) - dmrDMORX.databit(bit); - else if(m_ysfEnable) - ysfRX.databit(bit); - else if(m_p25Enable) - p25RX.databit(bit); } + } void CIO::interrupt() @@ -146,8 +156,6 @@ void CIO::interrupt() void CIO::start() { - ifConf(); - if (m_started) return; diff --git a/IO.h b/IO.h index 62fdfea..8398e2d 100644 --- a/IO.h +++ b/IO.h @@ -87,7 +87,7 @@ public: // RF interface API void setTX(void); void setRX(void); - void ifConf(void); + void ifConf(MMDVM_STATE modemState, bool reset); void start(void); void startInt(void); diff --git a/MMDVM_HS.cpp b/MMDVM_HS.cpp index 5802e17..ab3f8a5 100644 --- a/MMDVM_HS.cpp +++ b/MMDVM_HS.cpp @@ -27,6 +27,7 @@ // Global variables MMDVM_STATE m_modemState = STATE_IDLE; +MMDVM_STATE m_modemState_prev = STATE_IDLE; bool m_dstarEnable = true; bool m_dmrEnable = true; diff --git a/MMDVM_HS.ino b/MMDVM_HS.ino index 8ed7240..17e957f 100644 --- a/MMDVM_HS.ino +++ b/MMDVM_HS.ino @@ -23,6 +23,7 @@ // Global variables MMDVM_STATE m_modemState = STATE_IDLE; +MMDVM_STATE m_modemState_prev = STATE_IDLE; bool m_dstarEnable = true; bool m_dmrEnable = true; diff --git a/SerialPort.cpp b/SerialPort.cpp index fb58f98..d8f876c 100644 --- a/SerialPort.cpp +++ b/SerialPort.cpp @@ -238,6 +238,16 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length) dmrDMORX.setColorCode(colorCode); io.setLoDevYSF(ysfLoDev); + + if(m_dstarEnable) + io.ifConf(STATE_DSTAR, true); + else if(m_dmrEnable) + io.ifConf(STATE_DMR, true); + else if(m_ysfEnable) + io.ifConf(STATE_YSF, true); + else if(m_p25Enable) + io.ifConf(STATE_P25, true); + io.start(); return 0U; @@ -253,7 +263,7 @@ uint8_t CSerialPort::setMode(const uint8_t* data, uint8_t length) if (modemState == m_modemState) return 0U; -if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25) + if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE_DMR && modemState != STATE_YSF && modemState != STATE_P25) return 4U; if (modemState == STATE_DSTAR && !m_dstarEnable) return 4U; @@ -263,7 +273,7 @@ if (modemState != STATE_IDLE && modemState != STATE_DSTAR && modemState != STATE return 4U; if (modemState == STATE_P25 && !m_p25Enable) return 4U; - + setMode(modemState); return 0U; @@ -323,7 +333,12 @@ void CSerialPort::setMode(MMDVM_STATE modemState) } m_modemState = modemState; - + + if ((modemState != STATE_IDLE) && (m_modemState_prev != modemState)) { + DEBUG1("setMode: configuring Hardware"); + io.ifConf(modemState, true); + } + io.setMode(); }