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@ -33,7 +33,7 @@
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volatile bool totx_request = false;
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volatile bool torx_request = false;
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volatile bool even = true;
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static uint32_t last_clk = 2;
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static uint32_t last_clk = 2U;
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volatile uint32_t AD7021_control_word;
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@ -100,7 +100,7 @@ void Send_AD7021_control2(bool doSle)
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uint16_t CIO::readRSSI()
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{
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uint32_t AD7021_RB;
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uint16_t RB_word = 0;
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uint16_t RB_word = 0U;
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int AD7021_counter;
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uint8_t RB_code, gain_code, gain_corr;
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@ -145,22 +145,22 @@ uint16_t CIO::readRSSI()
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switch(gain_code) {
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case 0b1010:
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gain_corr = 0;
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gain_corr = 0U;
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break;
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case 0b0110:
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gain_corr = 24;
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gain_corr = 24U;
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break;
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case 0b0101:
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gain_corr = 38;
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gain_corr = 38U;
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break;
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case 0b0100:
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gain_corr = 58;
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gain_corr = 58U;
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break;
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case 0b0000:
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gain_corr = 86;
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gain_corr = 86U;
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break;
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default:
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gain_corr = 0;
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gain_corr = 0U;
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break;
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}
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@ -173,12 +173,12 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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{
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float divider;
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG10 = 0;
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uint32_t ADF7021_REG13 = 0;
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uint32_t AFC_OFFSET = 0;
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uint32_t ADF7021_REG2 = 0U;
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uint32_t ADF7021_REG3 = 0U;
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uint32_t ADF7021_REG4 = 0U;
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uint32_t ADF7021_REG10 = 0U;
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uint32_t ADF7021_REG13 = 0U;
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int32_t AFC_OFFSET = 0;
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if(modemState != STATE_CWID)
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m_modemState_prev = modemState;
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@ -525,11 +525,11 @@ if(m_duplex && (modemState != STATE_CWID))
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#if defined(DUPLEX)
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void CIO::ifConf2(MMDVM_STATE modemState)
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{
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG10 = 0;
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uint32_t ADF7021_REG13 = 0;
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uint32_t ADF7021_REG2 = 0U;
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uint32_t ADF7021_REG3 = 0U;
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uint32_t ADF7021_REG4 = 0U;
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uint32_t ADF7021_REG10 = 0U;
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uint32_t ADF7021_REG13 = 0U;
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switch (modemState) {
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case STATE_DSTAR:
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@ -717,7 +717,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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void CIO::interrupt()
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{
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uint8_t bit = 0;
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uint8_t bit = 0U;
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if (!m_started)
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return;
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@ -740,7 +740,7 @@ void CIO::interrupt()
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}
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// we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
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if (m_tx && clk == 0) {
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if (m_tx && clk == 0U) {
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m_txBuffer.get(bit, m_control);
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even = !even;
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@ -782,19 +782,19 @@ void CIO::interrupt()
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}
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// we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
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if (!m_tx && clk == 1 && !m_duplex) {
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if (!m_tx && clk == 1U && !m_duplex) {
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if(RXD_pin())
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bit = 1;
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bit = 1U;
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else
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bit = 0;
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bit = 0U;
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m_rxBuffer.put(bit, m_control);
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}
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if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0) {
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if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
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// that is absolutely crucial in 4FSK, see datasheet:
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// enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
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delay_us(26);
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delay_us(26U);
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// SLE Pulse, should be moved out of here into class method
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SLE_pin(HIGH);
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@ -817,22 +817,22 @@ void CIO::interrupt()
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m_modeTimerCnt++;
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if(m_scanPauseCnt >= SCAN_PAUSE)
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m_scanPauseCnt = 0;
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m_scanPauseCnt = 0U;
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if(m_scanPauseCnt != 0)
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if(m_scanPauseCnt != 0U)
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m_scanPauseCnt++;
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}
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#if defined(DUPLEX)
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void CIO::interrupt2()
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{
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uint8_t bit = 0;
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uint8_t bit = 0U;
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if(m_duplex) {
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if(RXD2_pin())
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bit = 1;
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bit = 1U;
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else
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bit = 0;
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bit = 0U;
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m_rxBuffer.put(bit, m_control);
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}
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