From d58a0385eef601af22fbb7f03ad4fc31f794d916 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Fri, 14 Apr 2017 21:56:58 -0300 Subject: [PATCH 1/6] Update date of the firmware --- SerialPort.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/SerialPort.cpp b/SerialPort.cpp index 4cfb633..3f370c1 100644 --- a/SerialPort.cpp +++ b/SerialPort.cpp @@ -69,9 +69,9 @@ const uint8_t MMDVM_DEBUG4 = 0xF4U; const uint8_t MMDVM_DEBUG5 = 0xF5U; #if defined(ADF7021_N_VER) -#define DESCRIPTION "MMDVM_HS-ADF7021N 20170325 (D-Star/DMR/YSF/P25)" +#define DESCRIPTION "MMDVM_HS-ADF7021N 20170414 (D-Star/DMR/YSF/P25)" #else -#define DESCRIPTION "MMDVM_HS-ADF7021 20170325 (D-Star/DMR/YSF/P25)" +#define DESCRIPTION "MMDVM_HS-ADF7021 20170414 (D-Star/DMR/YSF/P25)" #endif #define concat(a, b, c) a " (Build: " b " " c ")" From e1c5e0b13afb352db7764b94f9de5534dd5c4bd1 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Fri, 28 Apr 2017 00:42:53 -0300 Subject: [PATCH 2/6] Testing new registers values --- ADF7021.h | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/ADF7021.h b/ADF7021.h index c8a56a1..8e2e751 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -46,6 +46,9 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #if defined(ADF7021_14_7456) // R = 4 +// DEMOD_CLK = 2.4576 MHz (DSTAR) +// DEMOD_CLK = 4.9152 MHz (DMR, P25) +// DEMOD_CLK = 7.3728 MHz (YSF) #define ADF7021_PFD 3686400.0 // PLL (REG 01) @@ -69,7 +72,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_REG3_P25 0x2A4C04D3 #else #define ADF7021_REG3_DMR 0x2A4C80D3 -#define ADF7021_REG3_YSF 0x2A4C80D3 +//#define ADF7021_REG3_YSF 0x2A4C80D3 +#define ADF7021_REG3_YSF 0x2A4CC093 #define ADF7021_REG3_P25 0x2A4C80D3 #endif @@ -78,13 +82,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_DISC_BW_DSTAR 522U // K=85 #define ADF7021_DISC_BW_DMR 393U // K=32 #define ADF7021_DISC_BW_YSF_L 394U // K=32 -#define ADF7021_DISC_BW_YSF_H 344U // K=28 +//#define ADF7021_DISC_BW_YSF_H 344U // K=28 +#define ADF7021_DISC_BW_YSF_H 516U // K=28 #define ADF7021_DISC_BW_P25 394U // K=32 // Post demodulator bandwith (REG 04) #define ADF7021_POST_BW_DSTAR 10U -#define ADF7021_POST_BW_DMR 100U -#define ADF7021_POST_BW_YSF 20U +#define ADF7021_POST_BW_DMR 150U +#define ADF7021_POST_BW_YSF 15U #define ADF7021_POST_BW_P25 6U // IF filter (REG 05) @@ -122,6 +127,9 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #elif defined(ADF7021_12_2880) // R = 2 +// DEMOD_CLK = 2.4576 MHz (DSTAR) +// DEMOD_CLK = 4.0960 MHz (DMR, P25) +// DEMOD_CLK = 6.1440 MHz (YSF) #define ADF7021_PFD 6144000.0 // PLL (REG 01) @@ -208,7 +216,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #else #define ADF7021_SLICER_TH_DSTAR 0U -#define ADF7021_SLICER_TH_DMR 54U +#define ADF7021_SLICER_TH_DMR 57U #define ADF7021_SLICER_TH_YSF_L 38U #define ADF7021_SLICER_TH_YSF_H 75U #define ADF7021_SLICER_TH_P25 52U From bd759e04fbd3535880a00cd896a0991c216c3bc5 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Fri, 28 Apr 2017 23:20:13 -0300 Subject: [PATCH 3/6] New registers values for DMR and YSF (14.7456 MHz) --- ADF7021.cpp | 2 +- ADF7021.h | 28 +++++++++++++++------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/ADF7021.cpp b/ADF7021.cpp index ac5d5fe..027050d 100644 --- a/ADF7021.cpp +++ b/ADF7021.cpp @@ -305,7 +305,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset) case STATE_YSF: // Dev: +1 symb 900 Hz, symb rate = 4800 - ADF7021_REG3 = ADF7021_REG3_YSF; + ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H); ADF7021_REG10 = ADF7021_REG10_YSF; // K=28 diff --git a/ADF7021.h b/ADF7021.h index 8e2e751..db421ed 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -47,8 +47,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // R = 4 // DEMOD_CLK = 2.4576 MHz (DSTAR) -// DEMOD_CLK = 4.9152 MHz (DMR, P25) -// DEMOD_CLK = 7.3728 MHz (YSF) +// DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25) +// DEMOD_CLK = 7.3728 MHz (YSF_H) #define ADF7021_PFD 3686400.0 // PLL (REG 01) @@ -68,12 +68,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_REG3_DSTAR 0x2A4C4193 #if defined(TEST_DAC) #define ADF7021_REG3_DMR 0x2A4C04D3 -#define ADF7021_REG3_YSF 0x2A4C04D3 +#define ADF7021_REG3_YSF_L 0x2A4C04D3 +#define ADF7021_REG3_YSF_H 0x2A4C0493 #define ADF7021_REG3_P25 0x2A4C04D3 #else #define ADF7021_REG3_DMR 0x2A4C80D3 -//#define ADF7021_REG3_YSF 0x2A4C80D3 -#define ADF7021_REG3_YSF 0x2A4CC093 +#define ADF7021_REG3_YSF_L 0x2A4C80D3 +#define ADF7021_REG3_YSF_H 0x2A4CC093 #define ADF7021_REG3_P25 0x2A4C80D3 #endif @@ -81,15 +82,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Bug in ADI evaluation software, use datasheet formula (4FSK) #define ADF7021_DISC_BW_DSTAR 522U // K=85 #define ADF7021_DISC_BW_DMR 393U // K=32 -#define ADF7021_DISC_BW_YSF_L 394U // K=32 -//#define ADF7021_DISC_BW_YSF_H 344U // K=28 +#define ADF7021_DISC_BW_YSF_L 393U // K=32 #define ADF7021_DISC_BW_YSF_H 516U // K=28 #define ADF7021_DISC_BW_P25 394U // K=32 // Post demodulator bandwith (REG 04) #define ADF7021_POST_BW_DSTAR 10U #define ADF7021_POST_BW_DMR 150U -#define ADF7021_POST_BW_YSF 15U +#define ADF7021_POST_BW_YSF 20U #define ADF7021_POST_BW_P25 6U // IF filter (REG 05) @@ -128,8 +128,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // R = 2 // DEMOD_CLK = 2.4576 MHz (DSTAR) -// DEMOD_CLK = 4.0960 MHz (DMR, P25) -// DEMOD_CLK = 6.1440 MHz (YSF) +// DEMOD_CLK = 4.0960 MHz (DMR, YSF_L, P25) +// DEMOD_CLK = 6.1440 MHz (YSF_H) #define ADF7021_PFD 6144000.0 // PLL (REG 01) @@ -149,11 +149,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_REG3_DSTAR 0x29EC4153 #if defined(TEST_DAC) #define ADF7021_REG3_DMR 0x29EC0493 -#define ADF7021_REG3_YSF 0x29EC0493 +#define ADF7021_REG3_YSF_L 0x29EC0493 +#define ADF7021_REG3_YSF_H 0x29EC0493 #define ADF7021_REG3_P25 0x29EC0493 #else #define ADF7021_REG3_DMR 0x29ECA093 -#define ADF7021_REG3_YSF 0x29ECA093 +#define ADF7021_REG3_YSF_L 0x29ECA093 +#define ADF7021_REG3_YSF_H 0x29ECA093 #define ADF7021_REG3_P25 0x29ECA093 #endif @@ -167,7 +169,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Post demodulator bandwith (REG 04) #define ADF7021_POST_BW_DSTAR 10U -#define ADF7021_POST_BW_DMR 100U +#define ADF7021_POST_BW_DMR 150U #define ADF7021_POST_BW_YSF 20U #define ADF7021_POST_BW_P25 6U From 68c69a5c2bc67a9a961e54bec2c10959eb43ea1e Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Sat, 29 Apr 2017 00:34:11 -0300 Subject: [PATCH 4/6] Updating slicer threshold for DMR (ADF7021N) --- ADF7021.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ADF7021.h b/ADF7021.h index db421ed..a1d7e75 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -210,7 +210,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #if defined(ADF7021_N_VER) #define ADF7021_SLICER_TH_DSTAR 0U -#define ADF7021_SLICER_TH_DMR 48U +#define ADF7021_SLICER_TH_DMR 51U #define ADF7021_SLICER_TH_YSF_L 32U #define ADF7021_SLICER_TH_YSF_H 63U #define ADF7021_SLICER_TH_P25 43U From 515dbe4a8d51ab7d464ec903a73dc6fecfc24222 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Sat, 29 Apr 2017 00:42:44 -0300 Subject: [PATCH 5/6] Updating slicer threshold for YSF (ADF7021N) --- ADF7021.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ADF7021.h b/ADF7021.h index a1d7e75..4bd10f7 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -211,8 +211,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_SLICER_TH_DSTAR 0U #define ADF7021_SLICER_TH_DMR 51U -#define ADF7021_SLICER_TH_YSF_L 32U -#define ADF7021_SLICER_TH_YSF_H 63U +#define ADF7021_SLICER_TH_YSF_L 35U +#define ADF7021_SLICER_TH_YSF_H 69U #define ADF7021_SLICER_TH_P25 43U #else From ea6ec4e87982f3b32ab02c33b79f490f9a5da4e0 Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Sat, 29 Apr 2017 01:26:30 -0300 Subject: [PATCH 6/6] Fix value for discriminator BW in YSF (12.288 MHz) --- ADF7021.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/ADF7021.h b/ADF7021.h index 4bd10f7..8992ddc 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -128,8 +128,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // R = 2 // DEMOD_CLK = 2.4576 MHz (DSTAR) -// DEMOD_CLK = 4.0960 MHz (DMR, YSF_L, P25) -// DEMOD_CLK = 6.1440 MHz (YSF_H) +// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25) #define ADF7021_PFD 6144000.0 // PLL (REG 01) @@ -163,7 +162,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Bug in ADI evaluation software, use datasheet formula (4FSK) #define ADF7021_DISC_BW_DSTAR 522U // K=85 #define ADF7021_DISC_BW_DMR 491U // K=32 -#define ADF7021_DISC_BW_YSF_L 493U // K=32 +#define ADF7021_DISC_BW_YSF_L 491U // K=32 #define ADF7021_DISC_BW_YSF_H 430U // K=28 #define ADF7021_DISC_BW_P25 493U // K=32