From 6df168a17dcabbe44f2044344cac2e329934d9b0 Mon Sep 17 00:00:00 2001
From: Andy CA6JAU <juribeparada@gmail.com>
Date: Sun, 20 Aug 2017 20:49:56 -0300
Subject: [PATCH] Fix YSF +1 sym deviation to 900 Hz (according to standard),
 and fix deviation values for 12.288 MHz TCXO

---
 ADF7021.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/ADF7021.h b/ADF7021.h
index 6880613..3806d7f 100644
--- a/ADF7021.h
+++ b/ADF7021.h
@@ -77,8 +77,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // Deviation of modulator (REG 02)
 #define ADF7021_DEV_DSTAR        43U
 #define ADF7021_DEV_DMR          23U
-#define ADF7021_DEV_YSF_L        18U
-#define ADF7021_DEV_YSF_H        36U
+#define ADF7021_DEV_YSF_L        16U
+#define ADF7021_DEV_YSF_H        32U
 #if defined(ENABLE_P25_WIDE)
 #define ADF7021_DEV_P25          32U
 #else
@@ -161,12 +161,12 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // Deviation of modulator (REG 02)
 #define ADF7021_DEV_DSTAR        26U
 #define ADF7021_DEV_DMR          14U
-#define ADF7021_DEV_YSF_L        11U
-#define ADF7021_DEV_YSF_H        21U
+#define ADF7021_DEV_YSF_L        10U
+#define ADF7021_DEV_YSF_H        19U
 #if defined(ENABLE_P25_WIDE)
-#define ADF7021_DEV_P25          21U
+#define ADF7021_DEV_P25          19U
 #else
-#define ADF7021_DEV_P25          14U
+#define ADF7021_DEV_P25          13U
 #endif
 
 // TX/RX CLOCK register (REG 03)