From 4f293ee84f80046c1e9c48b03ad5d50b6de70c9f Mon Sep 17 00:00:00 2001 From: Andy CA6JAU Date: Thu, 23 Mar 2017 22:06:04 -0300 Subject: [PATCH] Adding Jonathan support for low deviation in YSF --- ADF7021.cpp | 11 +++++++--- ADF7021.h | 57 +++++++++++++++----------------------------------- Config.h | 3 --- Globals.h | 2 ++ IO.cpp | 3 ++- IO.h | 2 ++ MMDVM_HS.cpp | 2 ++ MMDVM_HS.ino | 2 ++ SerialPort.cpp | 6 ++++++ 9 files changed, 41 insertions(+), 47 deletions(-) diff --git a/ADF7021.cpp b/ADF7021.cpp index b35fea4..52240df 100644 --- a/ADF7021.cpp +++ b/ADF7021.cpp @@ -276,15 +276,15 @@ void CIO::ifConf() ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK ADF7021_REG4 |= (uint32_t) 0b0 << 7; ADF7021_REG4 |= (uint32_t) 0b11 << 8; - ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_YSF << 10; // Disc BW + ADF7021_REG4 |= (uint32_t) (m_LoDevYSF ? ADF7021_DISC_BW_YSF_L : ADF7021_DISC_BW_YSF_H) << 10; // Disc BW ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13 - ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold + ADF7021_REG13 |= (uint32_t) (m_LoDevYSF ? ADF7021_SLICER_TH_YSF_L : ADF7021_SLICER_TH_YSF_H) << 4; // slicer threshold ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data - ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_YSF / div2) << 19; // deviation + ADF7021_REG2 |= (uint32_t) ((m_LoDevYSF ? ADF7021_DEV_YSF_L : ADF7021_DEV_YSF_H) / div2) << 19; // deviation ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) } else if (m_p25Enable) { @@ -398,4 +398,9 @@ void CIO::setRX() PTT_pin(LOW); } +void CIO::setLoDevYSF(bool on) +{ + m_LoDevYSF = on; +} + #endif diff --git a/ADF7021.h b/ADF7021.h index 29f898b..cb8e843 100644 --- a/ADF7021.h +++ b/ADF7021.h @@ -49,11 +49,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Deviation of modulator (REG 02) #define ADF7021_DEV_DSTAR 43U #define ADF7021_DEV_DMR 23U -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DEV_YSF 16U -#else -#define ADF7021_DEV_YSF 32U -#endif +#define ADF7021_DEV_YSF_L 16U +#define ADF7021_DEV_YSF_H 32U #define ADF7021_DEV_P25 22U // TX/RX CLOCK register (REG 03) @@ -66,11 +63,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Bug in ADI evaluation software, use datasheet formula (4FSK) #define ADF7021_DISC_BW_DSTAR 522U // K=85 #define ADF7021_DISC_BW_DMR 393U // K=32 -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DISC_BW_YSF 394U // K=32 -#else -#define ADF7021_DISC_BW_YSF 344U // K=28 -#endif +#define ADF7021_DISC_BW_YSF_L 394U // K=32 +#define ADF7021_DISC_BW_YSF_H 344U // K=28 #define ADF7021_DISC_BW_P25 394U // K=32 // Post demodulator bandwith (REG 04) @@ -125,11 +119,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Deviation of modulator (REG 02) #define ADF7021_DEV_DSTAR 32U #define ADF7021_DEV_DMR 17U -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DEV_YSF 12U -#else -#define ADF7021_DEV_YSF 24U -#endif +#define ADF7021_DEV_YSF_L 12U +#define ADF7021_DEV_YSF_H 24U #define ADF7021_DEV_P25 16U // TX/RX CLOCK register (REG 03) @@ -142,11 +133,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Bug in ADI evaluation software, use datasheet formula (4FSK) #define ADF7021_DISC_BW_DSTAR 597U // K=85 #define ADF7021_DISC_BW_DMR 393U // K=32 -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DISC_BW_YSF 394U // K=32 -#else -#define ADF7021_DISC_BW_YSF 344U // K=28 -#endif +#define ADF7021_DISC_BW_YSF_L 394U // K=32 +#define ADF7021_DISC_BW_YSF_H 344U // K=28 #define ADF7021_DISC_BW_P25 394U // K=32 // Post demodulator bandwith (REG 04) @@ -201,11 +189,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Deviation of modulator (REG 02) #define ADF7021_DEV_DSTAR 26U #define ADF7021_DEV_DMR 14U -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DEV_YSF 10U -#else -#define ADF7021_DEV_YSF 19U -#endif +#define ADF7021_DEV_YSF_L 10U +#define ADF7021_DEV_YSF_H 19U #define ADF7021_DEV_P25 14U // TX/RX CLOCK register (REG 03) @@ -218,11 +203,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf // Bug in ADI evaluation software, use datasheet formula (4FSK) #define ADF7021_DISC_BW_DSTAR 522U // K=85 #define ADF7021_DISC_BW_DMR 491U // K=32 -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_DISC_BW_YSF 493U // K=32 -#else -#define ADF7021_DISC_BW_YSF 430U // K=28 -#endif +#define ADF7021_DISC_BW_YSF_L 493U // K=32 +#define ADF7021_DISC_BW_YSF_H 430U // K=28 #define ADF7021_DISC_BW_P25 493U // K=32 // Post demodulator bandwith (REG 04) @@ -269,23 +251,18 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf #define ADF7021_SLICER_TH_DSTAR 0U #define ADF7021_SLICER_TH_DMR 48U -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_SLICER_TH_YSF 32U -#else -#define ADF7021_SLICER_TH_YSF 63U -#endif +#define ADF7021_SLICER_TH_YSF_L 32U +#define ADF7021_SLICER_TH_YSF_H 63U #define ADF7021_SLICER_TH_P25 43U #else #define ADF7021_SLICER_TH_DSTAR 0U #define ADF7021_SLICER_TH_DMR 54U -#if defined(ADF7021_YSF_HALF_DEV) -#define ADF7021_SLICER_TH_YSF 38U -#else -#define ADF7021_SLICER_TH_YSF 75U -#endif +#define ADF7021_SLICER_TH_YSF_L 38U +#define ADF7021_SLICER_TH_YSF_H 75U #define ADF7021_SLICER_TH_P25 52U + #endif #define bitRead(value, bit) (((value) >> (bit)) & 0x01) diff --git a/Config.h b/Config.h index b314ae5..a24d2ce 100644 --- a/Config.h +++ b/Config.h @@ -55,9 +55,6 @@ // #define STM32_USART1_HOST #define STM32_USB_HOST -// Enable Half Deviation mode in YSF (experimental) -// #define ADF7021_YSF_HALF_DEV - // Send RSSI value: // #define SEND_RSSI_DATA diff --git a/Globals.h b/Globals.h index bf3b072..691931f 100644 --- a/Globals.h +++ b/Globals.h @@ -57,6 +57,8 @@ extern bool m_dmrEnable; extern bool m_ysfEnable; extern bool m_p25Enable; +extern bool m_duplex; + extern bool m_tx; extern bool m_dcd; diff --git a/IO.cpp b/IO.cpp index 7a3ff86..2ff9e3e 100644 --- a/IO.cpp +++ b/IO.cpp @@ -35,7 +35,8 @@ m_rxBuffer(RX_RINGBUFFER_SIZE), m_txBuffer(TX_RINGBUFFER_SIZE), m_ledCount(0U), m_ledValue(true), -m_watchdog(0U) +m_watchdog(0U), +m_LoDevYSF(false) { Init(); diff --git a/IO.h b/IO.h index c75dbe9..62fdfea 100644 --- a/IO.h +++ b/IO.h @@ -82,6 +82,7 @@ public: uint8_t setFreq(uint32_t frequency_rx, uint32_t frequency_tx); void setMode(void); void setDecode(bool dcd); + void setLoDevYSF(bool ysfLoDev); // RF interface API void setTX(void); @@ -102,6 +103,7 @@ private: bool m_started; CBitRB m_rxBuffer; CBitRB m_txBuffer; + bool m_LoDevYSF; uint32_t m_ledCount; bool m_ledValue; diff --git a/MMDVM_HS.cpp b/MMDVM_HS.cpp index 2dcdae0..5802e17 100644 --- a/MMDVM_HS.cpp +++ b/MMDVM_HS.cpp @@ -33,6 +33,8 @@ bool m_dmrEnable = true; bool m_ysfEnable = true; bool m_p25Enable = true; +bool m_duplex = false; + bool m_tx = false; bool m_dcd = false; diff --git a/MMDVM_HS.ino b/MMDVM_HS.ino index 9bd112b..8ed7240 100644 --- a/MMDVM_HS.ino +++ b/MMDVM_HS.ino @@ -29,6 +29,8 @@ bool m_dmrEnable = true; bool m_ysfEnable = true; bool m_p25Enable = true; +bool m_duplex = false; + bool m_tx = false; bool m_dcd = false; diff --git a/SerialPort.cpp b/SerialPort.cpp index be167d6..fb58f98 100644 --- a/SerialPort.cpp +++ b/SerialPort.cpp @@ -191,6 +191,9 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length) { if (length < 13U) return 4U; + + bool ysfLoDev = (data[0U] & 0x08U) == 0x08U; + bool simplex = (data[0U] & 0x80U) == 0x80U; bool dstarEnable = (data[1U] & 0x01U) == 0x01U; bool dmrEnable = (data[1U] & 0x02U) == 0x02U; @@ -224,6 +227,8 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length) m_dmrEnable = dmrEnable; m_ysfEnable = ysfEnable; m_p25Enable = p25Enable; + + m_duplex = !simplex; dstarTX.setTXDelay(txDelay); ysfTX.setTXDelay(txDelay); @@ -232,6 +237,7 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length) dmrDMORX.setColorCode(colorCode); + io.setLoDevYSF(ysfLoDev); io.start(); return 0U;